JPS58212243A - Clock regenerating circuit in digital signal transmission - Google Patents

Abstract

PURPOSE:To generate a regenerative clock with less shift from a PLL with a simple constitution, by adding an RF level detecting circuit and the like to the titled circuit so as to make the input fed to a tank circuit constant even if a part of a transmitted time series signal is missing. CONSTITUTION:An RF digital signal from a regenerative digital input terminal 7 is demodulated at a demodulating circuit 8, and applied to an edge detecting circuit comprising an exclusive OR circuit 12 and a delay circuit 13 via an LPF10 to detect each edge part. A frequency being a natural number multiple of its edge detecting signal is extracted at a capacitor C1 and a coil L1 for a tank circuit and applied to the PLL17. Further, the level of a signal from the terminal 7 is detected at the RF level detecting circuit 9 and the consecuting time below a prescribed level not demodulated at the circuit 8 normally is discriminated at a time discriminating circuit 15. Further, an output is applied to an AND circuit 14 inputting an output of the edge detecting circuit, so as to make the input to the tank circuit constant, allowing to output a regenerative clock with less shift from the PLL17.

Description

[Detailed description of the invention]

The present invention relates to a clock regeneration circuit in digital signal transmission, and even if there is a part of the transmitted time-series digital signal missing due to dropout or the like, it can be configured simply and inexpensively by cutting off the input signal to the tank circuit. An object of the present invention is to provide a clock recovery circuit that can extract a recovered clock signal with less deviation from a phase-locked loop (PLL). Conventionally, digital video signals related to still IF images or partial moving images have been added as additional information to digital audio signals and recorded intermittently on the same track on an information recording disk (hereinafter referred to as "disk") in chronological order. It is known that (2) this disk is read and reproduced using changes in electrostatic volume or changes in the intensity of light. In this case, the transmitted digital signal is, for example, as shown schematically in FIG.
The 6-bit four-channel digital data (data of the digital audio signal and/or digital video signal) D1 to D1) are arranged in chronological order at the positions indicated by 4, and then the subsequent P, , P2 A 16-bit error correction code is placed at the positions indicated by , and a 23-bit burden check code (cyclic redundancy check code) is placed at the position indicated by CRC. Of the last 3 bits, the position indicated by Adr is placed with, for example, 1-bit data of the total 196-bit control signal, and the remaining 2 bits indicated by U are the user's bit and i.
A spare 1 called D± (2 bits are allocated for . from 5YNC above

[The digital signal that constitutes one frame with a total of 130 bits up to J is the repetition frequency (3), for example, 44.1 kHz, which is the same as the sampling frequency.
At a transmission bit rate of 5.733 Mb/s, the signals are synthesized in time series for each frame and transmitted. This time-series composite digital signal is an NFtZ (Non-Return-to-Zero) signal, which is a self-clockable MT;
Either perform further digital modulation such as ``M (Modified Frequency Modulation) or 3P\ (3 Position Modulation), and then perform frequency modulation, or perform frequency modulation without performing the above digital modulation, and then It is recorded as a series of intermittent pits on a disc using a light beam, etc. In this disc playback device, a reproduced digital signal having a frame structure as shown in Fig. 1 obtained by frequency demodulating the signal reproduced from the disc is used. A high-frequency (for example, about 5.733 MHz) clock signal that is phase-synchronized with the signal is regenerated from the signal using a clock regeneration circuit, and the synchronization signal in the regenerated digital signal is detected based on the clock signal obtained thereby. Write data to the memory circuit (4), etc. Figures 2 and 3 respectively show block diagrams of each side of the conventional clock recovery circuit. In both figures, the same components have the same designations. Numbers are attached.In Fig. 2, input terminal 1
It is shown in FIG. 4(A) that is reproduced from the disc.
The F digital signal passes through a demodulation circuit and a comparator, and then a reproduced digital signal with a frame structure as shown in FIG. 1 with a waveform shown in FIG. each edge of is detected,
The edge detection signal as shown in the same figure (q) or the tank circuit 3
supplied to The tank circuit 3 is configured to perform the same fi+4 frequency as a natural number multiple of the transmission bit rate (therefore, if it is 1 times the transmission bit rate, it is 5.733 Mllz), and its output signal ζ1 is shown in Fig. 4 (l). The signal is then supplied to the limiter 4, where the cutting width is limited and converted into a rectangular wave as shown in FIG. However, the digital signal played back from the disc has
This includes time (5) T141: fluctuation (jitter) due to uneven rotation of the disk, etc. In the circuit shown in the second diagram, the frequency fluctuation of the clock signal due to the jitter appears directly at the output terminal 5, so the bit jitter is included. It is easy to cause Conventionally, as shown in FIG. 3, a PLL 6 has been used in place of the limiter 4 to absorb the jitter component and output the clock signal to the output terminal 5. By the way, dropouts generally occur in reproduced signals from a disc due to defects on the disc, poor recording, or the like. During this dropout period (
(shown as T1 in Fig. 4(A)), the reproduced data will be different from that at the time of recording t', or a code error will be detected by the error check code, so at this time, the two types of error correction codes mentioned above will be detected. Most code errors can be corrected and restored to the original data by performing modulo 2 addition for each corresponding bit together with the digital data of the four channels. However, these signal processes are based on the premise that the clock signal is stably and accurately reproduced. (6) However, if the above-mentioned dropout time length is long, the clock information obtained from the reproduced digital signal also includes irregular noise components, and the tank circuit 30') Since Q is also a finite value, It may output a frequency that deviates considerably from the tuning center frequency. - 1,000, January, L6 has a fairly wide lock range when the input level is large. For example, when using NF, 564 manufactured by Sibu-Futaikus Co., Ltd. as a commercially available PLL, the lock range characteristic is ±12
When it is V, it is shown by curve I, and when it is ±6■, it is shown by curve ■.
It is indicated by. Therefore, no matter which power supply voltage is used, if the input level is 100 mV or more, the input level is
It can be seen that it has a wide locking range for OmV or less. For this reason, during the tuning from the tank circuit 3 that occurs when the dropout time described above is long, the PLT,
6 is locked, and the frequency of the output clock signal of PIJL6 also changes significantly. When a wide (7) wide frequency fluctuation of the clock signal occurs, the error correction circuit performs modulo 2 addition of the above-mentioned V correction code and the digital data of the four channels to correct and restore the code protection. In the meantime, the addition operation is performed on data that is different from the data that should originally be added, so the image becomes blue depending on whether correct correction and restoration are performed. Therefore, the present applicant previously proposed in Japanese Patent Application No. 56-79890 a 'voltage-controlled @1 type crystal oscillator, which has an extremely narrow range of output signal frequency change relative to the control voltage' as a voltage-controlled oscillator in the PLT, 6. (vcxo), 41 (PLL
By providing a switch circuit means for switching the output signal of the phase comparator in 6 to a substantially constant value, fluctuations in the clock frequency can be suppressed within a range that does not cause bit loss, and thus the above-mentioned long-term We have developed a clock regeneration circuit that prevents and stops the phenomenon of erroneous correction following false clock information from PLL 6 or tank circuit 3 when clock information cannot be obtained.However, the proposed clock regeneration circuit is a component such as a VCXO, and the circuit size is large, and the frequency fluctuation (8) of the clock signal actually generates an abnormal sound and is detected by the listener within a practically acceptable frequency fluctuation tolerance range. The problem was that it was unsuitable for use as a consumer clock regeneration circuit because it was much more strictly suppressed to a small size than the above.The present invention eliminates the above-mentioned drawbacks and also solves the above drawbacks. An embodiment of the clock regeneration circuit according to the present invention will be described below with reference to Figs. 6 and 7. Fig. 6 shows a circuit system diagram of an embodiment of the clock regeneration circuit according to the present invention. A high frequency frequency modulated digital signal (11.
After the frequency characteristics of the I-digital signal are corrected by an equalizer (not shown), the input terminal 7 outputs the i+4 circuits 8 and 11. The signals are respectively supplied to the F' level detection circuit 9. The waveform of this input BP' digital signal is shown in FIG.
From this, the reproduced signal (9
) is output and supplied to the low-pass filter 10. After the reproduced signal is converted into a squared cosine wave by the low-phrase filter 0, it is supplied to the comparator 11, where it is also transformed into a digital signal of 7 binary values as shown in FIG. The output digital signal is applied to one input terminal of the exclusive OR circuit 12, and after being delayed by the delay circuit 13 for a time sufficiently smaller than its minimum inversion interval, the output digital signal is input to the input terminal of the exclusive OR circuit 12. In other words, the exclusive OR circuit 12 and the delay circuit 13 constitute a known edge detection circuit.
FIG. 7 (C1
An edge detection signal C having a waveform as shown in FIG. Hakata, the RF level detection circuit 9 receives the RF' digital signal a.
A level detection signal corresponding to the envelope is generated and supplied to the time discrimination circuit 15. The time discrimination circuit 15 (10) confirms that the input 1tp digital signal level from the input terminal 7 has returned to normal! ! This circuit discriminates whether or not the period in which the signal has fallen below a predetermined level that cannot be demodulated by the IAI circuit 8 continues for a certain period of time (denoted by T3 in FIG. 7(g)), which will be described later. Here, when the input signal is interrupted, the tank circuit, which is composed of the capacitor C1 and the coil L1 connected between the output terminal of the NANT) circuit 14 and the power supply terminal and has a single peak characteristic, gradually attenuates according to its time constant. Then, the lock range of the PLL 17 in the subsequent stage becomes narrower as explained in conjunction with FIG.
A voltage controlled oscillator (VCO) 17 free-runs at a constant frequency determined by circuit constants such as the capacitor C2. In the present invention, the oscillation frequency of this vCO is preselected to be a natural number times or a natural number times the frequency of the clock signal to be reproduced. The time discrimination circuit::::1 The constant time period discriminated in step 15 may be due to, for example, erroneous correction due to the above-mentioned frequency fluctuation of the clock signal due to dropout, or the time length of dropout that poses a practical problem (for example, (about 20 frames of digital signal transmission period),
The time is selected to be slightly shorter than the time required for the PLL 17 to become unlocked after the input signal to the tank circuit is interrupted. As shown by d in Figure 7), the output signal of the time discrimination circuit 15 is H during a normal period in which dropout does not occur, and when dropout occurs but the length of time is less than the above-mentioned fixed time. When the T3 relay continues for a certain period of time due to the dropout time, it becomes L level at that point, and this output signal d is applied to the input terminal of the NAND circuit 14. The output signal of the NAND circuit 14 is tuned by a tank circuit consisting of a capacitor C1 and a coil L1 to only clock signal components with a frequency that is a natural number multiple of the frequency of the edge detection signal C, and is supplied to the next stage amplifier 16, where it is amplified. and is supplied to the PLL 17 (111). Here, the output signal d of the time discrimination circuit 15 is 1 level during a normal period in which no dropout occurs or when a dropout occurs but the time length is less than the above-mentioned certain time, so the NAND circuit 14 The edge detection signal C is phase-inverted and taken out at the output terminal of , and the clock (i component) is taken out by the tank circuit. Therefore,
At this time, the PLL 17 absorbs the jitter of the input (No. 8) and outputs a normal reproduced clock signal. On the other hand, if the dropout of the period shown by 12 in FIG. , the output signal d of the time discrimination circuit 15 becomes as shown in FIG.
Since the edge detection signal C is at the L level as shown in FIG. 1, the edge detection signal C is not taken out at the output terminal of the NAND circuit 14, and the edge detection signal C is always at the H level. As a result, the input signal to the tank circuit is interrupted after the above-mentioned fixed time T3, and the amplifier 16 is supplied with a signal e whose amplitude is gradually attenuated as shown in FIG. It continued for a long time and ended up being 2
If it continues for about 0 frame digital signal transmission period,
The level decreases to a certain value, and as mentioned above, the VCO in I'T, T, 17 becomes free-running oscillation (13). The free-running oscillation frequency of this VCO is transmitted to the output terminal 18 via a frequency divider or frequency multiplier depending on the core wall (see Fig. 7).
It is output as a clock signal f of a constant frequency as shown in F'). As a result, even if the dropout time is long, significant frequency fluctuations in the clock signal can be suppressed, the operation of the correction circuit can be stabilized without using expensive parts such as VCXO, and incorrect correction can be minimized. It is possible to suppress it to . In addition, if the dropout time length is longer than the above-mentioned fixed time T3 and is smaller than the time length at which the PLL 17 loses its lock, the PLL 17
is maintained in a locked state, and a clock signal whose frequency fluctuates to such an extent that there is no practical angle is taken out to the output terminal 18. In addition, in the above embodiment, the digital signal is recorded on a disk, and the case where it is applied to a device that reproduces this is explained, but it is also applicable to the case where the digital signal is recorded on other recording media such as magnetic tape. can. As mentioned above, the clock reproduction N path in the digital signal transmission (14) according to the present invention is the clock reproduction N path reproduced from the recording medium.
Ii' A tank circuit that outputs an edge detection signal obtained by detecting each edge portion of the demodulated digital signal after passing through a demodulation circuit, and extracts a signal with a frequency that is a natural number multiple of the edge detection signal. A phase clock that is supplied with an output signal and outputs a regenerated clock signal that is phase-synchronized with the output signal.
A locked loop, a level detection circuit that detects the level of the RF digital signal, and a period in which the output signal of the level detection circuit is supplied and the level of the rLF digital signal is at a low level that cannot be properly demodulated by the demodulation circuit or for a certain period of time. This is a means to keep the input signal level of the tank circuit constant when the input signal level of the tank circuit is kept constant. Regenerate voltage controlled oscillator 1""'0 '7"(; fi no.) i'j"
Since the configuration is configured so that a constant clock signal frequency is extracted from the phase-locked loop by free-running excavation at a frequency that is 1/5 times the frequency of the clock signal, the dropout time length is reduced by the dropout. If the error correction due to frequency fluctuation continues for a period of time that could lead to a delay in practical use, the phase lock is activated after a period of time slightly shorter than that period (i.e., the sum of the above-mentioned fixed period and the above-mentioned fixed time) has elapsed.・It is possible to make the '-1 pressure control oscillator in the loop free-running and output a constant frequency clock signal with no frequency fluctuations than a phase-locked loop. Therefore, it is not possible to obtain long-term clock information conventionally. In this case, it is possible to minimize the error correction caused by the phase-locked loop following false clock information from the tank circuit, and furthermore, without using expensive components such as VCXO, it is possible to use general-purpose, commercially available Since the PLL-IC can be used in the above phase-locked loop, the circuit structure can be made inexpensive, and therefore, it has the advantage of being particularly suitable for consumer use.,9.
・1

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing an example of the configuration of one frame of a digital signal, FIGS. 2 and 3 are block diagrams showing each of the conventional circuits, and FIGS. The time chart for explaining the operation in Figures 2 and 3, and the time chart in Figure 5 for explaining the operation.
, FIG. 6 is a circuit system diagram showing an embodiment of the circuit of the present invention, and FIGS. 7 (5) to (g) respectively explain the operation of FIG. 6. This is a time chart for 6.17...Phase Locked Roof (PLL)
), 7. Fight playback RF' digital signal input terminal, 8.
fist bone demodulation circuit, 9...R]-level detection circuit, 11.
@Kari comparator, 13ψeφ delay circuit, 15... time discrimination circuit, 18... reproduced clock signal output terminal, C
1...Tank circuit capacitor, L8/war/tank circuit coil. (17)

Claims (1)

[Claims] An RF digital signal reproduced from a recording medium is passed through a demodulation circuit, and then an edge detection signal obtained by detecting each edge portion of the demodulated digital signal is supplied, and the signal has a frequency that is a natural number multiple of the edge detection signal. a tank circuit for taking out the RF digital signal; a phase-locked loop that is supplied with the output signal of the tank circuit and outputs a regenerated clock signal that is phase-synchronized therewith; a level detection circuit that detects the level of the RF digital signal; and the level detection circuit. means for making the input signal level of the tank circuit constant when the output signal of the tank circuit is supplied and the level of the RF digital signal is at a low level that cannot be properly demodulated by the demodulation circuit, or when the level of the RF digital signal is maintained for a certain period of time; (b) When the input signal level of the phase loop is held constant, a gradually attenuating signal is extracted from the tank circuit and after a certain period of time the voltage controlled oscillator in the phase loop is regenerated. Clock regeneration in digital signal transmission, characterized in that the phase-locked loop is configured to extract a constant clock signal frequency from the phase-locked loop by free-running at a frequency that is a natural number multiple or a natural number multiple of the clock signal frequency to be used. circuit.