JP3386506B2 - Information recording / reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium processing apparatus applied to, for example, an optical disk recording / reproducing apparatus (hereinafter, an optical disk apparatus). 2. Description of the Related Art In order to decode reproduction data from an optical disk, a reproduction clock synchronized with the reproduction data is required. The timing of reading the reproduced data is determined by the reproduced clock. A PLL circuit is used to generate a reproduction clock. Such a PLL circuit detects the phase difference between the reproduced clock and the reproduced data and sets the correction value to VC
A reproduction clock is generated by inputting it to O (voltage controlled oscirator). In the conventional optical disk device, the gain of the PLL circuit has the same value in the header part and the data part of the information recorded on the optical disk. In a conventional optical disk device, if a scratch or a foreign substance is adhered to an optical disk medium, an erroneous data signal is input to a PLL circuit, and synchronization is performed based on this signal. The bit in data reproduction
When a shift occurs, a data error occurs up to the position of the next synchronization code, and the error area may be larger than the actual error. Accordingly, the present invention prevents the bit shift from occurring by lowering the gain of the data portion from the gain of the PLL circuit in the header portion and the data preamble portion, where the reproduced signal and the PLL circuit need to be quickly synchronized. It is an object of the present invention to provide an information processing apparatus capable of preventing an error area from being enlarged. In order to achieve the above object, an information processing apparatus according to the present invention comprises: means for decoding a format of information recorded on an optical disk and providing a result of the decoding; Oscillating means for outputting a signal having a corresponding frequency, means for outputting a phase difference between reproduced data of the information and an output signal of the oscillating means, and processing the phase difference signal according to the decoding result, Means for supplying a processing result to the oscillating means. The positions of the header section, data preamble section, and data section of the information obtained from the optical disk are determined by the format decoding means, and the gain of the PLL circuit changes at that position. That is, the PLL circuit gain of the data section is set lower than the header section and the data preamble section. Therefore, the expansion of the error area due to the bit shift of the data portion is prevented. FIG. 1 shows an embodiment of a PLL circuit according to the present invention. An optical disk drive 1 optically reads information from an optical disk and outputs an electric signal corresponding to the optical signal to a reproduction signal processing circuit 2. Reproduction signal processing circuit 2
Is connected to the optical disk drive 1 and binarizes the input signal to output reproduced data RDT. The phase comparator 3 is connected to the reproduction signal processing circuit 2, and outputs the reproduction data RDT and V
The outputs of CO 8 are compared to generate signals CHG and DIS indicating the phase difference between the signals. The output of the charge pump 4 connected to the phase comparator 3 is the output C of the phase comparator 3.
When HG is at low level, the current is sucked, and when output DIS of phase comparator 3 is at high level, the current is released. The gain of the phase comparator 3 changes by switching SW1. a ₁ and b ₁ are resistors, and a ₁ <b ₁ . The format decoding circuit 5 detects the position of a data portion (described later) in the reproduction data RDT obtained from the optical disc, and outputs the detection result to the switch SW1 of the charge pump 4. When the signal being reproduced at present is a data part signal, a low level signal is output. As a result the switch SW ₁ of the charge pump 4 is turned OFF, the current gain decreases. An active filter 6 and an LPF (low-pass filter) 7 filter the output of the charge pump 4. VC
O8 is a clock (V) having a frequency corresponding to the output of the LPF.
CLK0). FIG. 2 shows an example of a format on an optical disk medium. The header includes a header preamble (HPA) composed of a repetition of a specific pattern for synchronizing the PLL circuit, an ID, and a synchronization code (AM) indicating the head of the ID. In order to prevent the ID portion from being unreproducible due to a defect on the medium, a plurality of AM + IDs are usually prepared and each has an ID number. The data portion is composed of 4813 bytes, and a synchronization code (RESYNC) is inserted every ten and several bytes in order to correct a bit shift during data reproduction. In the preceding stage of the data portion, a write completion flag (WF) and a data preamble portion (DP) for synchronizing the PLL circuit are provided.
A) and synchronization code (DM) for bit shift correction
Is arranged. Next, the operation of the information recording / reproducing apparatus according to the present invention will be described. First, the reproduction data binarized by the reproduction signal processing circuit 2 and the reproduction clock VC from the VCO 8
LKO is input to the phase comparison circuit 3, and the phase difference between these signals is detected. FIG. 3 shows a configuration example of the phase comparison circuit 1. FIG. 4 shows the outputs CHG and DIS when the output VCLK0 of the VCO 8 and the reproduction data RDT are input to the phase comparison circuit 1. 4A shows the case where the phases of VCLK0 and RDT match, FIG. 4B shows the case where the phase of VCLK0 is advanced, and FIG. 4C shows the case where the phase of VCLK0 is delayed. For example, when the phase of VCLK is advanced, the high period of the signal DIS is longer than the low period of the signal CHG. Therefore, at the output of the phase comparison circuit 1,
There is more outgoing current than incoming current. The output of the phase comparator 3 is inverted by the active filter 6, filtered by the low-pass filter 7, and input to the VCO 8. When the phase of VCLK is advanced, as in this case, the input voltage of VCO 8 drops. As a result, the frequency of the reproduced clock VCLK0 becomes low, and its phase is delayed. As described above, the correction based on the shift amount is performed by VC
By performing the operation on O, a reproduced clock VCLK0 synchronized with the reproduced data is generated. The format decoding circuit 5 first detects the AM portion of the reproduced data using the reproduced clock VCLK0 generated as described above.
Start decoding the D part, and if the result of the right / wrong judgment is correct, ID
The header position currently being played can be determined from the number.
As described above, if the header position currently being reproduced can be determined, the position of the data portion can be determined by the reproduction clock and the counter. As a result, as shown in the timing chart of FIG. 5, the data part separation signal is output to the switch SW1, and the switch SW1 is turned off. Therefore, the loop gain of the PLL circuit in the data section is lower than in other sections such as the header section and the data preamble section. The synchronization between the reproduced clock and the generated data in the PLL circuit can be performed in a shorter time as the loop gain of the entire PLL circuit is higher, but erroneous reproduced data is input to the PLL circuit due to a defect on the optical disk medium or the like. In such a case, the synchronization is quickly performed based on the wrong phase, so that an error due to the bit shift of the subsequent data is easily caused. When a bit shift occurs, the data becomes an error until a synchronization code in the data can be detected, and the error area becomes larger than the actual defective area. Therefore, at the time of reproducing the data portion, by lowering the gain of the PLL circuit, it is possible to prevent the occurrence of a bit shift due to a defect or the like in the data portion. ID1 to ID3 in FIG. 2 each contain the same data, and details of each ID section are shown in FIG. As shown in the figure, each ID section has an ID number, a block number,
It is composed of a track number, information, and a preamble part. The reverse phase data is obtained by inverting the normal phase with bits.
A is composed of the same data as HPA. Therefore, even when the phase of the reproduction clock VCLK0 and the phase of the reproduction data RDT do not match in ID1, if the phases match in ID2 or ID3,
The position of the currently reproduced data in the header portion is determined. As described above, since the reproduction clock VCLK0 is already synchronized by the time of data preamble DPA reproduction, it is not necessary to increase the PLL gain in the data section. For this reason, by switching the switch SW1 of FIG. 1 to the OFF side, the gain of the entire PLL circuit is lowered, and the occurrence of a bit shift can be suppressed by delaying the phase pull-in for a defect. According to the present invention, the occurrence of a bit shift in a data reproducing unit applied to an optical disk device or the like can be suppressed, and the expansion of data errors can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a configuration of an embodiment of a PLL circuit according to the present invention. FIG. 2 shows an example of a data format of an optical disc. FIG. 3 shows a specific configuration example of the phase comparison circuit 1 of FIG. FIG. 4 is a timing chart showing an operation of the phase comparison circuit 1 of FIG. 1; FIG. 5 is a timing chart showing the operation of the format decoding circuit of FIG. 1; FIG. 6 shows details of the ID part of FIG. 2. [Description of References] 1. Optical disk drive, 2. Reproduction signal processing circuit, 3. Phase comparator, 4. Charge pump, 5. Format decoding circuit. , 6 ... active filter, 7 ... low-pass filter, 8 ... voltage-controlled oscillator.

Claims (1)

(57) Claims 1. An information processing apparatus for reproducing information recorded on an information recording medium in a format including a header section, a data preamble section, and a data section, a signal obtained from the recording medium. Binarizing means for outputting a reproduction signal of the information by binarizing; and decoding the ID information recorded in the header section based on the reproduction signal output from the binarization means. ID information decoding means for judging the position of the data portion from ID information and providing the judgment result, oscillating means for outputting a signal having a frequency corresponding to the input voltage, and reproduction output from the binarization means A phase comparing unit that compares a phase of a signal with a phase of an output signal of the oscillating unit and outputs a phase difference signal corresponding to a phase difference between the two signals, and the ID information decoding unit. The phase difference signal output from the phase comparing means is amplified by a first uniform gain at the time of reproducing the data portion, and the second signal larger than the first is amplified at the time of reproducing an area other than the data portion.
An information recording / reproducing apparatus, comprising: a variable amplifying unit that amplifies with a uniform gain and provides the amplified phase difference signal to the oscillation unit.