JPS60140947A - Bit synchronization circuit - Google Patents

Abstract

PURPOSE:To decrease the pull-in time by applying phase correction of a reproduced clock only when a reception data is at a level of prescribed range so as to simplify the phase correction of the regenerated clock. CONSTITUTION:A counter 5 as a regenerated clock output circuit frequencydivides an output x1 of a pulse generating circuit 1 so as to obtain a regenerated clock x5. The phase correction of the clock x5 is controlled as shown in the following by a pulse x4. A circuit 2 generates a pulse x2 of a minute width at a point of time when an input in crosses a reference value Vc. A level measuring circuit 10 of a level discriminating circuit 3 detects the level of the reception signal in and when a detected output x10 is higher than the V1, an output x19 of a comparator 19 indicates a state ''1'' and when the x10 is lower than the level of a V2, an output x20 of a comparator 20 represents state ''1''. Then an AND circuit passes a pulse x2 when both the x19, x20 are at logical ''1'' and an x4 is obtained. A stable clock pulse is regenerated by using the x4 and clearing the counter 5 so as to correct the phase of an output x5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bit synchronization circuit provided in a receiver,
In particular, the present invention relates to a bit synchronization circuit that performs bit synchronization on data signals received in bursts.

Conventionally, bit synchronization circuits have a circuit configuration that corrects the phase of the reproduced clock pulse by referring to the phase of the received data while receiving a data signal, making protection against phase error correction complicated. It takes a long time to pull in the synchronization,
Therefore.

Either a preliminary signal for bit synchronization must be added to the received data signal, or the bit synchronization circuit itself must be extremely complex.

The object of the present invention is to eliminate all of these conventional drawbacks, and the phase correction is performed only when the received signal is within a predetermined range of levels.

The object of the present invention is to provide a bit synchronization circuit suitable for receiving burst signals with a very simple locking time and a short time.

Next, embodiments of the present invention will be described with reference to all the drawings.

Referring to FIG. 1, a bit synchronization circuit according to an embodiment of the present invention is provided in a receiver that receives a burst signal, and includes a reproduced clock output circuit consisting of a counter 5 and a level synchronization circuit of an input signal in. is a predetermined first level value V
, a predetermined second level value V2 (where V2>
Vl) is detected and the detection signal (X, 9 and
The level determination circuit 3 that outputs a signal in which both 20 and 11" is output, and only when this level determination circuit 3 outputs the detection signal, the reproduced clock output circuit (i.e., the counter 5) It has a bit synchronization control circuit (a circuit including circuit 2 and AND circuit 4) that completely controls phase correction based on input signal +n.

The counter 5 serves as a reproduced clock output circuit.

Output 3- of pulse generation circuit 1 that generates high-speed pulses The power xsk is divided into two stations to obtain a reproduced clock X++e.

Modification of the phase of the reproduced clock X is controlled by the output pulse X4 of the AND circuit 4. below.

The method for obtaining this pulse x4'(z will be explained below.

Circuit 2 is a circuit that generates a minute width pulse x2i when the input in crosses the reference value Vc' (z.Reference value V.

is given by the variable resistor 6.

First, after the comparator circuit 7 compares the input in' with the reference value V0, the output of the comparator 7 is delayed within one period of the high-speed pulse x1 using the flip-flop circuit 8. The input and output are input to an exclusive OR circuit 9 to obtain a pulse X2.

The level determination circuit 3 is for detecting that the level of the received signal in is greater than vl and smaller than V2.

Capacitor 11. Diode 12, 13° Resistor 14. Capacitor 15. Resistance 16. A level measuring circuit 10 including a capacitor 1 rectifies and smoothes the received signal in to measure the level. Part 4- If the output XIO of the comparator 19 is higher than vl, the output
, 9 indicates the state 11", and if XIO is lower than v2, the output X20 of the comparator 20 indicates the state "1". Note that 18.
21 and 22 are resistors for setting Vl and V2.

Circuit 4 is an AND circuit for passing or cutting off X2, but +X101 and X20 are both 11111, that is, the level of in is higher than vl, and v2
I get +X+e by letting it pass only when it is smaller.

In other words, +x4 occurs only when the input in is at the expected level, and +Xae is used to generate counter 5.
By clearing and correcting the phase of output X, a stable lock pulse can be regenerated.

Next, FIG. 2, which shows the operating waveforms of FIG. 1, will be described. The input signal in is a thermal signal during t, and is in a slightly noisy state. j2+j3+t4 indicates that a burst signal is coming.

t3 is a case where particularly large noise is included.

As a result of level measurement, XIO is V, if it is higher than XI9
If is in the °°1" state and is less than +"2, then X20 is in the n1n state. A minute width pulse is generated every time X2p and ■ are crossed, but as already explained in +X4, a pulse is not generated unless both +X101 and X20 are in the ``1°1'' state.A pulse is output to X4. The periods are t5 and t6.The phase of X is corrected at X4.

Now, when a signal is received, in a large noise/small range such as the interval t3, not that much noise is included, and even if the phase is corrected at this time, it will not result in an erroneous correction.

According to this example.

As soon as the level measuring circuit output XIO enters a stable state, it enters a synchronized state with respect to the burst signal, so the pull-in time is extremely short.

This pull-in time is determined by the resistors 14, 16, . determined by capacitors 11.15.17.

7- As explained above, if the present invention is used, the phase of the recovered clock can be easily corrected, and the synchronization The draw-in time is also short.

In addition, in FIG. 1, when a band-limiting filter is inserted and connected between the input terminal of the received signal 1n and the level determination circuit 3, the level of the special frequency component of the received signal is
Since phase correction for bit synchronization is performed only when the signal is between l and v2, the error correction rate for noise is further reduced by the effect of monitoring both the level and frequency of the received signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the entire bit synchronization circuit according to an embodiment of the present invention, and FIG. 2 is an operation waveform diagram for explaining FIG. 1. 1...Pulse generation circuit, 6...Level judgment circuit. 4...AND circuit, 5...Counter, 6...Variable resistor, 7...Comparison circuit, and...Flip-flop circuit. 9... Exclusive OR circuit, 10... Level measurement circuit. 19 and 20... Comparators. Honko) (

Claims (1)

[Scope of Claims] 1. In a bit synchronization circuit having a reproduced clock output circuit and configured to obtain a reproduced clock that is bit-synchronized with an input signal at an output terminal of the reproduced clock output circuit, 1 level value and a second level value larger than the first level value, and the level of the input signal is larger than the first level value and smaller than the second level value, and detects the hidden money. a level determination circuit that outputs a signal; and a pit synchronization, synchronization, and timing control circuit that controls phase correction based on the input signal for the reproduced clock output circuit only when the level determination circuit outputs the detection signal. A bit synchronization circuit comprising a control circuit. 2. In a bit synchronization circuit having a reproduced clock output circuit and configured to obtain a reproduced clock bit-synchronized with an input signal at an output terminal of the reproduced clock output circuit, a predetermined frequency component from the input signal is obtained. a filter that extracts a first level value and a second level value larger than the first level value, the level of the output signal of the filter is larger than the first level value, and a level determination circuit that detects a hidden money smaller than the level value of and outputs the entire detection signal; and a bit synchronization control circuit for controlling modification. 3. The reproduced clock output circuit is a counter that divides and outputs a pulse of a predetermined frequency. The bit synchronization control circuit operates only when the level determination circuit outputs the detection signal. 3. The bit synchronization circuit according to claim 1, wherein said bit synchronization circuit controls said counter to be reset at a time point when said human input signal crosses a reference value.