JPS63204563A - Data recording error detector for optical disk device - Google Patents

Abstract

PURPOSE:To inexpensively and surely execute verifying reading and to improve the reliability of recording data by providing the titled device with an allowable phase difference setting circuit for detecting that a phase difference exceeds a prescribed allowable value and rewriting the recording data in a replacing sector based on an output signal from the circuit. CONSTITUTION:The titled device is provided with an automatic phase control circuit 10A for reproducing a clock signal synchronizing with a recording data signal obtained from a recording medium 9 and the allowable phase difference setting circuit 18 for detecting that a signal phase difference outputted from a phase detector 12 in the circuit 10A exceeds the allowable value. When the circuit 18 detects that the phase difference between a reproduced clock signal outputted from a voltage control oscillator 11 and an input data signal exceeds a prescribed set value at the time of verifying reading, i.e. when the recorded data are in error, the circuit 18 actuates a replacing sector signal generator 17 to record data again in a replacing sector.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data recording error detection device for detecting errors in data recorded on an optical disc.

[Conventional technology]

FIG. 4 is a configuration diagram of a recording format when recording user data on an optical disc. In the figure, (1) is the header that records sector address information, and (2) is the fifth header.
A preamble is a run-up section for phase withdrawal of the automatic phase control circuit (9) in the figure, (3) is a sync pattern for initial synchronization of user data (4) to be recorded,
(5) is an error correction code that can detect errors in user data (4) during recording, and (6) is a header (1).
, a preamble (2), a sync band (3), user data (4), and an error correction code (5).
This is the sector recording format. Also, the header (1
) is pre-matted on the optical disc, and the area obtained by removing the header (1) from the recording format (6) is called add-on data, and is an area that is followed by the optical disc device.

FIG. 5 is a block diagram of a conventional optical disk data recording and reproducing system disclosed in, for example, Japanese Patent Application No. Sho 60-174598. In the figure, (7) is an error correction encoding means for generating an error correction code (5) from the user data to be recorded (4), and (8) is a modulator, the input side of which is an error correction encoding means. The output side of the means (7) and the reference clock signal # (al) are connected to modulate the add-on data in synchronization with the reference clock signal (a).

(9) is an optical disk which is a recording medium, and is controlled by a laser beam (not shown) which is turned on and off according to the signal modulated by this modulator (7).
This modulation signal is input into il:. (10) is an automatic phase control circuit whose input side is connected to the output side of the optical disk (9), into which a modulation signal read from the optical disk (9) is input, and a reproduced clock synchronized with this modulation signal. Generate signal (b). (14) is a demodulator whose input side is connected to the output side of the optical disc (9) and the reproduced clock signal (b), and according to the reproduced clock signal (b) from the automatic phase control circuit (1), Demodulates the read modulated signal. (15) is an error detection and correction means,
It is connected to the demodulator (14) and detects and corrects errors by referring to the error correction code (5) added to the user data (4) demodulated by the demodulator (14). )
is a switching circuit, and its output side is a demodulator (14)
and is connected to the input side of the error detection and correction means (15), and the error correction capability of the error detection and correction means (15) and the timing of demodulating the recorded signal of the automatic phase control circuit (10) will be described later as normal reproduction. Switch at verify read. (
17) is a replacement sector signal generator, the input side of which is connected to the NIR signal (C) from the error detection and correction means (15), and when the switching circuit (16) is switched at the time of verify reading, When the number of errors detected by the error detection and correction means (15) exceeds a specified number, a replacement sector signal is generated to notify that the user data (4) is to be rewritten in the replacement sector of the optical disk (9).

FIG. 6 is a detailed circuit diagram of the automatic phase control circuit (10). In the figure, an automatic phase control circuit (10) is composed of a voltage controlled oscillator (11), a phase detector (12) and a low pass filter (1S). The frequency of the voltage controlled oscillator (11) changes depending on the control voltage. Phase detector (12
) compares the phase of the output signal of this voltage controlled oscillator (11) and the output signal from the optical disk (9).

A low-pass filter (13) removes high frequency components from the output signal from the phase detector (12), and uses the output voltage of this low-pass filter as a control voltage to generate a voltage-controlled oscillator (11).
is supplied to.

The conventional data recording error detection device is configured as described above, and includes a correction encoding means (Fit) that converts the user data to be recorded (4) into an error correction code (5) that enables detection and correction of errors after recording. (Reference clock signal (a)
Modulation is performed by the transformer (8) in synchronization with the signal.

A modulation signal from the modulator (8) causes the modulation signal to be recorded on the optical disk (9) by means of a laser beam. Each time the user data (4) recorded on the optical disk (9) is recorded, it is checked whether it is recorded correctly, and if it is recorded incorrectly, the same user data (4) is written to another sector. Repeat the operation on line 5 (verify read). During this verify read, as in normal playback, the laser beam is irradiated with a lower output than during recording, and by reading the change in reflectance of the optical disc (9), the modulated recording signal is electrically transmitted. Take it out. By inputting the extracted modulated recording signal to the automatic phase control circuit (1a), a clock signal synchronized with the recording signal is reproduced. That is, as shown in FIG. 6, the output modulated recording signal output from the optical disk (9) is input to the automatic phase control circuit (1a), and the output signal of the voltage controlled oscillator (11) is combined with this input signal. The phase difference is compared by a phase detector (12), converted into a voltage that matches the phase difference between the two by a low-pass filter (13), and recorded by feeding it back to the voltage-controlled oscillator (11) as a control voltage. A clock signal synchronized with the signal is regenerated. After the recording signal modulated according to the reproduced clock signal (b) from the automatic phase control circuit (10) is demodulated by the demodulator (14), the error detection and correction means (15) determines whether or not there was an error during optical disc recording. Errors are detected and corrected by referring to the error correction code (5) added to the user data (4). At this time, if the error is within a specified range, a recording signal is recorded in the sector. Further, when the error exceeds the specified range, an error signal (C) is generated from the error detection and correction means (15), and upon receiving this error signal IC), the replacement sector signal generator (17) outputs the optical disc ( 9)
A replacement sector signal is generated to notify that the user data (4) will be rewritten in the replacement sector.

[Problem that the invention seeks to solve]

In the conventional data recording error detection device as described above, when demodulating the timing of the reproduced clock signal from the automatic phase control circuit by switching the verify read timing switching circuit, demodulation errors are more likely to occur than during normal reproduction. Errors are detected by changing the specified direction value, or by lowering the error correction ability of the error detection and correction means compared to normal playback, so that errors are detected, and the error is detected again in the replacement sector. To prevent recording errors from occurring during normal playback, we have created a reproduction clock adjustment circuit that includes a delay line to temporally change the timing of the reproduction clock signal and errors. This invention was made to solve these problems, as it required a circuit to switch the correction ability, which required a large circuit scale and high cost. It is an object of the present invention to provide a data recording error detection device that detects errors in recorded signals using the output of a detector.

[Means for solving problems]

A data recording error detection device according to the present invention includes an automatic phase control circuit that reproduces a clock signal synchronized with a recorded data signal from a recording medium, and an output signal phase difference of a phase detector of the automatic phase control circuit that is within a predetermined tolerance. a permissible phase difference setting circuit that detects that the value has been exceeded; and a replacement sector signal that operates based on the output signal from the permissible phase difference setting circuit and generates a replacement sector signal for rewriting recorded data in the replacement sector. It is equipped with a generator.

[For production]

In this invention, when the allowable phase difference setting circuit detects that the phase difference between the reproduced clock signal from the voltage controlled oscillator and the input data signal exceeds a predetermined value during verify read, that is, the recorded data is incorrect. If it is, the allowable phase difference setting circuit operates the alternate sector signal generator to cause the alternate sector to perform data recording again.

〔Example〕

FIG. 1 is a block diagram of a data recording and reproducing system including an optical disk data recording error detection device showing an embodiment of the present invention. In the figure, (force*(at.

(9), (14) and the pump (15) are exactly the same as those of the conventional device described above. (10A) is an automatic phase control circuit, the input side of which receives a modulation signal read from the optical disk (9), and generates a reproduced clock signal synchronized with this modulation signal. (18) is an allowable phase difference setting circuit, which detects that the output signal from the automatic phase control circuit (10A) exceeds a specified value. (17) is a replacement sector signal generator which generates a replacement sector signal of the optical disc (9) when the phase difference of the output signal from the phase detector (12) of the allowable phase difference setting circuit (10A) is large during verification read. A replacement sector signal is generated to notify that the add-on data is to be renewed.

FIG. 2 is a detailed circuit diagram of the automatic phase control circuit (IOA) and the allowable phase difference setting circuit (18). In the figure, the automatic phase control circuit (IOA) includes a voltage controlled oscillator (11),
It consists of a phase detector (12), a low pass filter (15) and a frequency divider (19). Allowable phase difference setting circuit (1
8) is a comparator (20), a reference voltage generator (2)
1) and an AND gate (22). The voltage controlled oscillator (11) has a low pass filter (
16) and the output sides thereof are respectively connected to one input side of the phase detector (12) via a frequency divider (19). The other input side of the phase detector (12) is connected to the output side of the optical disc (9). In addition, a phase detector (1
The output side of 2) is connected to the input side of the low-pass filter (16) and to the contact (Sl) of the switch (SW).

Further, one end of the contact (Sl) of the switch (SW) is grounded. The comparator (20) has one input side connected to a switch (SW), and the other input side connected to a reference voltage generator (21) whose end is grounded. One input side of the AND gate (22) is connected to the gate signal generation circuit (2S), and the other input side is connected to the comparator (20). Furthermore, the output side of the AND gate (22) is connected to the alternate sector signal generator (1).
7) is connected.

FIG. 3a is an output waveform diagram of the phase detector (12) of FIG. 2.

FIG. 6b is an output waveform diagram of the gate signal generation circuit (23) used in the phase difference setting circuit (18) of FIG. 2.

FIG. 3c is an output waveform diagram of the comparator (2o) in FIG. 2.

FIG. 3d is an output waveform diagram of the AND gate (22) of FIG. 2.

In the data recording error detection device configured as described in 5 above, the error correction encoding means (7) converts the error correction code (5) that makes it possible to detect and correct errors during playback from the user data (4) to be recorded. ) and the reference clock signal (a
), C modulation is performed by the modulator (8). A laser beam is controlled by a signal modulated by a modulator (8), and the modulated signal is recorded on an optical disk (9) by this laser beam. Check whether the add-on data recorded on the optical disc (9) is recorded correctly each time it is recorded. If it is recorded incorrectly, repeat the operation to write the same add-on data to other sectors. Execute (verify read). During this verify read, as well as during normal playback, the laser beam is irradiated with a lower output than during recording, and the recorded add-on data is electrically read by reading the change in reflectance of the optical disc (9). Take it out. The add-on data taken out from the optical disc (9) is input to an automatic phase control circuit (10A) to reproduce a clock signal synchronized with the add-on data. That is, as shown in FIG. 2, the add-on data read from the optical disc (9) is sent to the automatic phase control circuit (10).
A), and a phase detector (12) compares the phase difference between this input data signal and a divided signal obtained by dividing the output signal of the voltage controlled oscillator (11) by a frequency divider (19). , a low-pass filter (16) converts it into a voltage signal according to the phase difference between them, and feeds it back as a control voltage to a voltage-controlled oscillator (11) to reproduce a clock signal synchronized with the add-on data.

Next, the operation of the present invention will be explained in detail with reference to FIGS. 2 and 6. Input data signal and voltage controlled oscillator (1
If the frequencies of the output signals of 1) are different, the phase detector (1)
As shown in FIG. 5a, the output signal 2) generates a beat signal corresponding to the frequency difference between the two signals. When this beat frequency is below a certain value, both signals are frequency synchronized.

If the input data signal is within the synchronization range of the automatic phase control circuit (10A), the frequency of the voltage controlled oscillator (11) approaches the frequency of the input data signal in the positive half cycle, and moves away from it in the angular half cycle. . Therefore, the positive half-cycle changes more slowly than the negative half-cycle, and the overall DC level becomes positive.

When this DC level voltage controls the voltage controlled oscillator (11) in a direction that reduces the frequency difference, an even larger DC component is generated, and the frequency gradually follows the frequency at an accelerated rate due to the positive feedback effect. This process is a frequency pulling process. Next, when the frequency difference becomes below a certain level, the response of the automatic phase control circuit (10A) becomes 5 so that it can completely follow the beat signal, and synchronization is established within that period. This process is a phase locking process.

After that, it settles to a steady phase error of the automatic phase control circuit (10A), but the phase of the subsequent input data signal may be affected by medium defects, device noise, etc. (C1 voltage controlled oscillator (11))
, an output signal (phantom) proportional to the phase difference is obtained from the phase detector (12) as shown in FIG. 3a.

Also, a comparator (20) and a reference voltage generator (21)
), it is possible to detect when the voltage corresponding to the phase difference between the output signal (dl) of the phase detector (12), that is, the input data signal and the output signal of the voltage controlled oscillator (11) exceeds a certain specified value. 9. AND circuit (22) only when necessary
It can be output by

Each signal waveform (d) I (f)? (g),
(hl and (e) are shown in Figures 3a to 3d, respectively.

Now, during verify read, that is, when checking whether the recorded data was recorded correctly after data recording, the switch (SW) is set to the contact (Sl) side and the phase detector ( 12) so that the output signal (dl) flows.In addition, during normal playback, the switch (SW
) to the contact (82) Ic to set the allowable phase difference setting circuit (18)
If the phase difference between the input data signal and the output signal of the voltage controlled oscillator (11) exceeds a certain specified value, that is, if an error occurs in the recorded data, this allowable phase difference setting circuit will prevent the input data signal from operating. (18) Accordingly, the recording error detection pulse signal (e) is output, and this output signal (e) is supplied to the replacement sector signal generator (17), and the recorded data of the replacement sector is rewritten in order to rewrite the recording data. I do.

In general, the input data input to the automatic phase control circuit (IOA) is the sync pattern (5) after the preamble (2) of the recording format (6) as shown in FIG.
3), user data (4), and error correction code (5), and by the period of this preamble (2), the frequency pull-in process and the phase locking process have finished as shown in Figure 3a. , a regenerated clock signal with only a steady phase error remaining (
b) is generated by an automatic phase control circuit (10A). However, after the phase locking process, the sync pattern (
3) If a recording abnormality occurs in part of the data of the user data (4LH correction code (5)), the phase of the input data signal is different from the phase of the output signal of the voltage controlled oscillator (11), and the phase detection The output signal (dl) of the generator (12) becomes large as shown in waveform (i) in Fig. 6a. This abnormal phase error signal (1) is input to the comparator (20) and the reference voltage generator ( 21), and when it exceeds the reference voltage (f), the output signal (hl) of the comparator (20) becomes "
In this way, when the phase difference between the input data signal and the reproduced clock signal is exceeded, the output signal of the converter (20) becomes "1", and the data becomes Recording errors can be detected. Note that since the reference voltage (f+) input to the comparator (20) can be arbitrarily set by the variable resistor of the reference voltage generator (21), the voltage corresponding to the allowable phase difference can also be arbitrarily set. In the phase synchronization process, the phase difference between the input data signal and the reproduced clock signal (b) is large, and the output signal (h) of the comparator (20) often becomes "high". In order to prevent (18) from outputting an unnecessary recording error detection pulse signal, the gate signal (g) K generated from the gate signal generation circuit (23) is masked.3 In this way, during verify read, that is, after recording. It is possible to check whether there is an error in the recorded data by inputting the output signal of the phase detector (12) of the automatic phase control circuit (10A) to the allowable phase difference setting circuit (18).This allowable phase difference Setting circuit (18)
A recording error detection pulse signal (e) from the AND gate (22) is sent to a replacement sector signal generator (17), and a replacement sector signal is sent out so that the replacement sector can be reset when a recording error occurs.

In addition, in the above embodiment, when a recording error detection signal is generated during perify read, the case is explained in which the recording error detection signal is rewritten to a replacement sector, but the recording error detection pulse signal is counted by a counter, and the recording error detection pulse obtained as a result is Depending on the number, replacement sectors and replacement tracks (replacement of replacement sectors)
It is also possible to perform an operation of rewriting the data into , and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, the present invention includes an automatic phase control circuit that reproduces a clock signal synchronized with a recording data signal from a recording medium, and a phase difference between the output signals of the phase detector of the automatic phase control circuit that exceeds a predetermined tolerance value. a permissible phase difference setting circuit for detecting that the permissible phase difference has occurred, and a replacement sector signal generator that is operated by an output signal from the permissible phase difference setting circuit and generates a replacement sector signal for rewriting recorded data in the replacement sector to 5. By using the output signal of the phase detector, which is a part of the automatic phase control circuit that generates the reproduced clock signal from the data read from the optical disk, verification read can be performed inexpensively and reliably. Go,
This has the effect of increasing the reliability of recorded data.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the configuration of a data recording/reproducing system including an optical disk data recording error detection device showing one embodiment of the present invention, and FIG. 2 is an automatic phase control circuit shown in FIG. 1. (10A)
and detailed circuit diagram of the allowable phase difference setting circuit (18), No. 3a
The figure is an output waveform diagram of the phase detector (12), Figure 3b is an output waveform diagram of the gate signal generation circuit (23), Figure 3C is an output waveform diagram of the comparator (20), and Figure 3d is an output waveform diagram of the AND gate (22). ), Figure 4 is a configuration diagram of the recording format, Figure 5 is a diagram of data recording on a conventional optical disc,
A system configuration diagram for reproducing recorded data, FIG. 6 is a detailed circuit diagram of an automatic phase control circuit. In the figure, (7)... error correction encoding means, (8)...
0 modulator, (9)... optical disk, (IOA)... automatic phase control circuit, (11)... voltage controlled oscillator, (12)
...Phase m out! , (13)...Low pass filter, (1
4) Demodulator, (15) Error detection and correction means, (1
7) Alternate sector signal generator, (18) Allowable phase difference setting circuit, (19) Frequency divider, (20) Self comparator, (21) Reference voltage generator, (22) I.
AND gate (25)...Gate signal generator. In addition, the same reference numerals in each figure indicate the same or Buddhist priest parts. Figure 11 of eh-ze: 1: '1-1 Procedural amendment dated July 6, 1986

Claims (4)

[Claims] (1) Detects that the output signal phase difference between an automatic phase control circuit that reproduces a clock signal synchronized with a data signal reproduced from a recording medium and a phase detector of the automatic phase control circuit exceeds a predetermined tolerance value. and a spare sector signal generator that is operated by an output signal from the permissible phase difference setting circuit and generates a spare sector signal for rewriting recorded data in the spare sector. When reading data from an optical disc, if the output signal phase difference of the phase detector exceeds the predetermined tolerance value, the permissible phase difference setting circuit generates a data recording error detection output signal. Recording error detection device. (2) The data recording error detection device for an optical disk according to claim 1, wherein the recording medium is an optical disk. (3) The automatic phase control circuit includes a phase detector that detects the phase difference between the reproduced data signal and the reproduced clock signal, a low-pass filter that removes high-frequency components of the output signal of this phase detector, and an output voltage of this low-pass filter. Claim 1 is characterized in that it is comprised of a voltage controlled oscillator that uses as a control voltage, and a frequency divider that divides the frequency of an output signal from the voltage controlled oscillator and feeds it back to the phase detector. A data recording error detection device for an optical disc as described above. (4) The allowable phase difference setting circuit includes a reference voltage generator that generates a reference voltage, a comparator that compares this reference voltage with the output from the phase detector, and an AND between the output signal of this comparator and the gate signal. 2. The data recording error detection device for an optical disc according to claim 1, further comprising an AND gate that takes .