JPS61233469A - Reproducing device - Google Patents

Abstract

PURPOSE:To make it possible to hold a PLL circuit and to make data processing without error by utilizing the lack of a frame synchronizing signal as the detection signal of a lacked part of reproduced signals. CONSTITUTION:A phase comparing circuit 2 phase-compares a clock extracted from RF signals obtained from a pickup with the output of a VCO 6 and outputs an error signal ER and thereby a clock CLK phase locked from the VCO 6 RF signals can be obtained. A detection signal GFS that detects the lack of frame synchronizing signal FS is applied to an input terminal 7 and a switching signal SW is obtained from a comparator 9. Thereby,a switch 3 is made off, a PLL circuit 1 is held and the VCO 6 makes self-oscillation. During this period, the disk is kept at a specified speed by its inertia. Accordingly, the synchronization of the clock CLK obtained from the VCO 6 and RF signals is maintained at the time of holding of the PLL circuit 1 and signal processing can be made without causing errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a playback device for playing back a recording medium on which digital signals are recorded, and is suitable for use in, for example, a digital audio disc player.

[Invention I! Expenses]

The present invention utilizes a signal that detects a lack of a synchronization signal from a reproduced signal, and uses this detection signal to generate a clock.
By controlling the operation of the LL circuit, signal processing can be performed without error when a signal is lost due to noise.

[Conventional technology]

In a CD player that plays digital audio discs, such as compact discs, a PLL circuit reproduces a clock from a reproduction signal obtained from a pickup, and based on this clock, frame synchronization with a predetermined code is generated from the reproduction signal. I'm trying to separate the signals. Then, data processing of the reproduced signal is performed based on the synchronization signal and the clock. Therefore, the synchronization signal is important for data processing, and if this synchronization 1M signal is missing, data demodulation becomes impossible. For this reason, conventionally, the missing synchronization signal is detected and a pseudo synchronization signal is created based on this detection. Detection of synchronization signal loss is performed as shown in FIG.

In the disk data format, as shown in Figure 5, there are 588 clocks OLK between each synchronization signal FS, that is, in one frame period, so synchronization is performed based on these clocks OLK. A wind pulse WP having a predetermined pulse width T including the signal F8 is created, and the synchronization signal F8 is detected using this wind pulse WP. As a result, when the synchronization signal FS is missing as shown by the dotted line, it is possible to obtain the detection signal GFS that falls from rHJ to rLJ.

On the other hand, if a relatively long period of loss occurs in the reproduced signal due to a scratch on the disk, the PLL1 path will be disturbed, and the clock obtained from this PLL circuit will be disturbed, making data processing impossible. Conventionally, as a countermeasure against this problem, the missing part of the reproduced signal is detected, and during this detection period, the voltage in the PLL circuit is
The output frequency of the CO is held at the frequency before detection.

As a method for detecting missing portions of reproduced signals, the sixth method has traditionally been used.
As shown in FIGS. A and B, a method is used in which predetermined detection levels (1) and (2) are set for the envelope of the reproduced signal.

[Problem that the invention seeks to solve]

The method for detecting the missing portion of the reproduced signal shown in FIGS. If the signal is missing due to noise, the missing portion cannot be detected even if the detection level is set.

[Means for solving problems]

In the present invention, the signal GFS, which detects the missing part of the frame synchronization signal described above, is effectively used as a detection signal for the missing part of the reproduced signal.

[Effect]

Since the above signal GFS is obtained even during the noise period,
The PLL circuit can hold the signal even when the signal is lost due to noise.

〔Example〕

FIG. 1 shows a first embodiment in which the present invention is applied to the above-mentioned CD player.

In the figure, a PLL circuit 1 includes a phase comparison circuit 2, a switch 3, a low-pass filter 4 made up of a resistor R4 and a capacitor C4, a DC amplifier 5, and a vCO 6. During normal operation, the switch 3 is turned on.

The phase comparison circuit 2 compares the phases of the clock extracted from the RF multiplied signal obtained from the pickup and the output of the vCO 6, and outputs an error signal E. This error signal ER
controls vCO6 through switch 3, low pass filter 4 and amplifier 5. As a result, it is possible to obtain the clock OLK whose phase is locked to the RF multiplied signal from the VAO 6.

On the other hand, a detection signal GF8 shown in FIG. 2, which detects the omission of the frame synchronization signal FS mentioned above, is applied to the input terminal 7. The rLJ portion of this signal GF8 is the synchronization signal Pa
shows the missing frame period. This signal GF8
The rising and falling edges of are synchronized with the synchronization signal FS. After the signal GFS is inverted by the inverter 8, it is differentiated by the capacitor C2 and the resistor hole 2, and the negative differential pulse is removed by the diode D1. As a result, a signal S1 as shown in FIG. 2 is obtained. Note that the differential time constant 02R is selected to be relatively large.

The signal S is applied to a comparator 9 and compared with a predetermined detection level Vs, whereby a switching signal SW shown in FIG. 2 is obtained from the comparator 9. The rHJ portion of this signal SW indicates a lack of synchronization signal, and
This shows a loss of the reproduced signal (RF signal).The loss of the reproduction signal due to scratches on the disk, etc. is longer than the period of one frame (for example, 0.13m5ec) (for example, 1m5e).
c), it is sufficiently detected from the signal SWl.

By turning off the switch 3 during the "H" period of the signal SW, the PLL circuit 1 is held and the VOO
6 free-running oscillates at the frequency immediately before switch 3 is turned off. During this free-running oscillation period, the disk is held at a predetermined speed by its inertia. Therefore, when the PLL circuit 1 is held, the clock OL obtained from the vao6
The synchronization between K and the RF flaw signal is maintained, and signal processing can be performed without error.

When the playback signal is no longer missing, the signal SW becomes rLJ, the switch 3 is turned on again, and the PLL circuit 1 returns to normal operation.

The maximum value of the pulse width T2 of the signal SW in FIG. 2 is set to a value that allows the clock OLK caused by free running of the VOO 5 and the RF flaw signal clock component to follow. This T2
The maximum value of is determined by the detection level Vs of the comparator 9.

Further, in this embodiment, by controlling the transistor 10 with the signal GF8, the capacitor Oj is connected to and disconnected from the capacitor C1, thereby changing the capture range of the PLL circuit 1. In this embodiment, when there is a signal dropout, the transistor 10 is turned on and the capacitor C is turned on.
By connecting 8 and narrowing the capture range,
During the hold period, no response is made to disturbances.

FIG. 3 shows a second embodiment of the present invention, in which the switching signal SW is created digitally.

In the figure, the N-ary counter 11 that counts the clock OLK starts counting when the signal GFS falls and is reset when the signal GFS rises, as shown in FIG. rHJ shown in FIG. 2 obtained during counting by this counter 11
The switch signal SW for controlling the switch 3 shown in FIG. 1 can be obtained from the AND gate 13 by applying the signal S1 and a signal obtained by inverting the 1 signal GFS by the inverter 12 to the AND gate 13. This signal S
The pulse width T2 of W can be changed by selecting a preset value of the counter 11.

The above description has been made regarding the case in which the present invention is applied to a CD player, but the present invention is also applicable to playback devices for other digital audio discs, digital video discs, or other recording media such as magnetic tapes on which digital signals are recorded. It can be applied to the device.

〔Effect of the invention〕

The PLL circuit can be held during a signal drop period due to noise, and data processing during this signal drop period can be performed without error.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. The figure is a timing chart showing the operation of Fig. 1, Fig. 5 is a waveform diagram showing a method for detecting a missing frame synchronization signal, and Fig. 6 is a waveform chart showing a method for detecting a missing #r of a reproduced signal. . In addition, in the symbols used in the drawings, 1...................................................PLL circuit 2...
・・・・・・・・・・・・・Phase comparison circuit 3・・・・
・・・・・・・・・・Switch 6・・・・・・・・・・
. . . VaOGF8 . . . Frame synchronization signal loss detection signal.

Claims (1)

[Scope of Claims] A reproducing device configured to reproduce a recording medium on which a digital signal is recorded, and configured to generate a clock from the reproduced signal by a PLL circuit and detect a lack of a synchronizing signal, comprising: Based on the signal in which the signal loss is detected, the above PL
A playback device that controls the operation of an L circuit.