JPH02241288A - Synchronizing clock generator - Google Patents

Abstract

PURPOSE:To always generate a stable synchronizing clock by dividing the frequency of a clock whose frequency corresponds to the output of a loop filter by a frequency dividing means, making an internal synchronizing signal and an internal subcarrier signal, and supplying the results to a synchronizing phase comparing means and a burst phase comparing means. CONSTITUTION:When phase relation between the burst and horizontal synchronizing signal in a video signal is different from the phase relation between the internal subcarrier signal and internal horizontal synchronizing signal to be made by a frequency dividing means 7, even in case that the direct current value of a burst phase difference signal is '0', a synchronizing phase difference signal has the direct current value deviated only for the different part of the phase relation. A high-pass filter 3 executes operation to remove this direct current value from the synchronizing phase difference signal and to remake the signal to the signal of the direct current value '0' same as the burst phase difference signal. In such a state, even when the burst phase difference signal is switched to the output of the high-pass filter 3 by a switching means 4, the direct current value is '0' together. Accordingly, stable operation can be continued without generating a large step.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronous clock generation device that generates a clock synchronized with a video signal reproduced from a recording medium.

When playing back a video signal recorded on a conventional recording medium such as a video disc, the video signal generally has a time axis error (
jitter). If there is such jitter in the reproduced signal, the effect will be a direct synchronization disturbance with respect to the video signal, and at the same time, if the video signal is a composite color signal, color unevenness will occur and the image quality will deteriorate.

Therefore, in this type of playback device, a synchronized clock that follows the fluctuations in the time axis of the video signal is generated, the video signal is temporarily written to the memory in synchronization with this clock, and then read from the memory using a stable reference clock. A time base corrector is often used to remove jitter from the video signal. As a synchronized clock generator used in such a time base collector, there is a system using a PLL (phase locked loop) as disclosed in, for example, Japanese Patent Laid-Open No. 5193817. FIG. 7 shows a block diagram of such a synchronous clock generator. The clock generated by the variable frequency oscillation means 6 is frequency-divided by the frequency dividing means 7 into an internal subcarrier signal and an internal horizontal synchronization signal, and these are supplied to the burst phase comparison means 2 and the synchronous phase comparison means 1, respectively. The center frequency of the clock oscillated by the variable frequency oscillation means 6 is selected to be a common multiple of the frequencies of the internal subcarrier and the internal horizontal synchronization signal. The burst phase comparison means 2 compares the phases of the burst of the manually input video signal and the internal subcarrier signal, and the synchronization phase comparison means 1 similarly compares the phases of the horizontal synchronization signal and the internal horizontal synchronization signal. The phase difference signals obtained by the two phase comparison means are combined by a synthesizer 19, and the variable frequency oscillation means 6 is controlled based on this signal, so that the clock follows the time axis fluctuation of the input video signal. .

Problems to be Solved by the Invention In such a synchronous clock generation device, phase comparison using bursts is generally more accurate than one using horizontal synchronization signals, so during the period of stable reproduction from a recording medium, It is preferable to use a burst phase difference signal. On the other hand, in periods where there is a large phase error that exceeds the phase comparison range of the burst phase comparison means, such as during loop pull-in operation, or in periods where there are no bursts in the video signal, such as vertical synchronization periods, the synchronization phase difference signal by the horizontal synchronization signal is used. There must be. Therefore, it is necessary to use the two phase difference signals by appropriately switching between them.

However, if the phase relationship between the horizontal synchronization signal of the video signal and the burst signal is not specified, an offset corresponding to the phase difference constantly exists between the burst phase difference signal and the synchronization phase difference signal. However, this results in a mismatch in the phase synchronization points between the two phase comparators. As a result, even if the loop is in a stable operating state using the burst phase difference signal, switching to the synchronous phase difference signal during the vertical synchronization period will generate a large phase error, and in some cases may cause synchronization. This caused the loop to become unstable. In addition, when a so-called track jump operation occurs in which the playback track of the recording medium is moved in the playback device, the video signals recorded on adjacent tracks may have a time axis shift. This resulted in a phase error that exceeded the phase comparison range of the first phase comparator, resulting in loss of synchronization, resulting in an unstable condition.

Means for Solving the Problems In order to solve the above problems, the synchronization clock generating means of the present invention compares the phase of the horizontal synchronization signal of the video signal reproduced from the recording medium and the internal horizontal synchronization signal to determine the synchronization position. synchronous phase comparison means for outputting a phase difference signal; burst phase comparison means for comparing the phases of the burst signal of the video signal and the internal subcarrier signal to output a burst phase difference signal; and a DC component of the synchronous phase difference signal. a high-pass filter for removing the burst phase difference signal, a switching means for switching between the burst phase difference signal and the output of the high-pass filter, a loop filter for correcting frequency and phase characteristics of the output of the switching means, and the loop filter. variable frequency oscillation means for generating a clock having a frequency according to the output of the clock, and dividing the frequency of the clock to generate the internal synchronization signal and the internal subcarrier signal, and supplying the internal synchronization signal and the internal subcarrier signal to the synchronization phase comparison means and the burst phase comparison means. It is equipped with a frequency dividing means.

The device also includes burst detection means for detecting the presence or absence of a burst signal or a defect in the video signal, and the switching means selects the output of the high-pass filter during a period in which there is no burst signal or a period in which there is a burst defect according to the output of the burst detection means. It is also possible to have a configuration in which

Further, it may be configured to include vertical synchronization separation means for detecting a vertical synchronization signal from the video signal, and the switching means selects the output of the high-pass filter during the period of the vertical synchronization signal according to the output of the vertical synchronization separation means.

Alternatively, a track jump signal indicating a jump in a reproduction track of the recording medium may be input, and the switching means may be configured to select the output of the high-pass filter for a predetermined period from the track jump according to the track jump signal.

Furthermore, the high-pass filter includes a low-pass filter for extracting a low-frequency component of the synchronous phase difference signal, a holding means for holding or passing an output value of the low-pass filter, and a holding means for extracting a low-frequency component of the synchronous phase difference signal, and a holding means for holding or passing an output value of the synchronous phase difference signal. The holding means may be configured to include a subtracter that subtracts the output to obtain a high-pass filter output, and the holding means performs a holding operation during a period when the switching means selects the output of the high-pass filter.

Operation The present invention eliminates the offset between one phase difference signal due to the phase difference between the burst signal of the video signal and the horizontal synchronization signal, thereby eliminating the adverse effects caused by switching the phase difference signal and providing a stable signal at all times. A synchronous clock can be generated.

Embodiment Hereinafter, a synchronous clock generator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a synchronous clock generation means according to an embodiment of the present invention, in which 1 is a synchronous phase comparison means, 2 is a burst phase comparison means, 3 is a high-pass filter, 4 is a switching means, and 5 is a loop. 6 is a variable frequency oscillation means, and 7 is a frequency dividing means. The clock generated by the variable frequency oscillation means 6 is frequency-divided by the frequency dividing means 7, and is supplied to the synchronous phase comparison means 1 and the burst phase comparison means 2 as an internal horizontal synchronization signal and an internal subcarrier signal. In addition to this, a video signal reproduced from a recording medium is supplied from point A to the synchronous phase comparison means 1 and the burst phase comparison means 2, respectively. The burst phase comparison means 2 compares the phases of the burst of the video signal and the internal subcarrier signal and outputs a burst phase difference signal.

The switching means 4 selects and outputs one of the two signals input according to a control signal given from point 0. Normally, the switching means 4 selects the burst phase difference signal, and the frequency of the variable frequency oscillation means 6 is controlled through the loop filter 5 based on the burst phase difference signal. As a result, control is applied so that the phases of the internal subcarrier signal and the burst of the video signal match, and a clock synchronized with the input video signal is obtained from the output (point B) of the variable frequency oscillation means 6. At this time, the DC value of the burst phase difference signal becomes 0. On the other hand, the synchronization phase comparison means 1 compares the phases of the horizontal synchronization signal of the video signal and the internal horizontal synchronization signal, and outputs a synchronization phase difference signal. If the phase relationship between the burst in the video signal and the horizontal synchronization signal is different from the phase relationship between the internal subcarrier signal and the internal horizontal synchronization signal generated by the frequency dividing means 7, when the burst phase comparison means 2 is used, When the synchronous phase comparison means 1 is used, a difference in phase synchronous points occurs. Therefore, even if the DC value of the burst phase difference signal is 0, the synchronous phase difference signal will have a DC value that is shifted by the difference in phase relationship. The high-pass filter 3 removes this DC value from the synchronous phase difference signal and outputs a DC value of 0, which is the same as the burst phase difference signal.
It works to correct the signal. In this state, even if the switching means 4 switches from the burst phase difference signal to the output of the high-pass filter 3, stable operation can be continued without producing a large step since the DC value is 0 in both cases.

However, the loop including this high-pass filter 3 is not controlled in terms of direct current, and actual phase errors gradually accumulate as time passes. Therefore,
When the switching means 4 next switches to the burst phase difference signal side, the phase error that has been accumulated up to that point will appear, and it will be necessary to pull back to the burst phase synchronization point again. Normally, phase comparison means using bursts has a narrow phase comparison range, so if the accumulated error is large, synchronization may occur. The speed at which the phase error accumulates depends on the time constant of the high-pass filter, so the time constant should be made long enough depending on the length of time that control through the high-pass filter must actually be continued. It is necessary to choose.

Next, the control of the switching means 4 will be explained with reference to FIGS. 2, 3, 4, and 5. FIG. 2 is a block diagram of an example of a circuit that generates a switching control signal for the switching means 4, in which 8 is a burst detection means, 9 is a vertical synchronization detection means, 10 is a monostable multi, and 11 is an OR gate. . Further, FIGS. 3, 4, and 5 are timing charts for explaining the operation of FIG. 2. Second
In the figure, a video signal is input from point D.

The burst detection means 8 detects the presence or absence of bursts or defects in the video signal. Specifically, it can be realized by, for example, a configuration in which the amplitude of the burst portion is detected and a comparator compares whether the amplitude is within a predetermined range. FIG. 3 shows the state of detection by the burst detector stage 8, where there is no burst signal as shown in the broken line on the second line of the video signal shown in (a), or on the third line. Detect areas disturbed by defects. Note that the signals indicated by lowercase letters in the figure represent the signals at the points indicated by the same uppercase letters in FIG. As shown in (b), the detection output maintains the "H" level after an abnormality is detected in the burst until the next normal burst is detected. If you set "'L" level, it will appear in the output as is. The output of the OR game 11 is connected to the 0 point in FIG. 1 to control the switching means 4. In this case, when the 0 point is "H level", the switching means 4 selects the output of the high-pass filter. Therefore, when there is no burst or a defect is detected, the switching means 4 selects the output of the high-pass filter. By selecting the output of the pass filter 3, it is possible to prevent the influence of burst abnormalities.

The vertical synchronization detection means 9 detects the vertical synchronization signal of the video signal as shown in FIG. 4, and outputs the "'H" level during that period. Similarly to the above case, the switching means 4 selects the output of the high-pass filter 3 during the "Ho" level period. In the video signal, there may be no burst during the vertical synchronization signal period, and the burst phase difference signal cannot be used during this period. If the burst detection means 8 described above is used, a switching signal can be obtained during this period, but since playback devices generally use vertical synchronization signals to control other circuits, the vertical synchronization detection means 9 is used for this purpose. [This is simpler than burst detection.] Also,
Some discs, such as video discs, record bursts during the vertical synchronization period, but sync chip bursts are susceptible to waveform distortion due to the influence of clamps and A/D converters required for digitization, and burst phase comparison Depending on the configuration of the means 2, a normal phase difference signal may not be obtained. Even in this case, synchronization can be stabilized by using the vertical synchronization detection means 9.

Furthermore, when a playback device performs a so-called track jump operation in which the playback track of the recording medium is moved, the playback track before and after the jump has a constant angular velocity (CA).
Even if the horizontal synchronization signals are generally aligned, as is the case with video discs recorded in V), there is usually some deviation in the time axis. Therefore, even if the burst phase difference signal settles to almost 0 immediately before the jump, it will have a phase difference corresponding to the deviation immediately after the jump. If the deviation is large, it will exceed the phase comparison range of the burst phase comparison means 2 and cause the burst phase to be synchronized to be lost, resulting in loss of synchronization. Therefore, even in this case, loss of synchronization can be prevented by once pulling in the synchronization point before the jump using the synchronization phase difference signal passed through a high-pass filter, and then switching to the burst phase difference signal. Specifically, a track jump signal indicating a jump in the reproduced track is given from point E in FIG. 2, and as shown in FIGS. 11 to the switching means 4. Note that, as the jump signal, a track jump command outputted from a system control circuit, a microcomputer, etc. to a tracking control circuit in the playback device can be used. Alternatively, a signal indicating that the read position by the playback device has deviated from the track may be used. Further, the stretching time by the monostable multi 10 is determined according to the time required to draw the loop in order to perform the above-described operation.

FIG. 6 shows a circuit diagram of a specific configuration example in which the high-pass filter 3 is realized by a digital circuit.

If the loop continues to operate using the synchronized phase difference signal passed through the high-pass filter 3, there is a problem that phase errors gradually accumulate as mentioned earlier, but this configuration solves that problem. It is. In the 6th session, 12
is an adder, 13 is a latch, 14 is a constant multiplier, 15
1 is a subtracter, 16 is a NOR gate, and 17 is a clock pulse generation circuit. A portion 18 surrounded by a broken line, that is, an adder 12 and a latch 13 constitute an integrator, which integrates a signal at a point using a clock pulse supplied from a clock pulse generation circuit 17 through a NOR gate 16.

The integrator 18, arithmetic unit 14, and subtracter 15 collectively constitute a feedback type high-pass filter. If the output of the integrator 18 is O in the initial state, the synchronized phase difference signal inputted from five points will be output as is to the point, but if the synchronized phase difference signal has a DC component, the integrator 18 will convert that component. After integration, the output of the arithmetic unit 14 becomes equal to the DC value of the synchronous phase difference signal, that is, the DC value of the signal output at the point is O.
It settles in the state where it becomes. The time constant of this filter is determined by the frequency of the supplied clock pulse and the gain of the arithmetic unit 14. Here, if the same signal as the 0 point in FIG. 1 is supplied to the 1 point, the 1 point is at "L" level during the period when the switching means 4 selects the burst phase difference signal, and the clock pulse is passes through the NOR gate, so this circuit operates as a high-pass filter. At this time, a low frequency component of the synchronous phase difference signal, in other words, a value approximately equal to the DC component appears in the output of the arithmetic unit 14. Next, during the period in which the switching means 4 selects the output of the high-pass filter 3, one point becomes the "Ho" level and the output of the NOR gate 16 is fixed at the "L" level. Therefore, the integrator 18 receives the clock pulse is not supplied, and the latch 13 is in a state where it holds the value immediately before the switching means 4 switches.

That is, the output of the arithmetic unit 14 is fixed at a value approximately equal to the DC component of the synchronous phase difference signal, and the value obtained by subtracting the fixed value from the synchronous phase difference signal by the subtracter 15 is output at point K. Therefore, in this state, the high-pass filter 3 does not act as a high-pass filter, but simply subtracts a constant value, so that the problem of accumulation of phase errors as described above does not occur. Note that the arithmetic unit 14 only needs to realize constant multiplication; for example, it may only perform bit shifting. Further, it is not necessarily necessary to provide a clock pulse generation circuit independently for this filter, and for example, one obtained by dividing the frequency of the synchronous clock generated by the variable frequency oscillation means 6 may be used. Although FIG. 2 shows an example in which all of the burst detection means 8, vertical synchronization detection means 9, and trunk jump signal are used, only the necessary ones may be extracted and used depending on the purpose. .

Furthermore, the high-pass filter is not limited to the configuration shown in FIG. 6 as long as it removes low-frequency components. The circuit may be implemented digitally or analogously, or may be implemented using software. For example, the configuration may be composed of a low-pass filter that extracts a low-frequency component from the synchronous phase difference signal and a subtracter that subtracts its output from the synchronous phase difference signal, or it may be a simple high-pass filter using CR. .

The vertical synchronization detection means does not necessarily have to be configured to directly detect the video signal; for example, it may operate a counter using the horizontal synchronization signal in synchronization with the vertical synchronization signal that has been separated, and then decode the counter to generate the necessary signal. It may also be configured such that.

There is no particular limitation on the implementation method of the monostable multi as long as it generates timing for switching the switching means for a roughly predetermined period from a given trunk jump signal.

It can be realized using analog circuits, digital circuits, or software.

Effects of the Invention As described above, according to the present invention, it is possible to realize a synchronous clock generation device that eliminates the adverse effects that occur when switching between a burst phase difference signal and a synchronous phase difference signal and always generates a stable synchronous clock. . Furthermore, instability and loss of synchronization that occur when moving the reproduction track of the recording medium, such as during a track jump operation, can be prevented.

[Brief explanation of drawings]

The first part is a block diagram of an embodiment of a synchronous clock generator according to the present invention, the second part is a block diagram of an example of a circuit that generates a switching control signal, and FIGS. 3 to 5 explain FIG. FIG. 6 is a timing diagram, FIG. 6 is a circuit diagram of an example of a high-pass filter, and FIG. 7 is a block diagram of a conventional synchronous clock generator. 1... Synchronous phase comparison means, 2... Burst phase comparison means, 3... High pass filter,
4... Switching means, 5... Loop filter, 6... Variable frequency oscillation means, 7...
... Frequency division means.

Claims (5)

[Claims] (1) A synchronization phase comparison means that compares the phases of a horizontal synchronization signal of a video signal reproduced from a recording medium and an internal horizontal synchronization signal and outputs a synchronization phase difference signal, and a burst signal of the video signal and an internal subcarrier. burst phase comparison means for comparing the phase with a signal and outputting a burst phase difference signal; a high-pass filter for removing a DC component of the synchronized phase difference signal; and a combination of the burst phase difference signal and the high-pass filter. a loop filter that corrects the frequency and phase characteristics of the output of the switching means; variable frequency oscillation means that generates a clock having a frequency according to the output of the loop filter; 1. A synchronous clock generation device comprising frequency dividing means for generating the internal synchronization signal and the internal subcarrier signal and supplying the internal synchronization signal and the internal subcarrier signal to the synchronization phase comparison means and the burst phase comparison means. (2) A burst detection means for detecting the presence or absence of a burst signal or a defect in the video signal is provided, and the switching means switches the output of the high-pass filter during a period when there is no burst signal or during a period when there is a burst defect according to the output of the burst detection means. The synchronous clock generation device according to claim 1, wherein the synchronous clock generation device selects the synchronous clock. (3) A vertical synchronization separation means for detecting a vertical synchronization signal from a video signal is provided, and the switching means selects the output of the high-pass filter during the period of the vertical synchronization signal according to the output of the vertical synchronization separation means. A synchronous clock generation device according to claim (1). (4) A track jump signal indicating a jump in a playback track of the recording medium is input, and the switching means selects the output of the high-pass filter for a predetermined period from the track jump according to the track jump signal. (1) The synchronous clock generator described in (1). (5) The high-pass filter includes a low-pass filter for extracting a low-frequency component of the synchronous phase difference signal, a holding means for holding the output value of the low-pass filter, and an output of the holding means from the synchronous phase difference signal. Claim (1), further comprising a subtracter for subtracting the output from the high-pass filter, and wherein the holding means performs a holding operation during a period in which the switching means selects the output of the high-pass filter. The synchronous clock generation device according to any one of (4) to (4).