JPH02226553A - Reproducing clock protection circuit - Google Patents

Abstract

PURPOSE:To remarkably shorten lock time after recovering drop out by providing a drop out detector, an oscillator to output prescribed data, and a switching means to switch the input of a PLL circuit. CONSTITUTION:When the drop out of a reproducing signal occurs, the drop out detector 4 detecting the drop out is operated, and the switching means 6 is switched from the connection side of a pulse detector 1 to that of the oscillator 5. Thereby, data consisting of a binary signal with the same frequency as the highest frequency in reproducing data is inputted to the PLL circuit 2 from the oscillator 5. Therefore, a reproducing clock outputted from the circuit 2 is corrected so as to synchronize its phase with the output of the oscillator 5, however, the frequency is kept as a normal frequency. When the drop out is recovered, the means 6 is switched again, and the output of the detector 1 i.e. the reproducing data is immediately inputted to the circuit 2. However, since the frequency of the reproducing clock is kept at a normal level, it is enough to correct only a phase error at the circuit 2, thereby, a synchronized reproducing signal can be obtained in a short time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to, for example, PCM audio and digital VTR.
Regarding the recovered clock protection circuit used when reproducing digital information in etc., in particular, it is possible to shorten the lock-in time of the PLL circuit after the digital information reproduction signal drops out in the data area or preamble area and recovers. This invention relates to a recovered clock protection circuit.

[Conventional technology]

Generally, when reproducing digital information in PCM audio, digital VTR, etc., the reproduced signal is reproduced in a non-rectangular waveform as shown in FIG. 2(a) or FIG. 4(a). Conventionally, a reproduced signal detection circuit as shown in FIG. 3 has been used to detect digital information corresponding to recording, ie, reproduced data, from this reproduced signal.

In this reproduced signal detection circuit, first, the pulse detector 1 compares the reproduced signal with a predetermined threshold signal, as shown in FIG. 2(b).
Alternatively, it is converted into reproduction data consisting of a binary signal of "1" and "0" as shown in FIG. 4(b). In order to determine the signal value of this reproduced data, a reproduced clock synchronized with the reproduced data as shown in FIG. 2(c) is generated by a PLL (phase locked loop) circuit 2.
By inputting the reproduced data to the D terminal of the D-flip-flop (D-F/F) 3 and inputting this reproduced clock to the clear preset terminal CP, the reproduced data is changed as shown in FIG. 2(d). The detection data is converted into detection data consisting of a high-level signal of 1° and "0" synchronized with a reproduced clock.

The PLL circuit 2 includes a phase comparator that compares the phase of an input signal and an output signal, a low-pass filter that integrates the output of this phase comparator to obtain an error voltage, and inputs this error voltage as a control voltage. voltage controlled oscillator (VCO)
The phase difference between the input signal and the vCO signal is 9.
When it reaches 0°, the error voltage becomes O and the device is configured to enter a locked state. Therefore, some time is required for the reproduced clock to enter a locked state in synchronization with the reproduced data, and this time is called lock-in time.

Detection data detected from the reproduced data while the reproduced data and the reproduced clock are not synchronized (locked) as shown in FIG. 4(C) is an error as shown in FIG. 4(d). Become. In particular, since the reproduced data is not necessarily a signal whose on-time and off-time are repeated at a constant cycle, even if the reproduced data is suddenly input to the PLL circuit 2, a reproduced clock synchronized with the reproduced data can be obtained within a short time. This is difficult and increases the lock-in time and error rate.

Therefore, when recording digital data, a preamble is provided at the beginning of the data to synchronize the reproduced clock, as shown in Figure 5, and a preamble is provided at the end of the data to synchronize the reproduced clock immediately after data detection. A postamble is provided to prevent the disc from coming off. In order to synchronize the reproduced clock of the PLL circuit 2 with the reproduced data as soon as possible, it is better to have a short cycle of the reproduced data, so -a
In the preamble and postamble, data with the shortest period, that is, with the highest frequency, among the reproduced data is continuously recorded. In this way, if the PLL circuit 2 is quickly locked in during the preamble period, errors in detected data detected by the reproduced clock will not occur during data reproduction.

[Problem to be solved by the invention]

However, when a dropout occurs in the reproduced signal in the data area, as shown in FIGS. 6(a) and 6(ao), the reproduced data is lost and The period may be greatly disturbed, the reproduced clock may not be able to follow fluctuations in the reproduced data, and the PLL circuit 2 may become unlocked. In this case, when the dropout is recovered, the lock state of the PLL circuit 2 is recovered again. However, in this case, when the dropout recovers, the reproduced signal in the data area suddenly changes to the PLL circuit 2.
, it is difficult to recover the lock state within a short time after dropout recovery, resulting in a large amount of errors following the dropout region. Furthermore, a similar problem may occur when dropout occurs in the reproduced signal in the preamble region.

[Means to solve the problem]

In order to solve the above problems, the recovered clock protection circuit of the present invention uses a pulse detector to convert a reproduced signal into reproduced data consisting of a binary signal, and uses a PLL circuit to generate a reproduced clock synchronized with this reproduced data. A reproduced clock protection circuit attached to the reproduced clock generation circuit includes a dropout detector that detects dropout of the reproduced signal, an oscillator that outputs data consisting of a binary signal having the same frequency as the regular reproduced clock, and the aforementioned When the dropout detector detects a dropout of the playback signal, the PL
switching means for switching the power of the L circuit from the output of the pulse detector to the output of the oscillator, and lock-in of the PLL circuit after recovery from dropout occurring in the data region or preamble region of the digital information reproduction signal. It is characterized by being configured to shorten the time.

[For production]

With the above configuration, when a dropout of the reproduced signal is detected by the dropout detector, the switching means is switched and data consisting of a binary signal of a predetermined frequency output from the oscillator is input to the PLL circuit, and the reproduced clock is input to the PLL circuit. The phase and frequency of will be determined by the data output by the oscillator. Since the oscillation frequency of this oscillator is the same frequency as the regular reproduced clock, that is, the highest frequency in the reproduced data, the frequency of the reproduced clock after the reproduced signal is lost can be maintained at the regular frequency.

When the dropout is recovered, the switching means is switched again, and the output of the pulse detection circuit, that is, the reproduced data, is suddenly input to the PLL circuit.

However, the frequency of the recovered clock during the dropout period is maintained at the oscillation frequency of the oscillator, that is, the frequency of the regular recovered clock, so after the dropout is recovered, the PLL circuit only needs to correct the phase error. Often, this can significantly reduce lock-in time after dropout recovery.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 and 2.

As shown in FIG. 1, the playback lock protection circuit includes a dropout detection circuit 4 that inputs a playback signal and detects a dropout of the playback signal, and a dropout detection circuit 4 that inputs a playback signal and detects a dropout of the playback signal. The oscillator 5 generates data consisting of a binary signal that alternately repeats two values of "0" and "0", and the PLL is activated by the detection result of the dropout detection circuit 4.
It has switching means 6 for switching the input of the circuit 2 to either the output of the pulse detector 1 or the oscillator 5.

The pulse detector 1 inputs a predetermined threshold signal from the outside and generates a reproduced signal as shown in FIG. 2(a).
), and its output is as follows:
The signal is output to the PLL circuit 2 via the switching means 6, and to the D terminal of the D-flip-flop 3.

Further, the PLL circuit 2 has a known configuration, and its output is input to the clear preset terminal CP of the D-flip-flop 3.

In this reproduced clock protection circuit, when a dropout of the reproduced signal occurs, the dropout detector 4 detecting this is activated and switches the switching means 6 from the side connected to the pulse detector 1 to the side connected to the oscillator 5. As a result, data consisting of a binary signal having the same frequency as the highest frequency in the reproduced data is transmitted from the oscillator 5 to the PLL circuit 2.
is man-powered. Therefore, the phase of the reproduced clock output from the PLL circuit 2 is corrected to be synchronized with the output of the oscillator 5, but its frequency is maintained at the normal frequency.

When the dropout of the reproduced signal is recovered, the switching means 6 is switched again, and the output of the pulse detection circuit 1, that is, the reproduced data, is suddenly input to the PLL circuit 2.

However, since the frequency of the reproduced clock during the dropout period is maintained at the normal frequency, after the dropout has been recovered, the PLL circuit 2 only needs to correct the phase error, which allows the reproduced clock to be transferred within a short time. It is possible to obtain a regenerated clock that is synchronized with the , and it is possible to narrow the area where errors occur after recovery from dropout.

〔Effect of the invention〕

As described above, the recovered clock protection circuit of the present invention includes a dropout detector that detects a dropout of a reproduced signal, an oscillator that outputs data consisting of a binary signal having the same frequency as a normal reproduced signal, and a dropout detector that detects a dropout of a reproduced signal. and switching means for switching the input of the PLL circuit from the output of the pulse detector to the output of the oscillator when the detector detects dropout of the reproduced signal.

As a result, the reproduced clock after the reproduction signal is lost is maintained at its normal frequency. When the dropout is recovered, the switching means is switched again, and the output of the pulse detection circuit, that is, the reproduced data, is suddenly input to the PLL circuit. However, since the frequency of the recovered clock during the dropout period is kept at the regular frequency, after the dropout recovers, the PLL
The circuit only needs to correct the phase error, which has the effect of shortening the lock-in time after dropout recovery.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, in which FIG. 1 is a block circuit diagram showing a reproduced data detection circuit and a reproduced clock protection circuit, and FIG. 2 is a block circuit diagram showing each signal in a locked state. FIG. Fig. 3 is a block circuit diagram showing a conventional reproduction data detection circuit, Fig. 4 is a timing diagram of each signal in an unlocked state, and Fig. 5 is an explanatory diagram showing the structure of recorded data with preamble and postamble. , FIG. 6 is a waveform diagram of a reproduced signal and reproduced data when dropout occurs in the data area. 1 is a pulse detector, 2 is a PLL circuit, 4 is a dropout detector, 5 is an oscillator, and 6 is a switching means. Thatch 42 Scream

Claims (1)

[Claims] 1. A reproduced clock attached to a reproduced clock generation circuit that converts a reproduced signal into reproduced data consisting of a binary signal using a pulse detector and generates a reproduced clock synchronized with this reproduced data using a PLL circuit. The protection circuit includes a dropout detector that detects dropouts in the reproduced signal, an oscillator that outputs data at the same frequency as the frequency of a regular reproduced clock, and a dropout detector that detects dropouts in the reproduced signal. and switching means for switching the input of the PLL circuit from the output of the pulse detector to the output of the oscillator.