JPS62129854U

JPS62129854U -

Info

Publication number: JPS62129854U
Application number: JP1638886U
Authority: JP
Priority date: 1986-02-06
Filing date: 1986-02-06
Publication date: 1987-08-17

Description

[Brief explanation of drawings]

第１図は本考案のビツトタイミング抽出回路の
一実施例を示すブロツク図、第２図は本実施例に
おける各信号のタイミングチヤート、第３図は従
来のタイミング抽出回路例を示すブロツク図、第
４図はその各信号のタイミングチヤートである。１……トランジシヨン検出回路、２……１ビツ
ト遅延回路、３……トランジシヨン検出用フリツ
プフロツプ、４……トランジシヨンフラグフリツ
プフロツプ、５……インバータ、６……切換回路
、７……位相差検出用フリツプフロツプ、８……
ループフイルタ、９……ＶＣＯ、ａ……入力デー
タ、ｂ……トランジシヨン信号、ｃ……１ビツト
遅延トランジシヨン信号、ｄ……ローカルクロツ
ク、ｅ……イネーブル信号、ｆ……位相差出力、
……反転されたローカルクロツクｄ。 FIG. 1 is a block diagram showing an embodiment of the bit timing extraction circuit of the present invention, FIG. 2 is a timing chart of each signal in this embodiment, and FIG. 3 is a block diagram showing an example of a conventional timing extraction circuit. Figure 4 is a timing chart of each signal. DESCRIPTION OF SYMBOLS 1...Transition detection circuit, 2...1 bit delay circuit, 3...Flip-flop for transition detection, 4...Transition flag flip-flop, 5...Inverter, 6...Switching circuit, 7... Flip-flop for phase difference detection, 8...
Loop filter, 9...VCO, a...input data, b...transition signal, c...1-bit delayed transition signal, d...local clock, e...enable signal, f...phase difference output ,
...inverted local clock d.

Claims

[Claims for Utility Model Registration] In a bit timing extraction circuit that extracts the bit timing of a PCM signal using a phase synchronized oscillator, a transition detection circuit that outputs a transition signal when a transition in a 1-bit section of the PCM signal is detected. a 1-bit delay circuit that delays the output signal of the transition detection circuit by one bit of the PCM signal and outputs the delayed signal; an inverter that inverts the local clock output from the VCO of the phase-locked oscillator; and a transition detection circuit. A discrimination circuit inputs the output and a local clock and determines whether a transition signal is missing in a 1-bit section of the input PCM signal, and the output of the discrimination circuit determines whether a transition signal is missing in a 1-bit section. When there is no dropout, output from the inverter, and when there is no dropout, output from the 1-bit delay circuit.
A bit timing extraction circuit comprising a switching circuit for outputting to a phase difference detection circuit of each phase synchronized oscillator.