JPS61103936U - - Google Patents
Info
- Publication number
- JPS61103936U JPS61103936U JP18737584U JP18737584U JPS61103936U JP S61103936 U JPS61103936 U JP S61103936U JP 18737584 U JP18737584 U JP 18737584U JP 18737584 U JP18737584 U JP 18737584U JP S61103936 U JPS61103936 U JP S61103936U
- Authority
- JP
- Japan
- Prior art keywords
- controlled oscillator
- voltage
- frequency dividing
- shift register
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図はこの考案の並列―直列変換回路の一実
施例を示すブロツク図、第２図は第１図に示した
並列―直列変換回路における主要な波形図、第３
図は従来の並列―直列変換回路の一例を示すブロ
ツク図、第４図は第３図に示した従来の並列―直
列変換回路を説明するための波形図である。
図中、１０はシフトレジスタ、２０はＰＬＬ回
路、２１は位相比較器、２２はローパスフイルタ
、２３は電圧制御発振器、２４は１／Ｎ分周回路
である。
Figure 1 is a block diagram showing an embodiment of the parallel-to-serial conversion circuit of this invention, Figure 2 is a diagram of the main waveforms in the parallel-to-serial conversion circuit shown in Figure 1, and Figure 3 is a diagram showing major waveforms in the parallel-to-serial conversion circuit shown in Figure 1.
The figure is a block diagram showing an example of a conventional parallel-to-serial conversion circuit, and FIG. 4 is a waveform diagram for explaining the conventional parallel-to-serial conversion circuit shown in FIG. 3. In the figure, 10 is a shift register, 20 is a PLL circuit, 21 is a phase comparator, 22 is a low-pass filter, 23 is a voltage controlled oscillator, and 24 is a 1/N frequency dividing circuit.
Claims (1)
発振器と、分周回路とによつて、システムクロツ
ク信号に同期するＰＬＬ回路を構成し、前記電圧
制御発振器の出力をシフトレジスタのシフトクロ
ツク端子に供給すると共に、前記分周回路の出力
の前記シフトレジスタのロード端子に接続したこ
とを特徴とする並列―直列変換回路。 A phase comparator, a low-pass filter, a voltage-controlled oscillator, and a frequency dividing circuit constitute a PLL circuit synchronized with a system clock signal, and supply the output of the voltage-controlled oscillator to a shift clock terminal of a shift register. and a parallel-to-serial conversion circuit, characterized in that an output of the frequency dividing circuit is connected to a load terminal of the shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18737584U JPS61103936U (en) | 1984-12-12 | 1984-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18737584U JPS61103936U (en) | 1984-12-12 | 1984-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103936U true JPS61103936U (en) | 1986-07-02 |
Family
ID=30744840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18737584U Pending JPS61103936U (en) | 1984-12-12 | 1984-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103936U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947571A (en) * | 1972-09-09 | 1974-05-08 |
-
1984
- 1984-12-12 JP JP18737584U patent/JPS61103936U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947571A (en) * | 1972-09-09 | 1974-05-08 |
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