JPH02111936U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a PLL circuit with a phase synchronization state detection circuit according to an embodiment of the invention, and FIG.
3 is a block diagram of a conventional PLL circuit with a phase synchronization detection circuit, and FIG. 4 is a signal waveform diagram of various parts of the circuit shown in FIG. 3. In the figure, 1 is a 1/N frequency divider, 2 is a phase comparator, 3 is a loop filter, 4 is a piezoelectrically controlled oscillator,
5 is a 1/M frequency divider, and 6 is a peak value detection circuit (phase synchronization state detection circuit). Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims for Utility Model Registration] A phase comparator that detects a phase difference between two input signals; a loop filter that removes unnecessary high frequency components from the output signal of the phase comparator; and a control for the output signal of the loop filter. a voltage controlled oscillator that inputs the output signal of the voltage controlled oscillator and supplies one of the two input signals of the phase comparator; and a 1/M frequency divider that inputs an input signal from the outside. P with a 1/N frequency divider supplying the remaining one of the two input signals of the phase comparator as
A PLL with a phase synchronization state detection circuit, characterized in that the LL circuit is equipped with a phase synchronization state detection circuit that detects a state of change in the voltage value of the output signal of the loop filter and outputs a detection signal of an out-of-phase synchronization state. circuit.