JPS6150346U - - Google Patents
Info
- Publication number
- JPS6150346U JPS6150346U JP13412784U JP13412784U JPS6150346U JP S6150346 U JPS6150346 U JP S6150346U JP 13412784 U JP13412784 U JP 13412784U JP 13412784 U JP13412784 U JP 13412784U JP S6150346 U JPS6150346 U JP S6150346U
- Authority
- JP
- Japan
- Prior art keywords
- loop filter
- output
- sequential loop
- digital
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はデイジタル位相同期回路のブロツク図
、第２図は第１図の回路の特性を説明する図、第
３図は従来のシーケンシヤルループフイルタの具
体例を示す図、第４図は第３図の回路の特性を示
す図、第５図は従来のシーケンシヤルループフイ
ルタの他の例を示す図、第６図及び第７図は本考
案の実施例の回路図、第８図は第６図の回路の動
作の一例を示すタイミングチヤートである。
主要部分の符号の説明、１…位相比較器、２…
シーケンシヤルループフイルタ、３…ＶＣＯ、２
１〜２３，２６，２９，３１…カウンタ、２４，
２５，２８，３０…オアゲート。
Figure 1 is a block diagram of a digital phase locked circuit, Figure 2 is a diagram explaining the characteristics of the circuit in Figure 1, Figure 3 is a diagram showing a specific example of a conventional sequential loop filter, and Figure 4 is a diagram illustrating the characteristics of the circuit in Figure 1. 3 is a diagram showing the characteristics of the circuit, FIG. 5 is a diagram showing another example of a conventional sequential loop filter, FIGS. 6 and 7 are circuit diagrams of an embodiment of the present invention, and FIG. 7 is a timing chart showing an example of the operation of the circuit shown in FIG. 6; Explanation of symbols of main parts, 1... Phase comparator, 2...
Sequential loop filter, 3...VCO, 2
1 to 23, 26, 29, 31...counter, 24,
25, 28, 30...or gate.
Claims (1)
を位相比較してこの比較結果を２値量子化して導
出する位相比較器と、この位相比較器の出力を入
力として前記電圧制御発振器の制御信号を発生す
るシーケンシヤルループフイルタとを含むデイジ
タル位相同期回路であつて、前記シーケンシヤル
ループフイルタをプログラマブルカウンタにて構
成して、前記シーケンシヤルループフイルタの出
力により前記プログラマブルカウンタのカウント
数を制御自在としてなることを特徴とするデイジ
タル位相同期回路。 A phase comparator that compares the phases of an input wave and an output wave of the digital voltage controlled oscillator and binary quantizes and derives the comparison result, and generates a control signal for the voltage controlled oscillator using the output of this phase comparator as input. A digital phase synchronized circuit including a sequential loop filter, wherein the sequential loop filter is configured with a programmable counter, and the count number of the programmable counter can be freely controlled by the output of the sequential loop filter. A digital phase-locked circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13412784U JPS6150346U (en) | 1984-09-04 | 1984-09-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13412784U JPS6150346U (en) | 1984-09-04 | 1984-09-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6150346U true JPS6150346U (en) | 1986-04-04 |
Family
ID=30692647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13412784U Pending JPS6150346U (en) | 1984-09-04 | 1984-09-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6150346U (en) |
-
1984
- 1984-09-04 JP JP13412784U patent/JPS6150346U/ja active Pending
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