JPH0262836U

JPH0262836U -

Info

Publication number: JPH0262836U
Application number: JP13990788U
Authority: JP
Priority date: 1988-10-28
Filing date: 1988-10-28
Publication date: 1990-05-10

Description

[Brief explanation of drawings]

図は本発明の一実施例の基準クロツクから従属
クロツクを作成するＰＬＬ回路のブロツク図であ
る。１……フイードバツク用分周回路、２……従属
クロツク用分周回路、３……ＶＣＯ、４……基準
クロツク、５……従属クロツク、６……フイード
バツククロツク、７……基準クロツク切替信号、
８……セツトパルス、９……セツトパルス作成回
路、１０……位相比較回路、１１……基準クロツ
クセレクタ。 The figure is a block diagram of a PLL circuit for creating a dependent clock from a reference clock according to an embodiment of the present invention. 1...Feedback frequency divider circuit, 2...Slave clock frequency divider circuit, 3...VCO, 4...Reference clock, 5...Slave clock, 6...Feedback clock, 7...Reference clock switching signal,
8...Set pulse, 9...Set pulse generation circuit, 10...Phase comparison circuit, 11...Reference clock selector.

Claims

[Scope of utility model registration request]

In a circuit that selects one reference clock from a plurality of reference clocks and creates a slave clock synchronized with it using a PLL circuit, a frequency divider circuit for feedback, a frequency divider circuit for slave clocks, and a reference clock after switching between the reference clocks are used. A circuit for reducing lock time required, further comprising a circuit for creating a pulse for setting a feedback frequency divider circuit.