JPS63131467U - - Google Patents
Info
- Publication number
- JPS63131467U JPS63131467U JP2207987U JP2207987U JPS63131467U JP S63131467 U JPS63131467 U JP S63131467U JP 2207987 U JP2207987 U JP 2207987U JP 2207987 U JP2207987 U JP 2207987U JP S63131467 U JPS63131467 U JP S63131467U
- Authority
- JP
- Japan
- Prior art keywords
- frequency division
- pll circuit
- band
- tuner
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一実施例の選局回路の制御装
置を示すブロツク図、第２図は第１図の装置の制
御シーケンスを示すフローチヤート、第３図は従
来の装置の制御シーケンスを示すフローチヤート
、第４図は従来の装置でＶＨＦのローバンドから
ハイバンドに切り換えた場合のＶＣＯ制御電圧の
変化を示すグラフ、第５図はあるバンドにおける
ＶＣＯ発振出力レベルの周波数特性を示すグラフ
である。
１１…チユーナ、１２…ＰＬＬ回路、１４…マ
イクロコンピユータ、１５…バンド切換回路、１
６…プリスケーラ、１７…プログラマブル分周器
、１８…位相比較器、２０…シフトレジスタ、２
１…分周データラツチ。
FIG. 1 is a block diagram showing a control device for a channel selection circuit according to an embodiment of the present invention, FIG. 2 is a flowchart showing a control sequence of the device in FIG. 1, and FIG. 3 is a control sequence of a conventional device. Figure 4 is a graph showing the change in VCO control voltage when switching from VHF low band to high band in a conventional device, and Figure 5 is a graph showing the frequency characteristics of the VCO oscillation output level in a certain band. be. 11... Tuner, 12... PLL circuit, 14... Microcomputer, 15... Band switching circuit, 1
6... Prescaler, 17... Programmable frequency divider, 18... Phase comparator, 20... Shift register, 2
1...Divided data latch.
Claims (1)
器との周波数、位相を比較し、その比較電圧にて
チユーナを選局制御するＰＬＬ回路と、 チヤンネル操作信号が入力され、入力処理後、
バンド判別し、更に分周データを算出して該分周
データを前記ＰＬＬ回路に対し出力した後、前記
ＰＬＬ回路内の分周データラツチに対しデータラ
ツチ用ロードパルスを出力し、然る後にバンドデ
ータをバンド切換回路に対し出力し、ＰＬＬ回路
の分周制御を行なうと共に、チユーナのバンド切
換制御を行なう制御手段とを具備したことを特徴
とする選局回路の制御装置。[Claims for Utility Model Registration] A PLL circuit that divides the tuner's local oscillator output, compares the frequency and phase with a reference oscillator, and controls tuner tuning using the comparison voltage, and a channel operation signal is input. , after input processing,
After identifying the band, calculating frequency division data and outputting the frequency division data to the PLL circuit, a data latch load pulse is output to the frequency division data latch in the PLL circuit, and then the band data is output. 1. A control device for a tuning circuit, comprising: control means for outputting to a band switching circuit, controlling frequency division of a PLL circuit, and controlling band switching of a tuner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207987U JPS63131467U (en) | 1987-02-19 | 1987-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207987U JPS63131467U (en) | 1987-02-19 | 1987-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63131467U true JPS63131467U (en) | 1988-08-29 |
Family
ID=30819120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2207987U Pending JPS63131467U (en) | 1987-02-19 | 1987-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63131467U (en) |
-
1987
- 1987-02-19 JP JP2207987U patent/JPS63131467U/ja active Pending
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