JPS6363136B2 - - Google Patents

Info

Publication number
JPS6363136B2
JPS6363136B2 JP54033091A JP3309179A JPS6363136B2 JP S6363136 B2 JPS6363136 B2 JP S6363136B2 JP 54033091 A JP54033091 A JP 54033091A JP 3309179 A JP3309179 A JP 3309179A JP S6363136 B2 JPS6363136 B2 JP S6363136B2
Authority
JP
Japan
Prior art keywords
frequency
frequency divider
output
broadcasts
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54033091A
Other languages
Japanese (ja)
Other versions
JPS55124332A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3309179A priority Critical patent/JPS55124332A/en
Publication of JPS55124332A publication Critical patent/JPS55124332A/en
Publication of JPS6363136B2 publication Critical patent/JPS6363136B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer

Description

【発明の詳細な説明】 本発明はテレビ放送とFM放送を受信できるよ
うにしたPLL回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit capable of receiving television broadcasts and FM broadcasts.

第１図のPLL回路において、１は基準周波数
発振器、２は発振器１の出力を１／P1に分周する第 １分周器、３は位相比較器、４は低域濾波器、５
はチユーナの電圧制御型発振器、６は前記電圧制
御型発振器５の発振出力を１／P2に分周する第２分 周器、７は分周制御信号S1に応じて前記第２分周
器６の出力を分周する可変分周器である。この
PLL回路は位相比較器３に入力される比較信号、
即ち第１分周器２の出力と可変分周器７の出力が
同一周波数になるようにループが働くから、今、
可変分周器７の分周比をP3とし、基準周波数発
振器１の発振周波数をO、電圧制御型発振器５の
安定周波数をLOとすると、 O／P1＝LO×１／P2×１／P3 ……(1) が成り立つ。ここで、LOを求める式に直すと、 LO＝O×P2／P1×P3 ……(2)O ×P2／P1は安定周波数LOが飛び飛びの値をとる場 合のその周波数差に相当するが、この周波数差を
Sで表わすと LO＝S×P3 ……(3) となる。Sを小さくするとP3が大きくなるが、P3
を大きくするこは可変分周器７の構成が複雑にな
ると共に、可変分周器７の初段が扱う周波数が高
くなることを意味し、その実現にはコスト的、技
術的に不利な面がでてくる。 In the PLL circuit shown in Fig. 1, 1 is a reference frequency oscillator, 2 is a first frequency divider that divides the output of oscillator 1 to 1/P 1 , 3 is a phase comparator, 4 is a low-pass filter, and 5
is a tuner voltage controlled oscillator; 6 is a second frequency divider that divides the oscillation output of the voltage controlled oscillator 5 into 1/ P2 ; and 7 is the second frequency divider according to the frequency division control signal S1 . This is a variable frequency divider that divides the output of the converter 6. this
The PLL circuit has a comparison signal input to the phase comparator 3,
That is, since the loop works so that the output of the first frequency divider 2 and the output of the variable frequency divider 7 have the same frequency, now,
Assuming that the frequency division ratio of the variable frequency divider 7 is P 3 , the oscillation frequency of the reference frequency oscillator 1 is O , and the stable frequency of the voltage controlled oscillator 5 is LO , then O /P 1 = LO × 1 / P 2 × 1 /P 3 ...(1) holds true. Here, converting to the formula for calculating LO , LO = O ×P 2 /P 1 ×P 3 ...(2) O ×P 2 /P 1 is the frequency difference when the stable frequency LO takes discrete values. , but this frequency difference is
When expressed as S , LO = S × P 3 ...(3). If S is made smaller, P 3 becomes larger, but P 3
Increasing the frequency divider 7 means that the configuration of the variable frequency divider 7 becomes complicated and the frequency that the first stage of the variable frequency divider 7 handles increases, and there are cost and technical disadvantages in realizing this. It comes out.

ところで、テレビ放送の受信では微調ステツプ
を考慮してもSは125KHz程度で十分であるのに
対し、FM放送の受信では放送の中心周波数間隔
の100KHz以下にする必要がある。従つて、テレ
ビ放送とFM放送の両者を受信できるようなシス
テムに使うPLL回路では、前記周波数差Sはテレ
ビ放送受信だけの場合のSより小さくしなければ
ならず、そのためP3の値が大きくなり回路技術
上、及びコスト的に不利な面がでてくる。 By the way, in the reception of television broadcasts, S of about 125 KHz is sufficient even if fine adjustment steps are taken into consideration, whereas in the reception of FM broadcasts, it is necessary to set the S to 100 KHz or less, which is the center frequency interval of the broadcasts. Therefore, in a PLL circuit used in a system that can receive both TV broadcasts and FM broadcasts, the frequency difference S must be smaller than S in the case of only receiving TV broadcasts, so the value of P 3 is large. This results in disadvantages in terms of circuit technology and cost.

本発明は上記P3の最大値はテレビ放送受信用
のみのPLL回路と同じようにしてもFM受信時の
Sは十分小さくできるようにしたPLL回路を提案
するものであり、以下図面に従つて説明する。 In the present invention, the maximum value of P 3 mentioned above is the same as in the PLL circuit only for TV broadcast reception.
S proposes a PLL circuit that can be made sufficiently small, and will be explained below with reference to the drawings.

第２図において、基準周波数発振器１、位相比
較器３、低域濾波器４、電圧制御型発振器５並び
に可変分周器７は第１図と何ら変わらないが、第
１分周器２′及び第２分周器６′は端子８，９から
与えられるデータ、即ちテレビ放送受信時（以下
「テレビモード」という）の分周信号とFM放送
受信時（以下「FMモード」という）の分周信号
によつて２つの値をとりうるよう構成されてい
る。 In FIG. 2, the reference frequency oscillator 1, phase comparator 3, low-pass filter 4, voltage-controlled oscillator 5, and variable frequency divider 7 are the same as in FIG. 1, but the first frequency divider 2' and The second frequency divider 6' receives data from terminals 8 and 9, that is, the frequency division signal when receiving television broadcasting (hereinafter referred to as "TV mode") and the frequency division signal when receiving FM broadcasting (hereinafter referred to as "FM mode"). It is configured so that it can take two values depending on the signal.

今、第１分周器２′におけるテレビモードでの
分周比をP1（TV）、FMモードでの分周比をP1
（FM）とし、第２分周器６′におけるテレビモー
ドでの分周比をP2（TV）、FMモードでの分周比
をP2（FM）、更に周波数差Sについてテレビモー
ドのそれをS（TV）、FMモードでのそれをS
（FM）とすると、もともとOは(1)式よりO＝LO
×１／P3×P1／P2であつて、これに(3)式よりのS＝LO ／P3を代入すると、 O＝S×P1／P2 ……(4) となるから、テレビモードで必要な基準周波数O
（TV）は、 O（TV）＝S（TV）×P1（TV） ／P2（TV） ……(5) となり、同様にFMモードで必要な基準周波数O
（FM）は、 O（FM）＝S（FM）×P1（FM） ／P2（FM） ……(6) となる。そこでTVモードとFMモードでのOが
同一という条件を与えると、 S（TV）×P1（TV）／P2（TV） ＝S（FM）×P1（FM）／P2（FM） ……(7) が成立する。ここで、希望するS（TV）、S（FM）
の値としてS（TV）＝125KHz、S（FM）＝100KHz
を代入し、更に、P2（TV）＝128、P2（FM）＝64と
すると、P1（TV）、P1（FM）の組合せとして次の
組合せが生じる。 Now, the frequency division ratio in TV mode in the first frequency divider 2' is P 1 (TV), and the frequency division ratio in FM mode is P 1 (TV).
(FM), the frequency division ratio in TV mode in the second frequency divider 6' is P 2 (TV), the frequency division ratio in FM mode is P 2 (FM), and the frequency difference S is that in TV mode. S (TV), S it in FM mode
(FM), O is originally O = LO from equation (1)
×1/P 3 ×P 1 /P 2 , and by substituting S = LO /P 3 from equation (3) into this, O = S ×P 1 /P 2 ... (4) , the reference frequency required in TV mode O
(TV) is O (TV) = S (TV) × P 1 (TV) / P 2 (TV) ... (5) Similarly, the reference frequency O required in FM mode is
(FM) is O (FM) = S (FM) x P 1 (FM) / P 2 (FM) ... (6). Therefore, if we give the condition that O is the same in TV mode and FM mode, S (TV) × P 1 (TV) / P 2 (TV) = S (FM) × P 1 (FM) / P 2 (FM) ...(7) holds true. Here, select the desired S (TV), S (FM)
As the value of S (TV) = 125KHz, S (FM) = 100KHz
Further, if P 2 (TV) = 128 and P 2 (FM) = 64, the following combination of P 1 (TV) and P 1 (FM) is generated.

P1（TV） P1（FM） 3656 2285 3664 2290 3672 2295 3680 2300 今、この組合せのうちP1（TV）＝3664、P1
（FM）＝2290を選ぶと、(5)式から O（TV）＝O＝125×3664／128 ＝3578.125KHz となる。一方(3)式より P3＝LO／S ……(8) そこでTVモードのP3の最大値をP3（TV）、LO
の最大値をLO（TV）、FMモードのそれをP3
（FM）、LO（FM）とすると、 P3（FM）／P3（TV）＝LO（FM）／LO（TV）×S
（TV）／S（FM）……(9) なる関係式が得られる。ここでLO（FM）とLO
（TV）は放送規格より与えられるが、LO
（FM）／LO（TV）は1/9以下である。従つてS
（TV）／S（FM）が９以下であれば、 P3（FM）＜P3（TV） ……(10) が成立する。前記の例ではS（TV）／S（FM）＝
1.25であるから(10)式の関係が十分満足されてい
る。P 1 (TV) P 1 (FM) 3656 2285 3664 2290 3672 2295 3680 2300 Now, of this combination, P 1 (TV) = 3664, P 1
If (FM) = 2290 is selected, from equation (5), O (TV) = O = 125 x 3664/128 = 3578.125KHz. On the other hand, from equation (3), P 3 = LO / S ... (8) Therefore, the maximum value of P 3 in TV mode is P 3 (TV), LO
LO the maximum value of (TV), P 3 that of FM mode
(FM), LO (FM), P 3 (FM)/P 3 (TV) = LO (FM)/ LO (TV) × S
The following relational expression is obtained: (TV)/ S (FM)...(9). Here LO (FM) and LO
(TV) is given by the broadcasting standard, but LO
(FM)/ LO (TV) is less than 1/9. Therefore S
If (TV)/ S (FM) is 9 or less, P 3 (FM) < P 3 (TV) ...(10) holds true. In the above example, S (TV) / S (FM) =
1.25, so the relationship in equation (10) is fully satisfied.

このようにテレビモードとFMモードに対応し
て第１分周器２′の分周比をP1（TV）、P1（FM）、
第２分周器６′の分周比をP2（TV）、P2（FM）の
２段に切換えできるように構成し、且つテレビモ
ードでの安定周波数間隔をS（TV）、FMモード
でのそれをS（FM）とした場合、 S（TV）×P1（TV）P2（TV） ＝S（FM）×P1（FM）／P2（FM） P1（TV）＞P1（FM） P2（TV）＞P2（FM） の３式を同時に満足するように各値を選定すれ
ば、可変分周器７′の分周比P3の最大値は従来の
テレビだけの場合と同じで、安定周波数間の周波
数差Sは充分小さくできるのであり、従つて、斯
る本発明によればPLL回路をテレビ放送とFM放
送のいずれをも受信できるように構成する場合に
可変分周器の構成が複雑にならないという効果が
あり、動作上及びコスト上からみて非常に好まし
いといえる。 In this way, the frequency division ratio of the first frequency divider 2' is set to P 1 (TV), P 1 (FM),
The frequency division ratio of the second frequency divider 6' is configured to be switchable into two stages, P 2 (TV) and P 2 (FM), and the stable frequency interval in TV mode is changed to S (TV) and FM mode. If we take it as S (FM), then S (TV) × P 1 (TV) P 2 (TV) = S (FM) × P 1 (FM) / P 2 (FM) P 1 (TV)> If each value is selected so as to simultaneously satisfy the following three equations: P 1 (FM) P 2 (TV) > P 2 (FM), the maximum value of the frequency division ratio P 3 of the variable frequency divider 7' will be the same as the conventional one. As in the case of just a television, the frequency difference S between stable frequencies can be made sufficiently small.Therefore, according to the present invention, the PLL circuit is configured to be able to receive both television broadcasts and FM broadcasts. In this case, the structure of the variable frequency divider does not become complicated, which is very preferable from the viewpoint of operation and cost.

尚、第２図において、電圧制御型発振器５は単
独で示してあるが、この発振器は局部発振周波数
を与えるものとしてチユーナの一部をなすもので
あることはいうまでもない。ただし、そのチユー
ナはFM放送とテレビ放送の双方を受信できるチ
ユーナであつてもよく、FM放送用チユーナとテ
レビ用チユーナとして個別になつているものであ
つてもよい。前記の場合には、低域濾波器４から
の信号を１つの電圧制御型発振器に供給するだけ
でよいが、後者の場合には２つの電圧制御型発振
器に与えうるように接続し、場合によつてテレビ
放送受信時とFM放送受信時とで切り換える必要
がある。また第２図において、PLL回路と共働
する選局手段が示されていないが、この選局手段
は前記可変分周器７にS1で示す如く選局データに
従つた分周信号を与えると共に前記電圧制御型発
振器５を有するチユーナの電源等をも制御する
が、第２図のPLL回路をFM放送とテレビ放送を
選択的に受信できるような放送受信機に使用する
場合には、前記選局手段は第１分周器２′と第２
分周器６′に対しても分周信号を与える〔端子８，
９を通して〕ように構成されることはいうまでも
ない。第２図のPLL回路はそのような放送受信
機でなく、テレビ受像機とFM放送受信機のいず
れかに使用することもでき、その場合にも本発明
の効果を保有する。 Although the voltage controlled oscillator 5 is shown alone in FIG. 2, it goes without saying that this oscillator forms part of the tuner as it provides a local oscillation frequency. However, the tuner may be a tuner that can receive both FM broadcasts and television broadcasts, or it may be a tuner for FM broadcasts and a tuner for television separately. In the above case, the signal from the low-pass filter 4 only needs to be fed to one voltage-controlled oscillator, whereas in the latter case it is connected so that it can be fed to two voltage-controlled oscillators, and if Therefore, it is necessary to switch between receiving TV broadcasts and FM broadcasts. Further, in FIG. 2, although the tuning means that cooperates with the PLL circuit is not shown, this tuning means provides the variable frequency divider 7 with a frequency-divided signal according to the tuning data as shown by S1 . At the same time, it also controls the power supply of the tuner having the voltage controlled oscillator 5, but when the PLL circuit shown in FIG. 2 is used in a broadcast receiver that can selectively receive FM broadcasts and TV broadcasts, the above The channel selection means includes a first frequency divider 2' and a second frequency divider 2'.
A frequency division signal is also given to the frequency divider 6' [terminals 8,
Needless to say, it is constructed as follows. The PLL circuit shown in FIG. 2 can be used not only in such a broadcast receiver but also in either a television receiver or an FM broadcast receiver, and the effects of the present invention are retained in such cases as well.

以上の通り本発明のPLL回路はテレビ放送受
信用及びFM放送受信用として極めて有効であ
る。 As described above, the PLL circuit of the present invention is extremely effective for receiving television broadcasts and FM broadcasts.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は一般的なPLL回路のブロツク図であ
る。第２図は本発明に関するPLL回路のブロツ
ク図である。 １……基準周波数発振器、２′……第１分周器、
３……位相比較器、４……低域濾波器、５……電
圧制御型発振器、６′……第２分周器、７……可
変分周器。 FIG. 1 is a block diagram of a general PLL circuit. FIG. 2 is a block diagram of a PLL circuit according to the present invention. 1... Reference frequency oscillator, 2'... First frequency divider,
3... Phase comparator, 4... Low pass filter, 5... Voltage controlled oscillator, 6'... Second frequency divider, 7... Variable frequency divider.

Claims (1)

【特許請求の範囲】 １ 基準周波数発振器と、その出力を分周する第
１分周器と、電圧制御型発振器と、前記電圧制御
型発振器の出力を分周する第２分周器と、前記第
２分周器の出力を分周信号によつて分周する可変
分周器と、前記可変分周器の出力と第１分周器の
出力を位相比較する位相比較器と、その位相比較
器の出力の低周波成分を濾波して電圧制御型発振
器の制御信号として供給する低域濾波器とで構成
されるPLL回路において、前記第１分周器と第
２分周器の分周比をテレビ放送受信時とFM放送
受信時とで異なる値に設定できるようにすると共
に、第１分周器の分周比をテレビ放送受信の場合
P1（TV）、FM放送受信の場合P1（FM）とし、第
２分周器の分周比をテレビ放送受信の場合P2
（TV）、FM放送受信の場合P2（FM）とし、テレ
ビ放送受信の場合の安定周波数間隔をS（TV）
〔S（TV）＝O×P2（TV）／P1（TV）、ただしOは
基準周波数〕、FM放送受信の場合の安定周波数
間隔を S（FM）〔S（FM）＝O×P2（FM）／P1（FM）〕
としたとき、 S（TV）×P1（TV）／P2（TV） ＝S（FM）×P1（FM）／P2（FM） P1（TV）＞P1（FM） P2（TV）＞P2（FM） を同時に満足するようにしたことを特徴とする
PLL回路。[Scope of Claims] 1. A reference frequency oscillator, a first frequency divider that divides the output thereof, a voltage controlled oscillator, a second frequency divider that divides the output of the voltage controlled oscillator, and the a variable frequency divider that divides the output of the second frequency divider by a frequency division signal; a phase comparator that compares the phases of the output of the variable frequency divider and the output of the first frequency divider; and a phase comparator that compares the phases of the output of the variable frequency divider and the output of the first frequency divider. In a PLL circuit configured with a low-pass filter that filters a low frequency component of the output of a voltage-controlled oscillator and supplies it as a control signal to a voltage-controlled oscillator, the frequency division ratio of the first frequency divider and the second frequency divider is can be set to different values when receiving TV broadcasts and when receiving FM broadcasts, and the division ratio of the first frequency divider can be set to different values when receiving TV broadcasts.
P 1 (TV), for FM broadcast reception, P 1 (FM), and the frequency division ratio of the second frequency divider is P 2 for TV broadcast reception.
(TV), for FM broadcast reception, P 2 (FM), and for TV broadcast reception, the stable frequency interval is S (TV).
[ S (TV) = O ×P 2 (TV) / P 1 (TV), where O is the reference frequency], the stable frequency interval for FM broadcast reception is S (FM) [ S (FM) = O ×P 2 (FM)/P 1 (FM)]
When, S (TV) × P 1 (TV) / P 2 (TV) = S (FM) × P 1 (FM) / P 2 (FM) P 1 (TV) > P 1 (FM) P 2 (TV) > P 2 (FM) is simultaneously satisfied.
PLL circuit.
JP3309179A 1979-03-19 1979-03-19 Pll circuit Granted JPS55124332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3309179A JPS55124332A (en) 1979-03-19 1979-03-19 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3309179A JPS55124332A (en) 1979-03-19 1979-03-19 Pll circuit

Publications (2)

Publication Number Publication Date
JPS55124332A JPS55124332A (en) 1980-09-25
JPS6363136B2 true JPS6363136B2 (en) 1988-12-06

Family

ID=12376993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3309179A Granted JPS55124332A (en) 1979-03-19 1979-03-19 Pll circuit

Country Status (1)

Country Link
JP (1) JPS55124332A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350121A (en) * 1986-08-19 1988-03-03 Mitsubishi Electric Corp Frequency adjusting circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53138621A (en) * 1977-05-11 1978-12-04 Hitachi Ltd Radio receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119311U (en) * 1976-03-05 1977-09-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53138621A (en) * 1977-05-11 1978-12-04 Hitachi Ltd Radio receiver

Also Published As

Publication number Publication date
JPS55124332A (en) 1980-09-25

Similar Documents

Publication Publication Date Title
EP0432052B1 (en) RF modulator
JPS63242030A (en) Broad band frequency synthesizer receiver
US4963838A (en) Frequency synthesizer
US5220684A (en) Channel selecting circuit
US5995169A (en) SIF signal processing circuit
JPS61251313A (en) Electronic tuning type fm receiver
JPS588617B2 (en) Jiyushinki
US4095190A (en) Tuning system
JPS6363136B2 (en)
JPH021973Y2 (en)
JPS5883446A (en) Receiver
JP3053838B2 (en) Video intermediate frequency circuit
JPS60223335A (en) Turner of am/fm receiver
JP2811841B2 (en) Modulator using PLL
JPH0314812Y2 (en)
JPS5881341A (en) Receiver
JPS6223146Y2 (en)
JPS6019857B2 (en) Receiving machine
JPS6035302Y2 (en) automatic tuning circuit
JPS6349412B2 (en)
JPS58177036A (en) Am radio receiver
JPS6136427B2 (en)
JPH03117222A (en) Receiver of voltage synthesizer system
JPS6136426B2 (en)
JPS60245319A (en) Fm receiving device of synthesizer system