JPS6349412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital tuning control device used in a PLL (Phase Locked Loop) frequency synthesizer tuner.

BACKGROUND ART Conventionally, as a digital tuning control device used in a PLL frequency synthesizer tuner, for example, the product name "HD44015" sold by Hitachi, Ltd. is known.

In order to make this digital tuning control device applicable in each region of Japan, the United States, and Europe,
The reference frequency signal to the phase comparator forming the PLL loop is selectively switched. Therefore, the time base signal for the clock function is formed by independent multi-stage frequency dividing circuits.

An object of the present invention is to provide a digital tuning control device with a simplified circuit.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to an AM/FM radius receiver.

What is indicated by symbol 1 is the AM front end, which is composed of a varactor (variable capacitance element) tuned high frequency amplification and frequency mixing circuit.

The output signal of this AM front end 1 is AM
It is transmitted to the intermediate frequency and detection circuit 2, where the AM
An audio output signal is formed.

On the other hand, what is indicated by symbol 3 is the FM front end, which is composed of a varactor-tuned FM high-frequency amplification circuit and a frequency mixing circuit. this
The output signal of the FM front end is transmitted to the FM intermediate frequency and detection circuit 5 via an FM intermediate frequency filter 4 made of ceramic or the like, for example.
Here an FM audio signal is formed. Note that in the case of an FM stereo receiver, an FM stereo demodulation circuit (not shown) is provided at the next stage, and a stereo audio signal is formed by this for FM stereo broadcasting.

Furthermore, an audio power amplification stage and an AM/FM switching circuit are also provided, but these are omitted in the figure.

A varactor control voltage formed by a low-pass filter 9 of a PLL circuit is applied to the varactors of the AM front end 1 and FM front end 3.

In addition, the frequency mixing circuits of AM front end 1 and FM front end 3 each have a PLL.
A frequency signal formed by a VCO (voltage controlled oscillator circuit) in the circuit is applied as a local oscillation frequency.

The symbol 10 indicates a semiconductor integrated circuit (LSI) for PLL control, such as a CMOS
(complementary metal-insulator-semiconductor) circuit, and forms part of a PLL loop that constitutes a frequency synthesizer and its digital control section.

In the LSI 10 shown in the figure, the numbers surrounded by circles indicate its external terminals, which are connected to an external circuit network through these terminals.

Symbol 11 indicates a switching circuit that switches between the oscillation output of the AM VCO 8 applied to the No. 3 terminal and the oscillation output of the FM VCO 6 applied to the No. 4 terminal. to communicate. Note that the oscillation frequency of the FM VCO 6 is high and would exceed the response limit of the program counter 12 if left as is, so the frequency is lowered by a prescaler (frequency divider) 7.

The symbol 13 indicates a latch circuit which holds the frequency division ratio N of the program counter 12, decodes the N value, and outputs the above switching circuit 1.
1 switching signal is formed.

The program counter 12 has the N value of the latch circuit 13 preset, and by repeatedly counting N input pulses, forms a 1/N frequency-divided pulse at its output, and sets one input terminal of the phase comparator 14. tell to.

A reference frequency signal is applied to the other input terminal of the phase comparator 14. Then, this phase comparison output is transmitted to the low pass filter 9 via the No. 1 terminal, and the above-mentioned varactor control voltage and VCO control voltage are formed. Therefore, when the PLL loop is locked, the oscillation frequency of the AM VCO 8 is set to a frequency N times that of this reference frequency signal, and the oscillation frequency of the FM VCO 8 is set to
In VCO6, the frequency is further divided by prescaler 7, so if the frequency division ratio is N', then N×
The oscillation frequency is set to the reference frequency N' times higher.

This reference frequency is formed as follows. Symbol 15 is a reference frequency oscillation circuit using an externally attached crystal resonator, and here, for example,
A stabilized oscillation frequency of 11.52MHz is created.

This oscillation output is generated by the fixed frequency dividing circuit 16.
For example, the frequency is divided by 1/2 ⁷ , and at its output,
Converted to a 90KHz frequency signal.

What is indicated by symbol 17 is one that receives the output signal of the fixed frequency dividing circuit 16 and forms a plurality of types of the reference frequency signals, for example, 1/
This is a variable frequency divider circuit with frequency division ratios of 9, 1/10, 1/18, and 1/20. This allows 10KHz, 9KHz,
Selectively forms four types of reference frequency signals: 5KHz and 4.5KHz. The switching circuit 19 forms the switching control signal, and receives, for example, a 2-bit signal from the controller 20, decodes it, and forms the switching control signal.

Reference numeral 18 indicates an inverse variable frequency divider circuit which receives the output signal of the variable frequency divider circuit 17 and forms a time base signal whose output frequency is constant. Therefore, the frequency division ratio is set in the same manner as the variable frequency division circuit 17, but a frequency division ratio that has an inverse conversion relationship with the frequency division ratio selected by the variable frequency division circuit 17 is selected. It is something.

These variable frequency divider circuit 17 and inverse variable frequency divider circuit 1
The specific configuration of 8 will be explained next.

Note that the controller 20 is composed of, for example, a microcomputer, a keyboard, a display device, etc., and is used to form the N value to the latch circuit 13 and to send a switching signal to the switching circuit 19. to form. Further, upon receiving the PLL lock signal outputted from the phase comparator 14 through the second terminal, a sweep operation during automatic selection is performed. It also receives a time base signal from terminal No. 7 and performs clock operations, etc.

FIG. 2 shows a block diagram showing one embodiment of the variable frequency divider circuit 17 and the inverse variable frequency divider circuit 18.

The 90KHz frequency signal formed by the fixed frequency divider circuit 16 is transmitted to the variable frequency divider circuit 1 of 1/9 or 1/10.
7a. This selectively creates a divided output of 10 or 9KHz.

The frequency-divided output of the variable frequency divider circuit 17a is inputted to a 1/2 fixed frequency divider circuit 17b, and a frequency-divided output of 5 or 4 KHz is formed at its output. The frequency-divided output of the fixed frequency divider circuit 17b and the frequency-divided output of the variable frequency divider circuit 17a are input to a multiplexer 17c, where they are selected and one of them is used as a reference frequency signal to the phase comparator 14. It is conveyed as.

switching the frequency division ratio of the variable frequency divider circuit 17a;
The selection of the multiplexer 17c is made by the switching circuit 1.
This is done by means of a control signal formed at 9.

The variable frequency divider circuit 17a and multiplexer 1
In combination with 7c, in this example, 10,
Four types of reference frequency signals of 9, 5, or 4.5 KHz can be alternatively formed.

Further, in this embodiment, the output signal of the variable frequency dividing circuit 17a is used to form the time base signal. That is, in order to form a mime base signal of a constant frequency, a variable frequency dividing circuit 18a similar to that described above is used. However, although this variable frequency dividing circuit 18a has a frequency dividing ratio of 1/9 or 1/10 as described above, the frequency dividing ratio is selected to be the opposite ratio to that of the variable frequency dividing circuit 17a.

For example, when the frequency division ratio of the variable frequency dividing circuit 17a is set to 1/9, this variable frequency dividing circuit 1
The frequency division ratio of 8a is set to 1/10. On the other hand, when the frequency division ratio of the variable frequency divider circuit 17a is set to 1/10, the frequency division ratio of the variable frequency divider circuit 18a is set to 1/9. Thereby, the inversely variable frequency divided output from the variable frequency dividing circuit 18a can always form a constant frequency (1 KHz) signal. In this embodiment, a fixed frequency dividing circuit 18b is provided to set the frequency of the time base signal to 50 KHz.

FIG. 3 shows a block diagram of a modification of the circuit of the embodiment shown in FIG. 2. In FIG.

In this embodiment, although not particularly limited, if the frequency from the fixed frequency divider circuit 16 is 450KHz,
The reference frequency (450 KHz) is divided into 1/9 or 1/10 by a variable frequency dividing circuit 17a similar to the above. Then, a 1/5 fixed frequency dividing circuit 17b'' forms a signal of 10 or 9 KHz.

Also, 10 from the 1/5 fixed frequency divider circuit 17b''
Or 9KHz frequency division output and the above variable frequency division circuit 17a
The 50 or 45KHz frequency divided output from the 1/2 fixed frequency divider circuit 17 with a selection function at its input
The frequency is selectively divided by 1/2 by b'. Then, one of the 1/5 fixed frequency divided output and the 1/2 fixed frequency divided output is transmitted to the phase comparator 14 as a reference frequency signal by a multiplexer 17c similar to the above. The above 1/2 frequency divided output is 5 or 4.5KHz, 25 or 20KHz, so the reference frequency signal formed through the multiplexer 17c is 25, 22.5, 10.9, 5 or 4.5KHz.
Become a type.

In addition, in order to form the time base signal, in this embodiment, the above 1/5 fixed frequency division output (10 or
9KHz) is used.

That is, the 1/5 fixed frequency division output is inversely converted by the same variable frequency division circuit 18a as described above, and a constant frequency signal of 1 KHz is formed as the output.

Although not particularly limited, a 1/10 fixed frequency dividing circuit 18b' is further provided in order to set the frequency of the time base signal to 50 Hz as described above.

According to this embodiment described above, in forming the time base signal, the divided output used for forming the reference frequency signal is utilized. Therefore, the number of frequency dividing stages of the frequency dividing circuit that forms the time base signal can be reduced, and the circuit can be simplified.

Furthermore, when configured with a CMOS circuit, its power consumption can be reduced. That is,
As is well known, a CMOS circuit consumes current when changing its output, so the current consumption is large in the frequency dividing stage where the input frequency is high. In this example, the frequency in the part reduced by sharing the frequency dividing stage is as high as 90KHz to 450KHz.
The effect of reducing power consumption is significant.

The invention is not limited to the above embodiments.

Variable frequency divider circuit 1 for forming a reference frequency signal
7 and the inverse variable frequency divider circuit 18 for forming the time base signal can be modified in various ways depending on the required frequency.

In addition to the radio receiving device, the present invention also provides:
It can be similarly utilized in a digital tuning control circuit for television reception.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an AM/FM radio receiving device.
FIGS. 2 and 3 are block diagrams showing an embodiment of the main part of the present invention, respectively. 1...AM front end, 2...AM intermediate frequency and detection, 3...FM front end, 4...
IF filter, 5...FM intermediate frequency and detection, 6...
...VCO for FM, 7...Prescaler, 8...AM
VCO, 9...Low pass filter, 10...
LSI, 11...Switching circuit, 12...Program counter, 13...Latch circuit, 14...Phase comparator, 15...Oscillation circuit, 16...Fixed frequency divider circuit,
17... variable frequency divider circuit, 18... inverse variable frequency divider circuit, 19... switching circuit, 20... controller.

Claims (1)

[Claims] 1. A reference frequency oscillator circuit, receiving this oscillation frequency or its fixed frequency divided output, and selecting a plurality of reference frequency signals for the phase comparator in the PLL frequency synthesizer tuner according to the frequency division ratio switching signal. and a first variable frequency divider circuit that receives the output signal of the first variable frequency divider circuit and changes the frequency division ratio of the first variable frequency divider circuit according to the frequency division ratio switching signal. and a second variable frequency divider circuit that forms a time base signal of a constant frequency using a frequency division ratio of inverse conversion. 2. The phase comparator, program counter, and circuit that selectively forms the time base signal and the plurality of reference frequency signals forming the PLL loop in the PLL frequency synthesizer tuner are configured in one semiconductor integrated circuit device. A digital tuning control device according to claim 1, characterized in that the digital tuning control device is a digital tuning control device according to claim 1.