JPS5919438A - Digital tuning controller - Google Patents

Abstract

PURPOSE:To obtain a time base signal having a prescribed frequency out of the 2nd frequency division circuit, by providing the 2nd frequency division circuit operated with an inverted frequency dividing ratio to the frequency dividing ratio, in addition to a variable frequency division circuit inputting selectively plural reference signals to a phase comparator. CONSTITUTION:An output(90kHz) of a fixed frequency division circuit 16 is frequency-divided by the 1st variable frequency division circuit 17a to 1/9 or 1/10, furthermore, frequency-divided to 1/2 at a fixed frequency divider 17b. An output of a multiplexer 17c is applied to the phase comparator as a reference frequency signal. The switching of the frequency dividing ratio of the frequency division circuit 17a and the selection of the multiplexer 17c are performed with a control signal from a switching circuit 19. The output of the frequency division circuit 17a is frequency-divided at the 2nd variable frequency division circuit 18a. The frequency dividing ratio of the frequency division circuit 18a is set inversely to that of the frequency division circuit 17a.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a digital tuning control device used in a PLL (phase locked loop) frequency synthesizer tuner.

Conventionally, as a digital tuning control device used in a PLL frequency synthesizer tuner, for example, the component name [HD44015J] sold by Hitachi, Ltd. is known.

In this digital tuning control device, in order to be applicable in each region of Japan, the United States, and Europe, a reference frequency signal is sent to the phase comparator that constitutes the PLL loop. I am trying to switch it selectively. Therefore, the time base signal for the clock function is formed by an independent multi-stage frequency dividing circuit.

An object of the present invention is to provide a digital tuning control device whose circuit is completely simplified.

Other objects of the invention will become apparent from the following description and drawings.

Is this invention below? This will be explained in detail along with examples.

FIG. 1 shows a block diagram of an embodiment of the present invention applied to an iAM/FM radio receiving apparatus.

What is indicated by symbol 1 is the AM front end, which is composed of a varactor (variable capacitor) tuned high wave amplification and frequency mixing circuit.

The output signal of this AM front end 1 is transmitted to an AM intermediate frequency and detection circuit 2, where an AM audio output signal is formed.

On the other hand, what is indicated by symbol 3 is the FM front end, which is composed of a varactor-tuned FM high-frequency amplification circuit and a frequency mixing circuit. The output signal of this FM front end is transmitted to an FM intermediate frequency and detection circuit 5 via an FM intermediate frequency filter 4 made of ceramic or the like.
The transmission formula n1 is formed here, and the FM voice key signal is formed. In the case of an FM stereo receiver, an FM stereo signal path (not shown) is provided at the next stage, and 7M
For stereo broadcasting, a K-th stereo audio signal is generated.

Furthermore, an audio power amplification stage and an AM/FM switching circuit are also provided, but these are omitted in the 1ir1 diagram.

A varactor control voltage formed by a low-pass filter 9 of a PLL circuit is applied to the varactors of the AM front end 1 and FM front end 3.

'E*, AM front end 1 and FM front end 3 frequency mixing circuits are each formed by a VCO (voltage controlled oscillator circuit) in a jL P L L circuit, and a nine frequency code is applied as a local oscillation frequency. Ru.

The symbol 10 is a semiconductor integrated circuit (LSI) for PLL control, such as a CMOS (complementary metal-insulator-semiconductor) circuit. Frequency synthesizer? A part of the PLL loop and its digital control section are formed.

In L8 construction 10 in the same figure, the circled numbers 1f indicate the external terminals, and these terminals are all connected to the external circuit network! -i1.

Symbol 11 indicates a switching circuit that switches between the oscillation output of the AM vaoB applied to the 3rd terminal and the FM VOO6 oscillation output applied to the 4th terminal.
It is transmitted to the program counter 12. In addition, v0 for FM
The frequency of 06 is high, and the frequency up to 1 exceeds the response limit of the program counter 12, so the greasy scaler (frequency divider) 7 lowers the frequency V.

A latch circuit is indicated by 13, which holds the entire frequency division ratio N of the program counter 12, and
That Nll1 yen? Is the switching signal for W611 the upper and lower switching times? Form.

When the N11 section of the latch circuit 13 is preset and the program counter 12 repeatedly receives N input pulses, the program counter 12 generates all 1/N frequency divided pulses at its output and inputs one of the inputs to the phase comparator 14. Tell it to the terminal.

A reference frequency signal is applied to the other input terminal of the phase comparator 14. Then, this phase comparison output is transmitted to the low-pass filter 9 through the valve No. 1 terminal to form the above varactor control voltage and the 00 control voltage. Therefore, P
When the LL loop is locked, the AM vcoB firing frequency is set to a frequency N times this reference frequency signal, and in the FM v006, the frequency is further divided by the grease scaler 7, so the frequency division ratio is If N', then the emission frequency is set to the number of reference stations e which is NXN' times.

This reference frequency is formed as follows. Reference numeral 15 indicates a reference frequency oscillation circuit that does not require an externally attached crystal oscillator, in which a stabilized oscillation frequency of, for example, 11.52 MH2 is generated.

This oscillation output is processed by the fixed frequency dividing circuit 16, for example.
1/2” and at its output, 9 Q
It is converted into a KHz frequency signal.

What is indicated by symbol 17 is the output signal of the fixed frequency divider circuit 16? Accordingly, the above reference frequency of several types of σ is 100? For example, 1/9°1/10.1/1
This is a variable frequency divider circuit with a frequency division ratio of 8.1/20. Eri, l OKH2, 9KHz.

Four types of reference frequency signals of 5KHz and 4.5KH2 are selectively formed. The switching circuit 1911''t, which forms the switching control signal, receives, for example, a 2-bit signal from the controller 20, decodes all of this, and forms all the upper switching control signals.

What is indicated by symbol 18 is an inverse variable frequency divider circuit,
In response to the output signal of the variable frequency dividing circuit 17, a time base signal tone whose output frequency is constant is formed. Therefore, the frequency division ratio is set in the same way as the variable frequency division circuit 17, but a frequency division ratio that has an inverse conversion relationship with the frequency division ratio selected by the variable frequency division circuit 17 is selected. It will be revealed.

These variable frequency divider circuits 17. The specific configuration of the inverse variable frequency divider circuit 18 will be explained next.

In addition, what is indicated by the symbol 20 is the controller 2, which is composed of, for example, a microcomputer, a keyboard, a display device, etc.
K shadow formation, switching to the switching circuit 19 (forming 1! It performs all the sweep operations. It receives the time pace signal from terminal 7 and performs upward clock operations.

FIG. 2 is a block diagram showing an embodiment of the variable frequency divider circuit 17 and the inverse variable frequency divider circuit 18.

The frequency signal of 7t 90 KH2 formed by the fixed frequency dividing circuit 16 is transmitted to the variable frequency dividing circuit 17 of 1/9 or 1/10.
aK is input. This selectively creates a 10 or 9 KHz branch output.

The frequency-divided output of the variable frequency divider circuit 17a is inputted to a 1/2 fixed frequency divider circuit 17b, and a 5 or 4KH2O frequency-divided output is formed at its output. The division output of the fixed frequency divider circuit 17b and the division output of the variable frequency divider circuit 17a are input to a multiplexer 17c, and one of them is selected by the multiplexer 17c.
It is transmitted as a reference frequency signal to the

The switching of the frequency division ratio of the variable frequency dividing circuit 17a and the selection of the multiplexer 17o is performed by a switching circuit 19 and a control circuit 19.

In this embodiment, from the combination K of the variable frequency divider circuit 17a and the multiplexer 17c, the frequency is 10.9°5, or 4.
．． Four types of reference frequency signals of 5 KHz can be alternatively generated.

Further, in this embodiment, the output signal of the variable frequency dividing circuit 17a is used to form a time base signal tone. That is, in order to form a mime base signal having a constant frequency, a variable frequency dividing circuit tea similar to that described above is used. However, the division ratio of the variable frequency divider circuit 18aid must be 1/9 or 1/10 as described above, but the division ratio is selected to be opposite to that of the variable frequency divider circuit 17a.

For example, if the frequency division ratio of the variable frequency divider circuit 17a is set to t1/9, the frequency division ratio of the variable frequency divider circuit 18a is set to 1/9.
/10 can be set. On the other hand, when the frequency division ratio of the variable frequency divider circuit 17a is set to 'kl/10, the frequency division ratio of the variable frequency divider circuit 18a is set to μm/9. In addition, the inverse variable frequency division output from the variable frequency division circuit 18aK can always form a constant frequency (IKH2) signal.
Wow. In this example, 50
A fixed frequency dividing circuit tab is provided to set the frequency to KHz.

FIG. 3 shows a block diagram of a modification of the embodiment circuit shown in FIG. 2 above.

In this embodiment, although not particularly limited, when the frequency from the fixed frequency divider circuit 16 is 450 KH2, the variable frequency divider circuit 17aK similar to the above
KHz) Divide into k1/9 or 1/10. and,
1/5 fixed frequency divider circuit 17b", 10 or 9KH
2 signal r is formed.

Furthermore, the 10 or 9KH2O frequency divided output from the 115 fixed frequency divider circuit 17b'' and the 5KH2O frequency divided output from the variable frequency divider circuit 17a
The frequency-divided output of 0 or 45 KHz is selectively divided into 1/2 by a 1/2 fixed frequency divider circuit 17b' whose input is provided with a selection function. The upper Δ115 fixed frequency division output and the 1/2 fixed frequency division output are transmitted as a reference frequency signal to any of the frequency division output phase ratio machines 14 by a multiplexer 170 similar to the above. Since the 1/2 frequency divided output is 5 or H4, 5KH2, 25 or 20KH2, the reference frequency signals formed through the multiplexer 17c'i are 25.22.5, 10.9.5.
Or 6 types of 4.5KH2.

In addition, in order to completely form the time base signal, in this embodiment, the above-mentioned 115 fixed frequency division output (10 or -9KH
z) is used.

In other words, the above device 15 fixed frequency division output circuit is inversely converted by the variable division channel 18a K, and the output is IK.
A constant frequency M signal of H, is entirely formed.

Although not particularly limited, in order to set the frequency of the time pace signal to 50 Hz as described above, a 1/10 fixed frequency dividing circuit 18b' is further provided.

According to this embodiment described above, when forming all the time base signals, the branch output tU is used for the purpose of forming all the reference frequency signals. Therefore, the number of frequency dividing stages of the frequency dividing circuit that forms the time pace signal can be reduced, so that the circuit can be simplified.

Reed. If the circuit is configured with 0M08 circuits, its power consumption can be reduced. That is, as is well known, the 0M08 circuit consumes current when changing its output sound, so the current consumption 1 in the frequency division stage where the human input frequency is high is large. In this embodiment, the frequency in the portion reduced by sharing the frequency dividing stage is 90KH2 to 450KH2.
Since it has a high KH2, the effect of reducing power consumption is significant.

This invention is not limited to the previous ae embodiment.

The variable frequency divider circuit 17 for forming all reference frequency signals and the inverse variable frequency divider circuit 18 for forming all time base signals can be modified in various ways depending on the required frequency. Ruru.

Further, the present invention can be similarly applied to a digital leg opening control circuit for television reception in addition to the radio receiving device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment when this invention is applied to an iAM/FM radio receiving device, and FIGS.
The figures each show an example of this invention. FIG. 1...AM front end, 2...AM intermediate frequency and detection, 3...FM front end, 4...IF filter, 5...FM intermediate frequency and detection, 6...FM
V○0, 7...Prescaler, 8...VO for AM
O19...Low pass filter, 10...LSI, 1
1...Switching circuit, 12...Program counter, 1
3... Latch circuit, 14... Phase comparator, 15...
- Oscillation circuit, 16... Fixed frequency divider circuit, 17... Variable frequency divider circuit, 18... Inverse variable frequency divider circuit, 19... Switching circuit, 20... Controller.

Claims (1)

[Claims] 1. In response to the reference frequency oscillation circuit and this rooting frequency or its fixed frequency division amount, according to the frequency division ratio switching signal, 1'LL
A first variable frequency divider circuit selectively inputs a plurality of reference frequency signals to a phase comparator in a frequency synthesizer tuner, and an output signal of this first variable frequency divider circuit. and a second variable frequency divider circuit that, in accordance with the frequency division ratio switching signal, generates a time pace signal of a constant frequency using a frequency division ratio that is inversely converted to the frequency division ratio of the first variable frequency divider circuit. and? All features include a digital tuning control device. 2. P in the above PLL frequency synthesizer tuner
LL loop? comprising a phase comparator, a program counter, the time pace signal and the plurality of reference frequencies 1;
The circuit that selectively forms the glyph is located at the