JPS62107529A - Electronic tuner incorporating fixed frequency divider having band changeover function - Google Patents

Electronic tuner incorporating fixed frequency divider having band changeover function

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Publication number
JPS62107529A
JPS62107529A JP24703185A JP24703185A JPS62107529A JP S62107529 A JPS62107529 A JP S62107529A JP 24703185 A JP24703185 A JP 24703185A JP 24703185 A JP24703185 A JP 24703185A JP S62107529 A JPS62107529 A JP S62107529A
Authority
JP
Japan
Prior art keywords
signal
frequency
voltage
band
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24703185A
Other languages
Japanese (ja)
Inventor
Takeshi Saito
武志 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24703185A priority Critical patent/JPS62107529A/en
Publication of JPS62107529A publication Critical patent/JPS62107529A/en
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To simplify the connection between an electronic tuner and an external circuit by incorporating a circuit which counts a signal frequency as soon as a frequency division signal of a fixed frequency divider is outputted and outputs a reception frequency band switching signal in response to the said count into the electronic tuner. CONSTITUTION:The reception is enabled by biasing band pass filters 2, 4 and a VCO6 to a prescribed tuning voltage with respect to a desired reception RF signal fed to an RF signal input terminal 1, the RF signal via the band pass filter 2, an amplifier 3 and the band pass filter 4 is frequency-converted by using a signal of the VCO6 into an IF signal, which is outputted at an output terminal 8 via an IF amplifier 7. A voltage fed to a tuning voltage terminal 11 controls the VCO6 that its output is frequency-divided by a fixed frequency divider 9 and then inputted to a PLL circuit. In this case, the fixed frequency divider 9 counts a signal being the frequency division of the oscillated signal of the VCO6 and outputs a reception frequency band switching voltage. The voltage is fed to the band pass filters 2, 4 and the tuning circuit of the VCO to select the reception band.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はテレビジョン信号などの高周波信号を受信する
電子チューナに係り、特に、PLL回路による選局に好
適な電子チューナに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electronic tuner that receives high frequency signals such as television signals, and particularly to an electronic tuner suitable for channel selection using a PLL circuit.

〔発明の背景〕[Background of the invention]

従来のPLL回路による選局を行なう複数の受信帯域に
よりテレビジョン信号などの高周波信号を受信する電子
チューナは特開昭56−11447号記載の様に受信周
波数帯切り換え信号は制御部からの信号により電圧発生
回路を駆動することにより得ており、したがって受信周
波数帯切り換え用に、電圧制御発振器の周波数設定用の
信号線路の他に余分に1系統以上の信号線路が必要とな
る欠点がある。また、特開昭57−89153号では電
圧制御発振器の周波数設定用の同調電圧を利用して、受
信周波数帯毎に設定された基8%圧と比較して受信周波
数帯切り換え信号を出力するもので信号線路の数は少な
く出来るが電圧による切り換え電圧発生をさせるために
、受信チャネルと同期をとるのが困難であり、特に、発
振周波数の同調電圧に対する感度が高い場合には正確な
帯域切り換えが困難となる欠点がある。
Conventional electronic tuners that receive high-frequency signals such as television signals through multiple reception bands perform channel selection using a PLL circuit, as described in Japanese Patent Application Laid-Open No. 56-11447, the reception frequency band switching signal is determined by a signal from a control unit. This is obtained by driving a voltage generating circuit, and therefore, there is a drawback that one or more signal lines are required in addition to the signal line for setting the frequency of the voltage controlled oscillator for switching the receiving frequency band. Furthermore, in Japanese Patent Application Laid-open No. 57-89153, a tuning voltage for frequency setting of a voltage controlled oscillator is used to compare the base 8% voltage set for each receiving frequency band and output a receiving frequency band switching signal. Although the number of signal lines can be reduced, it is difficult to synchronize with the receiving channel because the switching voltage is generated using a voltage. Especially when the sensitivity of the oscillation frequency to the tuning voltage is high, accurate band switching is difficult. There are drawbacks that make it difficult.

〔発明の目的〕[Purpose of the invention]

本発明の目的は複数の受信周波数帯域切り換え機能を有
する電子チューナの外部回路との信号線路の接続を少な
くして接続を容易にすると同時に受信周波数帯域の数の
異なる電子チューナ間の互換性を確保し、さらに受信周
波数帯に応じた切り換え何月を正確に発生させる電子チ
ューナを提供することにある。
The purpose of the present invention is to reduce the number of signal line connections between an electronic tuner having a plurality of reception frequency band switching functions and an external circuit, thereby facilitating the connection, and at the same time ensuring compatibility between electronic tuners having different numbers of reception frequency bands. Furthermore, it is an object of the present invention to provide an electronic tuner that accurately generates the switching frequency according to the receiving frequency band.

〔発明の概要〕[Summary of the invention]

電子チューナ部に内蔵された固定分周器の分周出力は比
較的周波数が低いためこの周波数を計数して計数値に応
じて受信周波数帯切り換え電圧を発生させることが比較
容易薯こ行なえることからこれらの切り換え電圧発生回
路をチューナあるいは固定分周器IC内に内蔵させる。
Since the divided output of the fixed frequency divider built into the electronic tuner section has a relatively low frequency, it is relatively easy to count this frequency and generate a reception frequency band switching voltage according to the counted value. Therefore, these switching voltage generation circuits are built into a tuner or a fixed frequency divider IC.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の詳細な説明する。第1図はシングルス−
パーヘテロダイン方式電子チューナに本発明を実施した
場合の回路ブロック図である。1は高周波信号(RF倍
信号入力端子。
The present invention will be explained in detail below. Figure 1 shows singles-
FIG. 2 is a circuit block diagram when the present invention is implemented in a perheterodyne electronic tuner. 1 is a high frequency signal (RF multiplied signal input terminal).

2は可変バンドパスフィルタ、3は増幅器、4は可変バ
ンドパスフィルタ、5はミクサ、6は電圧制御発振器(
VCO)、7はIF増幅器。
2 is a variable band pass filter, 3 is an amplifier, 4 is a variable band pass filter, 5 is a mixer, 6 is a voltage controlled oscillator (
VCO), 7 is an IF amplifier.

8はIF出力端子、9は固定分周器、10はAGC電圧
端子、11は同調電圧端子、12は分周出力端子である
。RF信号入力端子1に供給された希望受信RF信号に
対して、バンドパスフィルタ2および4.VCo6は所
定の同調電圧にバイアされることにより受信が可能とな
り、バンドパスフィルタ2.増幅器3.バンドパスフィ
ルタ4を介したRF倍信号VCo6の信号により周波数
変換されてIF信号となり、IF増幅器7を介して出力
端子8に出力される。同調電圧端子11に供給される電
圧はVCo6を固定分周器9で分周した後、PLL回路
に入力され、P LL回路より供給される電圧である。
8 is an IF output terminal, 9 is a fixed frequency divider, 10 is an AGC voltage terminal, 11 is a tuning voltage terminal, and 12 is a frequency division output terminal. For the desired received RF signal supplied to the RF signal input terminal 1, bandpass filters 2 and 4. The VCo 6 is biased to a predetermined tuning voltage to enable reception, and the bandpass filter 2. Amplifier 3. The signal is frequency-converted by the RF multiplied signal VCo6 through the bandpass filter 4 to become an IF signal, which is output to the output terminal 8 through the IF amplifier 7. The voltage supplied to the tuning voltage terminal 11 is a voltage that is input to the PLL circuit after frequency-dividing the VCo 6 by the fixed frequency divider 9, and is supplied from the PLL circuit.

この時、固定分周器9はVCo6の発振信号を分周した
信号・ 3 ・ を計数し、計数値に応じた受信周波数帯域切り換え電圧
を出力する様になっており、この電圧が、バンドパスフ
ィルタ2.4およびvCOの同調回路に供給され受信帯
域の選択を行なう。
At this time, the fixed frequency divider 9 counts the frequency-divided signal 3 of the oscillation signal of the VCo 6 and outputs a receiving frequency band switching voltage according to the counted value, and this voltage It is supplied to the filter 2.4 and the vCO tuning circuit to select the receiving band.

バンドパスフィルタ2.4およびVCo6の同調回路の
基本構成の一例を第2図に示す013および13′はそ
れぞれRF倍信号入力あるいは出力端子である014.
15.25.26.27は高周波バイパスコンデンサ、
16は第1のコイル、18は第2のコイル、 17Fi
、スイッチングダイオード。
An example of the basic configuration of the tuning circuit of the bandpass filter 2.4 and the VCo 6 is shown in FIG. 2. 013 and 13' are RF multiplied signal input or output terminals, respectively.
15.25.26.27 are high frequency bypass capacitors,
16 is the first coil, 18 is the second coil, 17Fi
, switching diode.

20はバラクタダイオード、19はコンデンサ、23゜
24は抵抗、21は第1バンド電圧端子、22は第2バ
ンド電圧端子、28は同調電圧端子である。この同調回
路は第1および第2の2つの受信帯域を受信するための
もので、スイッチングダイオード17を導通あるいは非
導通にすることでwc2あるいは第1の受信周波数帯域
を受信し、同調電圧により受信周波数を決定する。
20 is a varactor diode, 19 is a capacitor, 23 and 24 are resistors, 21 is a first band voltage terminal, 22 is a second band voltage terminal, and 28 is a tuning voltage terminal. This tuning circuit is for receiving two reception bands, the first and second, and receives wc2 or the first reception frequency band by making the switching diode 17 conductive or non-conducting, and receives the reception frequency band by the tuning voltage. Determine the frequency.

第3は本発明の別の実施例でダブルス−パーヘテロダイ
ン方式に本発明を応用した回路プロ・ 4 ・ ツク図である。29はRF信号入力端子、30はバンド
パスフィルタ、31は増幅器、52は第1ミクサ、33
はVCo、34はバンドパスフィルタ、35は第1IF
増幅器、36は第2ミクサ、37は固定発振器、38は
IF増幅器、39はIF出力端子。
The third is another embodiment of the present invention, which is a circuit diagram in which the present invention is applied to a double superheterodyne system. 29 is an RF signal input terminal, 30 is a band pass filter, 31 is an amplifier, 52 is a first mixer, 33
is a VCo, 34 is a bandpass filter, and 35 is the first IF.
36 is a second mixer, 37 is a fixed oscillator, 38 is an IF amplifier, and 39 is an IF output terminal.

40は第3ミクサ、41は固定分周器、42は分周出力
端子、4りはバンド電圧端子、43は同調電圧端子、4
4はAGC電圧端子である。RF信号入力端子29から
のRF倍信号複数の受信帯域に分割されたバンドパスフ
ィルタ30.増幅器31を介して第1ミクサでvCOに
より周波数変換され、RF倍信号りも高い周波数の第1
IF信号となり、バンドパスフィルタ34で帯域制限を
受は増幅器35で増幅された後第2ミクサにおいて固定
発振器の信号により通常のIP信号に周波数変換され、
増幅器58で増幅された後IF信号出力端子39より出
力される。vCOは電子チューナ外部に設けたPLL回
路により、第3ミクサ40で作られるVCOsxと固定
発振器37の発振周波数の差の信号を固定分周器41で
分周した信号を使って作り出された同調電圧で制御され
る。この時、固定分周器41からはVCOの周波数を分
周した信号を計数し、計数値に応じた受信帯域に設定す
るバンド電圧が出力され、これにより複数個のバンドパ
スフィルタからなるバンドパスフィルタ50の1を選択
的に動作させる0この場合のバンドパスフィルタ30は
第4図に示す様な構成例が考えられる。
40 is a third mixer, 41 is a fixed frequency divider, 42 is a frequency division output terminal, 4 is a band voltage terminal, 43 is a tuning voltage terminal, 4
4 is an AGC voltage terminal. A bandpass filter 30 that divides the RF multiplied signal from the RF signal input terminal 29 into a plurality of reception bands. The frequency is converted by VCO in the first mixer via the amplifier 31, and the RF multiplied signal is also converted into the first mixer with a higher frequency.
The signal becomes an IF signal, is band-limited by a bandpass filter 34, is amplified by an amplifier 35, and then frequency-converted into a normal IP signal by a signal from a fixed oscillator in a second mixer.
After being amplified by the amplifier 58, it is output from the IF signal output terminal 39. vCO is a tuning voltage created by a PLL circuit provided outside the electronic tuner using a signal obtained by dividing the signal of the difference between the oscillation frequencies of VCOsx created by the third mixer 40 and the fixed oscillator 37 by the fixed frequency divider 41. controlled by At this time, the fixed frequency divider 41 counts the signal obtained by dividing the frequency of the VCO, and outputs a band voltage to be set in the reception band according to the counted value. 1 of the filters 50 is selectively operated.The bandpass filter 30 in this case may have a configuration example as shown in FIG.

第4図は受信帯域を3分割し、スイッチングダイオード
で切り換えて、1つのバンドパスフィルタを選択して動
作させるもので、45および46はRF信号入力あるい
は出力端子、 47.48゜49は第1.第2.第3バ
ンドパスフイルタ、50はスイッチングダイオード、 
51.55.54は抵抗。
In Fig. 4, the receiving band is divided into three parts, and one band pass filter is selected and operated by switching with a switching diode, 45 and 46 are RF signal input or output terminals, 47.48° and 49 are the first and second band pass filters. .. Second. a third bandpass filter; 50 is a switching diode;
51.55.54 is resistance.

52は高周波バイパスコンデンサ、 55.56.57
は第1.第2.第3バンド電圧端子である。55゜56
.57のいずれか1つのバンド電圧端子に、第3図のバ
ンド電圧端子42′からの電圧が印加され、受信周波数
帯域に相当するバンドパスフィルタを動作させるスイッ
チングダイオードが導通状態となる。この時、他のスイ
ッチングダイオードはすべて非導通となる。
52 is a high frequency bypass capacitor, 55.56.57
is the first. Second. This is the third band voltage terminal. 55°56
.. The voltage from the band voltage terminal 42' in FIG. 3 is applied to one of the band voltage terminals 57, and the switching diode that operates the band pass filter corresponding to the reception frequency band becomes conductive. At this time, all other switching diodes become non-conductive.

第5図は第1図および第6図における固定分周器の第1
の構成例である。58はvCOの発振信号入力端子、5
9は分周出力端子、60はバンド電圧出力端子、61は
固定分周器、62は計数器。
Figure 5 shows the first fixed frequency divider in Figures 1 and 6.
This is a configuration example. 58 is the oscillation signal input terminal of vCO, 5
9 is a frequency division output terminal, 60 is a band voltage output terminal, 61 is a fixed frequency divider, and 62 is a counter.

63はバンド電圧発生器、64はデコーダ、65はラッ
チ回路である。発振信号入力端子58から入力し7’2
VCO信号は固定分周器61で分周され、分周信号の一
部はPLL回路へ、分周出力端子を介して供給される。
63 is a band voltage generator, 64 is a decoder, and 65 is a latch circuit. Input from oscillation signal input terminal 58 7'2
The VCO signal is frequency-divided by a fixed frequency divider 61, and a portion of the frequency-divided signal is supplied to the PLL circuit via a frequency-divided output terminal.

分周信号は、クロック発生器のクロック信号を基準にし
て計数器62においてクロックの期間だけ計数され、こ
の計数結果をデコーダ64に入力して複数個のゲート出
力とし、このゲート出力をバンド電圧発生回路65でク
ロック期間相当分だけ保持すると同時にバンド電圧とし
て出力する。バンド電圧発生回路ではデコーダ64の情
報を直接的にバンド電圧とするかあるいは、デコードさ
れた情報をあらかじめ受信周波数帯域に応じてROM等
に設定した・ 7 ・ 情報と比較してバンド電圧を発生させるなどの方法が考
えられる。
The frequency-divided signal is counted by a counter 62 for a clock period based on the clock signal of the clock generator, and this counting result is input to a decoder 64 to be outputted from a plurality of gates, and this gate output is used to generate a band voltage. The circuit 65 holds the voltage for a period corresponding to the clock period and simultaneously outputs it as a band voltage. The band voltage generation circuit generates a band voltage by directly converting the information from the decoder 64 into a band voltage, or by comparing the decoded information with information previously set in a ROM, etc. according to the receiving frequency band. Possible methods include:

〔発明の効果〕〔Effect of the invention〕

本発明によれば、固定分周器の出力信号を使って受信周
波数帯を切り換えるためのバンド電圧が得られるので電
子チューナと外部回路の接続が簡略されると同時に、周
波数により受信周波数帯の切り換えができるので正確な
切り換えが可能である。ま九、計数器、デコーダ、バン
ド電圧発生回路、クロック発生回路等を、固定分周器と
ともに集積化することも可能である。
According to the present invention, the band voltage for switching the reception frequency band is obtained using the output signal of the fixed frequency divider, so the connection between the electronic tuner and an external circuit is simplified, and at the same time, the reception frequency band can be switched depending on the frequency. This allows accurate switching. Furthermore, it is also possible to integrate a counter, a decoder, a band voltage generation circuit, a clock generation circuit, etc. together with a fixed frequency divider.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す回路ブロック図、
第2図は同調回路の一例を示す回路図、第3図は本発明
の第2の実施例を示す回路ブロック図、第4図はバンド
パスフィルタの構成の一例を示す回路図、第5図は本発
明の固定分周器を示し回路ブロック図である。 2・・・バンドパスフィルタ 4・・・バンドパスフィルタ ・ 8 ・ 6・・・VCO9・・・固定分周器 20・・・バンドパスフィルタ 52・・・第1ミクサ   53・・・VCO66・・
・第2ミクサ   37・・・固定発振器40・・・第
3ミクサ   41・・・固定分周器61・・・固定分
周器   62・・・計数器63・・・クロック発生回
路 64・・・デコーダ 65・・・バンド電圧発生回路
FIG. 1 is a circuit block diagram showing a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing an example of a tuning circuit, FIG. 3 is a circuit block diagram showing a second embodiment of the present invention, FIG. 4 is a circuit diagram showing an example of the configuration of a bandpass filter, and FIG. FIG. 1 is a circuit block diagram showing a fixed frequency divider according to the present invention. 2... Band pass filter 4... Band pass filter 8 6... VCO 9... Fixed frequency divider 20... Band pass filter 52... First mixer 53... VCO 66...
・Second mixer 37...Fixed oscillator 40...Third mixer 41...Fixed frequency divider 61...Fixed frequency divider 62...Counter 63...Clock generation circuit 64... Decoder 65...Band voltage generation circuit

Claims (1)

【特許請求の範囲】 1、電圧制御発振器の発振周波数を固定分周器により分
周した信号を用いてPLL(フェーズ・ロック・ループ
)回路により該発振周波数を決定し、複数の受信周波数
帯域のうちの1つを選択することによりテレビジョン信
号などの高周波信号を受信する電子チューナにおいて、
固定分周器の分周信号を出力すると同時に、該信号の周
波数を計数し、該計数値に応じた受信周波数帯切り換え
信号を出力する回路を電子チューナに内蔵させたことを
特徴とする電子チューナ。 2、固定分周器が、受信周波数帯切り換え信号を出力す
る回路を内蔵していることを特徴とする特許請求の範囲
第1項記載の電子チューナ。
[Claims] 1. Using a signal obtained by dividing the oscillation frequency of the voltage controlled oscillator by a fixed frequency divider, the oscillation frequency is determined by a PLL (phase-locked loop) circuit, and the oscillation frequency is determined by a PLL (phase-locked loop) circuit, and In an electronic tuner that receives a high frequency signal such as a television signal by selecting one of the
An electronic tuner characterized in that the electronic tuner has a built-in circuit that outputs a frequency-divided signal of a fixed frequency divider, simultaneously counts the frequency of the signal, and outputs a reception frequency band switching signal according to the counted value. . 2. The electronic tuner according to claim 1, wherein the fixed frequency divider includes a built-in circuit for outputting a reception frequency band switching signal.
JP24703185A 1985-11-06 1985-11-06 Electronic tuner incorporating fixed frequency divider having band changeover function Pending JPS62107529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24703185A JPS62107529A (en) 1985-11-06 1985-11-06 Electronic tuner incorporating fixed frequency divider having band changeover function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24703185A JPS62107529A (en) 1985-11-06 1985-11-06 Electronic tuner incorporating fixed frequency divider having band changeover function

Publications (1)

Publication Number Publication Date
JPS62107529A true JPS62107529A (en) 1987-05-18

Family

ID=17157376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24703185A Pending JPS62107529A (en) 1985-11-06 1985-11-06 Electronic tuner incorporating fixed frequency divider having band changeover function

Country Status (1)

Country Link
JP (1) JPS62107529A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1684429A1 (en) 2005-01-14 2006-07-26 Robert Bosch Gmbh Circuit arrangement and method for band switching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1684429A1 (en) 2005-01-14 2006-07-26 Robert Bosch Gmbh Circuit arrangement and method for band switching

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