JPS5931043Y2 - Frequency divider circuit - Google Patents

Description

[Detailed Description of the Invention] Some radio receivers use a synthesizer circuit to form a local oscillation signal of a desired frequency and use this to perform reception.

In this case, by changing the frequency division ratio of the frequency dividing circuit that forms the comparison signal within the synthesizer circuit, the variable range of the formed local oscillation signal changes, and therefore the receiving band can be changed.

The present invention relates to a frequency dividing circuit suitable for use in such cases.

First, an example of a receiver used in the present invention will be explained.

In addition, in this example, the reception frequency band is 1 to 30.
(2) h is divided into 29 bands of IMHz each, and each band can receive any frequency within that band.

In FIG. 1, 1 is an antenna, and 2 is a selector, which extracts a received signal of 1 to 30 MHz.This received signal is supplied to a variable bandpass filter 4 through a high frequency amplifier 3, and is converted into a received signal of a desired band. is taken out.

In this case, the pass band of the filter 4 is switched by the band select knob 40, for example, every six bands.

This received signal is then supplied to the first mixer circuit 51, and an oscillation signal from a first local oscillation circuit, that is, a VCO (voltage controlled variable frequency oscillator circuit) 21, which will be described later, is supplied to the mixer circuit 5 as a first local oscillation signal. Supplied.

Therefore, in the mixer circuit 5, among the received signals from the filter 4, only the received signal of the desired receiving frequency is frequency-converted into a first intermediate frequency signal having a carrier frequency of, for example, 45.145 MHz, and this first intermediate frequency signal is supplied to the second mixer circuit γ through the first intermediate frequency amplifier 6.

The mixer circuit 7 is also supplied with a first local oscillation signal having an oscillation frequency of 45.6 MHz from a second local oscillation circuit 11 that does not use a crystal oscillator.

Therefore, in the mixer circuit 7, the first intermediate frequency signal is frequency-converted into a second intermediate frequency signal having a carrier frequency of 455 kHz, and this second intermediate frequency signal is supplied to the detection circuit 9 through the second intermediate frequency amplifier 8. , the detected signal is extracted from the terminal 101.

Then, the first local oscillation signal is transmitted to the second local oscillation circuit 11, V
It is formed by the FO (variable frequency oscillation circuit) 12 and PLL 20 as follows.

That is, in the VFO 12, an oscillation signal whose frequency changes between 3.455 and 2.455 MHz is formed in response to the dial operation, and this oscillation signal is sent to the mixer circuit 1.
At the same time, the second local oscillation signal from the second local oscillation circuit 11 is supplied to the mixer circuit 13, and from the mixer circuit 13, a beat signal whose frequency changes between 42.145 and 43.145 MHz is supplied to the mixer circuit 13. is extracted, and this beat signal is passed through the bandpass filter 14 to the mixer circuit 2.
2I is supplied, and furthermore, this mixer circuit 22 is supplied with a VCO.
An oscillation signal from 21 is supplied.

In this way, a beat signal having a frequency that is the difference between the two signals supplied to the mixer circuit 22 is extracted from the mixer circuit 22.

This beat signal is then supplied to a frequency divider circuit 24 through a low-pass filter 23, where it is divided into the frequency of V2, and this frequency-divided signal is further supplied to a variable frequency divider circuit 25, where it is
The frequency is divided into N frequencies.

In this case, the frequency division ratio 1/N is set from 1/4 to 1/32 (N
=4 to 32).

This frequency-divided signal is then supplied to the phase comparison circuit 26, and at the same time, the fixed oscillation circuit 27 having a crystal oscillator
The kHz oscillation signal is supplied to the comparator circuit 26, the frequency-divided signal and the oscillation signal are phase-compared, and the comparison output is the VC
021 as its control signal.

Therefore, in a steady state, the frequency of the division signal from the frequency dividing circuit 25 is 50, which is the oscillation frequency of the oscillation circuit 2γ.
Since it is equal to 0 kHz, if the frequency division ratio 1/N of the frequency dividing circuit 25 is, for example, 1/4 (~4), the frequency of the frequency divided signal from the external dividing circuit 24 is 2 MHz, and the frequency of the frequency divided signal from the mixer circuit 22 is equal to 0 kHz. The frequency of the beat signal is 4 MHz.

In this case, the oscillation frequency of the VCO 21 is the sum of the frequency of the beat signal from the filter 14 and the frequency of the beat signal from the mixer circuit 22, and the frequency of the beat signal from the filter 14 is determined by the dial of the VFOl2. 42.145-43, 145 M corresponding to the operation
Varies between Hz.

Therefore, in the case of 1/N=174, from VCO21,
46.145-4 corresponding to VFOl2 dial operation
An oscillation signal whose oscillation frequency changes between 7.145 MHz is obtained.

On the other hand, when the frequency division ratio 1/N of the frequency dividing circuit 25 is 1/32 (N=32), the frequency of the beat signal from the mixer circuit 22 is 32 MHz.
1 to 74. corresponding to the vEO12 dial operation.
An oscillation signal whose oscillation frequency changes between 145 and 75.145 MHz is obtained.

That is, in general (here, the frequency of the beat signal from the mixer circuit 22 is N (MHz), so from the VCO 21, the VFOl 2 (7) dial operation) corresponds to (
42,145+N) ~ (43,145+N) (MHz)
An oscillation signal whose oscillation frequency changes between

This oscillation signal is then used as the first local oscillation signal.
While being supplied to the mixer circuit 5, the first intermediate frequency is
45.145 MHz, the receiving frequency band is 1 to 30 MHz, and in that case, the receiving band can be switched in IMHz units by changing the frequency division ratio 1/N of the frequency dividing circuit 25. Along with V.F.O.
By changing the oscillation frequency of l2, it is possible to receive any frequency in each reception band.

Incidentally, the frequency dividing circuit 25 having a variable frequency division ratio 17N used in such a circuit can be configured as follows using, for example, a presettable down counter.

That is, the contents of this down counter are preset to (N-1), a signal is supplied to this down counter, and when the next pulse is supplied with the contents of this down counter reaching II OII, , as soon as the output signal is taken out (this time, the down counter is again (
N-1).

This preset value can be changed depending on each reception band.

In this way, for example, when N=4, the counter will be 1, but the counter will be 3.
When the counter is preset and a signal is supplied to this counter, it counts down for each pulse, the third pulse is supplied, and the fourth pulse is supplied with the contents of the counter being "□ II". Then, the output signal is taken out and the counter is reset to 3 again.

This operation is repeated to obtain one output signal for every four pulses, and frequency division by 1/4 is performed.

This is the same even when N has other values.

However, there is generally little demand for the above-mentioned presettable down counter, and for this reason, it has not been integrated into an IC.

Therefore, when constructing such a circuit, it must be constructed from individual parts without using an IC, resulting in a very large circuit.

In view of these points, the present invention attempts to perform the same operation as described above using a presettable up-counter that is integrated into an IC.

Hereinafter, one example of the present invention will be explained with reference to FIG.

In FIG. 2, 51.52 is a presettable decimal up counter, 53.54 is a preset circuit, and 55 is a reset circuit.Counters 51 and 52 are connected in series, and a frequency dividing circuit 24 A branch signal from the station is supplied.

Further, the contents of the preset circuits 53 and 54 are switched by the band select knob 40 in accordance with the reception band.For example, as shown in FIG.
3 is set to be the complement of the 1st place number of the band number to 9, and the preset circuit 54 is set to the complement of the 10th place number of the band number to 3 (this is set).

Further, the reset circuit 55 is formed of, for example, a NAND circuit, and when II 41 It is output to the counters 51 and 52, a reset signal is generated.

As a result, the counters 51 and 52 are reset, the contents of the preset circuits 53 and 54 are taken out, the counters 51 and 52 are preset to that value, and the output signal is taken out and supplied to the comparison circuit 261. be done.

According to such a configuration, when the first band is selected by the band select knob 40, for example, II 81+ is set in the preset circuit 53 and "3" is set in the preset circuit 54.

Therefore, the counter 51°52t is 81+ and "
311 is preset and a frequency division signal is supplied to these counters 51 and 52, the counters 51 and 5 are counted up for each salt pulse, and the third pulse is supplied, and the counters 51 and 5
The content of 2 is "1" and II 411, i.e. II
When the fourth pulse is supplied in the state of 41If, one pulse is taken out from the counter 51.52 and supplied to the comparator circuit 26, and the signal II 4111 is output, which causes a reset. A reset signal is generated in circuit 55 which causes counter 51 .
52 is reset, and at this time, the preset circuits 53.54 supply signals of "8" and II 31+, and the counters 51.52 are reset to "811 and 11+" again.
3” (This is preset.

This operation is repeated, four pulses and one pulse of the frequency-divided signal are taken out, and the frequency is divided by 1/4.

This is the same when N is other values, and the frequency division by 17N is performed.

In this way, frequency division with a variable frequency division ratio of 1/N is performed.In this case, according to the present invention, a presettable up-counter is used, so it can be integrated into an IC and the circuit can be made smaller. .

In addition, in this circuit, the difference between the preset value, the reset value, and the frequency division ratio 1/N is (reset value) - (
There is a relationship of (preset value) + 1 = N, so the value to be reset may be a value equal to or greater than N at the maximum frequency division ratio.

[Brief explanation of drawings]

Figure 1 is a system diagram of an example of a receiver using the present invention;
The figure is a system diagram of an example of the present invention, and FIG. 3 is a diagram for explaining the same. 51.52 is an up counter, 53.54 is a preset circuit, and 55 is a reset circuit.

Claims (1)

[Claims for Utility Model Registration] A presettable up-counter, a reset circuit that detects the content of this up-counter and generates a reset signal when it reaches a first value, and a reset circuit that detects the content of this up-counter and generates a reset signal when the content reaches a first value; It has a preset circuit that presets the second value (this signal is taken out at the time of the above reset), and the frequency division is performed, and the second value can be changed by the band select knob. Frequency divider circuit.