JPS5818360Y2 - synthesizer type radio receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synthesizer type radio receiver equipped with a PLL.

An electronic tuning receiver is an analog type that uses a voltage memory element to generate a voltage that gradually increases depending on the command voltage and continues to output the voltage at that time when the command voltage disappears to change the capacity of the voltage variable element of the tuning circuit. In addition to the synthesizer type, a synthesizer type has appeared, especially for CB reception.

This synthesizer type receiver has the configuration shown in FIG.

In this figure, 1 is an antenna, 2 is a high frequency amplifier, 3 is a local oscillator, 4 is a mixing or frequency converter, 5 is an intermediate frequency amplifier, and 6 is a detection circuit. , 8.9 is a resonant circuit using a voltage variable capacitance element such as Paris Camp as a capacitor.

These parts are the same as the tuner section of a normal superheterodyne electronically tuned radio receiver.

In the case of a synthesizer type receiver, the varicap control and therefore tuning circuits include a key switch 10° controller 11, a prescaler 12, a 1/N programmable frequency divider 13, a reference frequency oscillator 14, its frequency divider 15, and a PLL A phase detector 16 and a low-pass filter 17 are provided.

The channel selection operation in this receiver is performed at frequencies 71.0 to 90, 0.
This will be explained below using FM broadcasting in Japan at MHz as an example.

The output frequency of the local oscillator 3 for the above FM broadcast frequency band is 65.3 to 79.3 MHz, but this is reduced to 1/10 by the prescaler 12, which is a splitter, to 6.53 to 7.93 MHz. do.

This is further divided into N=653 to 7930 by the divider 13.
Divide the frequency by a value of 1/N that changes between

The channel separation of FM broadcasting is 100KH2, so the broadcasting frequencies are 76.0, 76.1, 7
6.2..., in terms of local frequency, it is 65.3.65.
4, 65.5... and no other values, the output frequency of the divider 13 is always 10K when the N value is selected appropriately and tuned to the broadcast frequency.
Hz.

These N values 653, 654...793 are stored in the controller 11, and the key switch 10
(this will indicate the desired broadcasting station),
precent to divider 13.

On the other hand, the reference frequency oscillator 14 has a frequency of 5.76MHz in this example.
However, since the frequency is set to 11576 by the divider 15, the output of the divider is 10 KHz.

Therefore, the receiver is connected to the key switch 10 and the controller 1.
When the divider 13 is in the reception state corresponding to the precented N value in the thread path of 1, the output frequencies of the dividers 13 and 15 are both 10 KHz, and after the phase synchronization ratio, there is no output from the phase detector 16, and the tuning circuit is variable. The capacitive element is not adjusted, and the receiver enters the receiving state at this moment, but if the receiver reaches the receiving state corresponding to the N value, the phase detector 16 generates an output with a width and polarity corresponding to the deviation. After this is smoothed by a low-pass filter 17, it is applied to the variable capacitance elements of the resonance circuits 7-9.

Therefore, the reception frequency is adjusted, and when the output frequency of the divider 13 converges to 10 KHz and is synchronized, the adjustment ends and the reception state at the broadcasting station (broadcasting frequency) specified by the N value is entered.

This synthesizer type receiver allows highly accurate reception.

That is, the N value used for channel selection does not change, of course, and therefore the reception accuracy depends on the accuracy of the reference frequency oscillator 14, which is extremely accurate because it is a crystal oscillator.

By the way, the above example uses FM reception in Japan, so the frequency output by the reference frequency oscillator 14.15 is 10.
KHz, but the reception range was expanded regionally to the world,
In terms of signal format, in addition to FM, AMXLW (long wave), SW (
If the standard frequency is expanded to include short waves, there will be some inconveniences if the standard frequency is only 10 KHz, so it is set to 9 KHz, 5 KHz, etc.

Conventionally, this frequency switching was performed as shown in FIG.

That is, in this FIG. 2, 21 is output from the divider 15.
This is a reference signal switching circuit that outputs one of the frequencies of 0 KHz, 9 KHz, and 5 KHz to set the reference frequency fr, and performs the above switching upon receiving the signals Sa, Sb, and Sc.

In this figure, 3a and 3b indicate the local oscillation frequency for AMXFM after passing through the prescaler, and
, S2 is an AM or FM signal, and becomes H (high) level when AM or FM reception is selected (Nando Game) 24.25
open.

S3 is a signal for cutting off the output of the local oscillator, and turns on and off the power to the amplifiers 22 and 23 that amplify the outputs of the local oscillators 3a and 3b.

26 is the or gate. T1 to T4 are digit synchronization signals, D
A-DD is a BCD signal, and the details will be described later, but to give an overview, the signal DA-DD is the 1st and 10th N value.
The decimal values of the 1st and 100th digits are specified, and T1 to T4 select and rank the circuits in which they are launched.

By the way, as is clear from FIG. 2, the switching of the reference frequency fr depends on the signals Sa, Sb, and Sc.
There are multiple circuit configurations.

The present invention attempts to improve this point and simplify the circuit configuration.

That is, as mentioned above, each digit of the N value from O to 9 is 4 pinto 2.
Although specified by the value signals DA-DD, the range of the N value is 653 to 793 in the above example, and a three-digit number is sufficient.

However, in the case of shortwave, the broadcasting frequency range is 4550 to 120.
00KHz % Channel Separation Id 5K
Hz.

The local frequency is 5000~12450KHz, and from these relationships, the reference frequency 5KHzXN=1000~24
Since it is set to 90, the N value is a 4-digit number.

However, since the highest number in the thousandth place is 2, it can be expressed with a 2-pinto binary code and a 4-pinto code D.
2 points are left over for A to DD.

The present invention focuses on this point, and uses the 2 pins Dc and DD at the highest level T4 as the reference signal switching signal to
a-8c is unnecessary, and also used as a local oscillation output cutoff signal, making signal S3 unnecessary.

This will be explained in detail below with reference to the embodiment shown in FIG.

In Figure 3, 15a, 15b, 15c are 1/4° 1/16,
The frequency dividers of 1/9, 1/10, and 1/18 correspond to the aforementioned divider 15.

13a. 13b, 13c, 13d are 1st place, 10th place, 10th place
This is a decimal preset down counter corresponding to the 0th and 1000th positions, and corresponds to the programmable frequency divider 13 described above.

11a, 11b, 11c. 11d is a 4-bit branch circuit that takes in each digit of the N value.

All 4-bit outputs of the launch circuits 11a to 11c are connected to the counters 13a to 13c, but only the 2 pin outputs of the last launch circuit 11d are connected to the counter 13d to specify the N value. The two pinpoint outputs 11d□ and 11d2, which are not used, are connected to the reference frequency switching circuit 21.

Reference numeral 30 denotes an amplifier, which corresponds to amplifiers 22 and 23 in FIG. 2, but for the sake of simplicity, they are shown collectively without being divided into AMXFM systems.

31 is an OR gate; 32 is a frequency divider that divides the output frequency of the 5KHz divider 15C to 1/100 and outputs a 50Hz clock reference pulse; 33 is an input terminal to which the local frequency that has passed through the prescaler is applied; 34,3
5 is a Vdd and Vss power supply terminal, 36 is a bias voltage output terminal to the variable capacitance element, and 37 is a clock reference pulse output terminal.

To explain the operation, our country's FM82.5 is -fIJ.
If MHz is to be received, the local frequency is 82.5
-10.7=71.8 (MHz), and if the frequency is divided by 1/10 with a pre-scaler and the reference frequency fr is 10 KHz, N=718.

The digit synchronization signals T□ to T4 are generated at the timing shown in FIG. 4 and are input to the 4-bit branch circuits 11a to 11d, so first, the 4-bit binary codes DD, DC2DB, and DA are set to 100.
As 0, the first numeric value 8 of the N value is taken into the launch circuit 11a at the timing T□, then the DDDA is set as 0001, and the 10th digit 1 of the N value is taken into the launch circuit 11b at the timing T2, and then DDDA is taken into the launch circuit 11b at the timing T2. -N with DA as 0111
The iooth numerical value 7 is taken into the launch circuit 11c at the timing T3.

At the next timing T4, the launch circuit 11d takes in the 1000th place value of the N value and switching information such as the reference frequency, but in this example, the 1000th place value of the N value is O, so DA=DB2. 〇, and the reference frequency fr is 10KH
z, so it is set as DC""Os DD-1.

Note that the selection of the reference frequency fr is determined in advance using the focus Dc and DD as follows, for example.

When the N value is thus taken into the launch circuits 11a to 11d, the counters 13a to 13d take in the contents of the launch circuits 11a to 11d all at once each time the 0-)" signal S4 is input.
A down count is started using the local frequency input from the terminal 33.

Further, the two output terminals of the launch circuit 11d are input to the reference signal switching circuit 21, and this circuit is connected to the 10KH signal of the divider 15c.
The z output is output to the phase detector 16.

When counters 13a to 13c have counted 718 pulses of the local frequency, all counts become OK, and counter 1
Since 3d is O from the beginning, the output of the OR gate G becomes L level at this time, and one pulse is output to the phase detector 16.

This pulse is also applied to the counters 13a to 13d and becomes a load signal, so that the counters 13a to 13d are again preset to the N value and count down the local frequency.

This is repeated below, but the frequency fp of the pulse outputted from the OR gate 31 is 1/N of the local oscillation frequency (after being set to '10' by the prescaler).

The signal of frequency fp is compared with the reference signal of frequency fr by the phase detector 16, and as shown in FIG.
If fr=fp, a positive pulse signal S5 with a pulse width corresponding to the phase difference is generated, and if fr=fp, the pulse signal S5 has an amplitude of zero.

The output pulse signal S5 of this phase detector 16 is input to a low-pass filter 17 and smoothed, and then
This is the bias voltage for the variable capacitance element 9 (FIG. 1).

If 2 bits DC9DD of the 4-bit binary code given at the generation timing of the digit synchronization signal T4 are switched to 10 or OO, it becomes 9KHz or 5KHz as is clear from Table 1 above.
When the reference frequency fr of KHz is selected and it is set to 11, the reference signal switching circuit 21 turns off the power supply So to the amplifier 30, making the amplifier inoperable.

Therefore, the power consumption of the amplifier 30 becomes zero, the counters 13a to 13d stop counting, and the phase detector 16, etc., that is, the PLL stops operating, so the power consumption becomes very small.

Although not shown, the N value taken into the latch circuits 11a to 11d is guided to a 7-segment display to display the reception frequency, but when DC=DD=1, the input to the display is input to the divider 32. It is switched to the output of the clock circuit that receives the output and displays the time.

As explained in detail above, according to the present invention, the reference frequency switching information and a signal that disables the PLL etc. are included in the division ratio given to the frequency divider, which simplifies the structure of the synthesizer type receiver. can be used to reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synthesizer type receiver, FIG. 2 is a block diagram mainly showing the reference frequency switching circuit section of the receiver, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 5 and FIG. 5 are waveform diagrams illustrating the operation. In the drawing, 13a to 13d are programmable frequency dividers, 16 and 17 are PLL circuits, 11a to 11d are launch circuits, 11d is a launch circuit that takes the highest N value, and 11d
11d2 is a 2-pin output which is not used for specifying the N value, and 21 is a reference frequency switching circuit.

Claims (1)

[Scope of utility model registration request] The number N that determines the frequency division ratio is precented, and the local oscillation frequency is counted down to 1/N of the local oscillation frequency.
A programmable frequency divider that outputs a frequency, and a PLL circuit that compares the phases of a reference frequency and the output frequency of the divider and generates a voltage that controls a tuning voltage variable capacitance element of a receiver tuner section according to the difference. , the N
In a synthesizer type radio receiver that receives the broadcast of a station specified by a value, four launch circuits are provided to take in each digit of the N value of up to four digits, and the divider and P
A reference frequency switching circuit is provided between the LL circuit and the N
A 2-bit output that is not used for specifying the N value of the launch circuit that takes in the highest value is connected so as to be applied to the reference frequency switching circuit as a reference frequency switching command and a local oscillation frequency signal cutoff command. A synthesizer type radio receiver characterized by: