JPS63246020A - Tuner - Google Patents

Tuner

Info

Publication number
JPS63246020A
JPS63246020A JP62080734A JP8073487A JPS63246020A JP S63246020 A JPS63246020 A JP S63246020A JP 62080734 A JP62080734 A JP 62080734A JP 8073487 A JP8073487 A JP 8073487A JP S63246020 A JPS63246020 A JP S63246020A
Authority
JP
Japan
Prior art keywords
frequency
circuit
oscillator
voltage
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62080734A
Other languages
Japanese (ja)
Inventor
Fuminori Suzuki
文典 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP62080734A priority Critical patent/JPS63246020A/en
Publication of JPS63246020A publication Critical patent/JPS63246020A/en
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To eliminate the need for an externally mounted LC circuit by providing a local oscillator circuit outputting a pulsating current frequency appearing at the terminal voltage of an impedance element in series with the power supply of an inverter ring oscillator as a local oscillation frequency. CONSTITUTION:An RF frequency signal from an antenna 1 is mixed with a local oscillation signal from a local oscillator 5 by a mixer circuit 3 via an RF amplifier 2 and used as an IF signal, and outputted via an IF filter 20 and an IF amplifier 4. On the other hand, a converter 6 outputs a voltage Vc according to the frequency data from a memory 7 operated externally. The output current of an inverter ring oscillator 51 of the local oscillator 5 is controlled by the voltage Vc, a pulsating current is extracted by a current control FET as a voltage and fed to the mixer 3 via a BPF 53 and an amplifier 54.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テレビ、ラジオ、無線機等のチューナーに関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to tuners for televisions, radios, radios, etc.

〔従来の技術〕[Conventional technology]

従来より、スーパーヘテロダイン方式のチューナーは、
LC共振回路を用いた局部発振器を使用していた。
Traditionally, superheterodyne tuners are
A local oscillator using an LC resonant circuit was used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

チ瓢−す−の小型化が進み、ワンチップのFMチューナ
ーが出現している今日においても、局部発振器用の共振
用LC回路だけは外付けせざるを得す、最後まで問題と
して残っていた。また、完全モノリンツク化するために
局部発振器を単なるCMOSインバータリングで構成す
ると充分に高い周波数が得られず、周波数を上げようと
すれば消費電流が大きくなってしまうと言う問題があっ
た。
Even today, when electronic devices are becoming smaller and one-chip FM tuners have appeared, only the resonant LC circuit for the local oscillator has to be externally connected, which remained a problem until the end. . Furthermore, if the local oscillator is configured with a simple CMOS inverter in order to achieve a completely monolink system, a sufficiently high frequency cannot be obtained, and there is a problem in that if the frequency is increased, the current consumption increases.

本発明は、局部発振器にインバータリングを用い、その
消費電流波形を局発信号として動作し、モノリシック化
とLC部品の削減を目的とするものである。
The present invention uses an inverter in a local oscillator, operates its current consumption waveform as a local oscillator signal, and aims to achieve monolithic design and reduce the number of LC components.

〔問題点を解決するための手段〕[Means for solving problems]

このような問題に対し1本発明のチューナーは、奇数個
のCMOSインバータをリング状に直列接続したインバ
ータリング発振器と前記インバータリング発振器の電源
に直列接続したインピーダンス素子とを有し、前記イン
ピーダンス素子の端子ヱ正に現れる脈動電流周波数を局
部発振周波数として出力することにより外付LC回路を
不要とした局部発振器を備えたことを特徴とするもので
ある。
In order to solve such problems, the tuner of the present invention includes an inverter ring oscillator in which an odd number of CMOS inverters are connected in series in a ring shape, and an impedance element connected in series to the power supply of the inverter ring oscillator. This device is characterized by being equipped with a local oscillator that eliminates the need for an external LC circuit by outputting the pulsating current frequency appearing at the terminal as a local oscillation frequency.

〔実施例〕〔Example〕

第1図は、本発明のチ具−す−の一実施例を示す回路ブ
ロック図である。1はアンテナ、2はRF増幅器、6は
混合回路、20はIPフィルター、4は中間周波増幅器
、5は本発明の特徴点である局部発振器、6はD/Aコ
ンバータ、7はメモリーである。アンテナ1からのRF
周波数信号は、RF増幅器2で増幅され、更に混合回路
6で局部発振器5からの局発信号と混合されて中間周波
数信号(以降、IF倍信号言う。)となり、IFフィル
ター20を通って、最後に中間周波増幅器4により増幅
されて出力される。このIP倍信号検波回路(図示せず
)によってビデオ信号その他に変換される。
FIG. 1 is a circuit block diagram showing an embodiment of the tool of the present invention. 1 is an antenna, 2 is an RF amplifier, 6 is a mixing circuit, 20 is an IP filter, 4 is an intermediate frequency amplifier, 5 is a local oscillator which is a feature of the present invention, 6 is a D/A converter, and 7 is a memory. RF from antenna 1
The frequency signal is amplified by the RF amplifier 2, further mixed with the local oscillator signal from the local oscillator 5 by the mixing circuit 6 to become an intermediate frequency signal (hereinafter referred to as the IF multiplied signal), passed through the IF filter 20, and finally The signal is then amplified by the intermediate frequency amplifier 4 and output. This IP multiplied signal detection circuit (not shown) converts the signal into a video signal or other signal.

局発周波数はD/Aコンバータ6からのチューニング電
圧Vcによりコントロールされ、前記D/Aコンバータ
6は外部操作可能なメモリー7からの周波数データに従
って電圧Vcを出力する。
The local frequency is controlled by a tuning voltage Vc from a D/A converter 6, and the D/A converter 6 outputs a voltage Vc according to frequency data from an externally operable memory 7.

本発明の特徴点である前記局部発振器5は、インバータ
リング発振器51と、前記インバータリング発振器51
の動作電流を前記VcK従って制限するために前記イン
バータリング発振器51の電源に直列接続した電流制御
FET52と、前記電流制御FE752のドレイン端子
に現れる脈動電圧から余計な周波数成分を取り除(バン
ドパスフィルター56と増幅器54により構成されてい
る。
The local oscillator 5, which is a feature of the present invention, includes an inverting oscillator 51 and an inverting oscillator 51.
A current control FET 52 is connected in series with the power supply of the inverting oscillator 51 in order to limit the operating current of the VcK, and an unnecessary frequency component is removed from the pulsating voltage appearing at the drain terminal of the current control FE 752 (a band-pass filter is used). 56 and an amplifier 54.

第2図は前記脈動電圧の発生メカニズムを説明するため
の略図である。第2図(a)は、5段の場合のインバー
タリング発振器51の構成図であり、インバータ11〜
15をリング状に接続して構成されているが、各々のゲ
ート容量等により寄生容量C1〜C5も存在する形とな
っている。
FIG. 2 is a schematic diagram for explaining the mechanism of generating the pulsating voltage. FIG. 2(a) is a configuration diagram of the inverting oscillator 51 in the case of five stages, and the inverter 11 to
15 connected in a ring shape, parasitic capacitances C1 to C5 also exist due to the respective gate capacitances.

第2図(b)は、各インバータの出力電圧な■1〜v5
とした時のタイムチャート図である。インバータのpc
h、l’Jch両方のFETを一瞬貫通するいわゆる貫
通電流が前記寄生容量C1〜C5の充放電電流に比べて
非常に小さい場合、このインバータリング発振器51の
動作電流は、Nc h FETがONになるタイミング
で流れることになるので、第2図(b)に示すIdのよ
うな形になる。この電流が前記電流制御FET52に流
れるとドレイン端子電圧も前記Idと同様の形となり、
その周波数はインバータリング発振周波数の丁度5倍と
なる。
Figure 2(b) shows the output voltage of each inverter.
It is a time chart figure when it does. inverter pc
When the so-called through current that momentarily passes through both the h and l'Jch FETs is very small compared to the charging/discharging current of the parasitic capacitances C1 to C5, the operating current of the inverting oscillator 51 is the same as when the Nch FET is turned on. Since it flows at the timing shown in FIG. 2(b), the shape is as shown in FIG. When this current flows through the current control FET 52, the drain terminal voltage also has the same form as Id,
Its frequency is exactly five times the inverting oscillation frequency.

この場合、脈動電流を電圧として取り出すために周波数
調整用のFETを兼用したが、高周波で比較的高いイン
ピーダンスを持つ素子であれば良く、単なる抵抗やIC
内に渦巻状にアルミ配線を巻いたインダクターを使って
も良い。
In this case, a frequency adjustment FET was also used to extract the pulsating current as a voltage, but any element that has a relatively high impedance at high frequency will suffice, such as a simple resistor or an IC.
You can also use an inductor with aluminum wire wrapped inside it in a spiral shape.

なお、前記寄生容量C1〜C5を非常に小さくするか、
或は前記貫通電流を太き(すれば丁度10倍の周波数が
得られる。
Note that the parasitic capacitances C1 to C5 may be made very small, or
Alternatively, the through current can be made thicker (if this is done, a frequency exactly 10 times higher can be obtained).

第3図は、本発明の別の実施例を示す回路ブロック図で
ある。第1図と異なる部分は局部発振器500回路構成
と、局部発振周波数をPLL方式によりて制御するため
の可変分周回路8と水晶発振回路9と7工イズ検出回路
10とを追加したことである。前記フェイズ検出回路1
0は、前記可変分周回路8からの信号と前記水晶発振回
路9からの信号とを比較して周波数が一致するようにそ
の出力信号Vcをコントロニルする一般的構成となって
いる。局部発振器50は、インバータリング発振器51
の発振信号を波形整形する波形整形回路55を備えてい
るため、局部発振周波数の5分の1の周波数を出力する
よう構成されていることになる。これにより、可変分周
回路8の構成は超高速である必要が無(なり、CMOS
ブリップ70ツブによる構成が可能となる。
FIG. 3 is a circuit block diagram showing another embodiment of the present invention. The difference from FIG. 1 is the addition of a local oscillator 500 circuit configuration, a variable frequency divider circuit 8, a crystal oscillation circuit 9, and a 7-speed detection circuit 10 for controlling the local oscillation frequency using a PLL method. . The phase detection circuit 1
0 has a general configuration in which the signal from the variable frequency divider circuit 8 and the signal from the crystal oscillation circuit 9 are compared and the output signal Vc is controlled so that the frequencies match. The local oscillator 50 is an inverting oscillator 51
Since it is provided with a waveform shaping circuit 55 that shapes the waveform of the oscillation signal, it is configured to output a frequency that is one-fifth of the local oscillation frequency. As a result, the configuration of the variable frequency divider circuit 8 does not need to be ultra-high speed (it becomes CMOS
A configuration with 70 blips is possible.

〔発明の効果〕〔Effect of the invention〕

このように、本発明によれば、CMO8では従来得られ
なかった高い周波数の信号を得ることが出来るほか、従
来外付していたLC共振回路が要らな(なり、さらにプ
リスケーラ−(超高速固定分周器)の機能も有するため
、従来大きな電流を消費していた局部発振用バッファー
とプリスケーラ−も不要となるなど革命的効果があり、
チューナーの小型化に貢献する。
As described above, according to the present invention, in addition to being able to obtain high-frequency signals that could not be obtained conventionally with CMO8, there is no need for the conventional external LC resonant circuit, and there is also a prescaler (ultra high-speed fixed Since it also has the function of a frequency divider), it has revolutionary effects such as eliminating the need for local oscillation buffers and prescalers, which conventionally consumed large currents.
Contributes to miniaturization of tuners.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の実施例を示し、第1図はチーーナーの構
成を示す回路ブロック図、第2図(a)は5段の場合の
インバータリング発振器の回路図、第2図(b)は各イ
ンバータの出力電圧をv1〜■5とした時のタイムチャ
ート図、第3図は、他の実施例を示す回路ブロック図で
ある。 2・・・・・・RF増幅器、 6・・・・・・混合回路、 5.50・・・・・・局部発振器、
The drawings show an embodiment of the present invention, and FIG. 1 is a circuit block diagram showing the configuration of a tuner, FIG. 2(a) is a circuit diagram of an inverting oscillator in the case of five stages, and FIG. FIG. 3 is a time chart diagram when the output voltage of the inverter is set to v1 to v5, and FIG. 3 is a circuit block diagram showing another embodiment. 2...RF amplifier, 6...Mixing circuit, 5.50...Local oscillator,

Claims (1)

【特許請求の範囲】[Claims] 奇数個のCMOSインバータをリング状に直列接続した
インバータリング発振器と前記インバータリング発振器
の電源に直列接続したインピーダンス素子とを有し、前
記インピーダンス素子の端子電圧に現れる脈動電流周波
数を局部発振周波数として出力する局部発振器を備えた
ことを特徴とするチューナー。
It has an inverter ring oscillator in which an odd number of CMOS inverters are connected in series in a ring shape, and an impedance element connected in series to the power supply of the inverter ring oscillator, and outputs the pulsating current frequency appearing in the terminal voltage of the impedance element as a local oscillation frequency. A tuner characterized by being equipped with a local oscillator.
JP62080734A 1987-03-31 1987-03-31 Tuner Pending JPS63246020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62080734A JPS63246020A (en) 1987-03-31 1987-03-31 Tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62080734A JPS63246020A (en) 1987-03-31 1987-03-31 Tuner

Publications (1)

Publication Number Publication Date
JPS63246020A true JPS63246020A (en) 1988-10-13

Family

ID=13726612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62080734A Pending JPS63246020A (en) 1987-03-31 1987-03-31 Tuner

Country Status (1)

Country Link
JP (1) JPS63246020A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430493A2 (en) * 1989-11-27 1991-06-05 Seiko Instruments Inc. Signal processor
KR100404395B1 (en) * 2001-09-24 2003-11-03 엘지이노텍 주식회사 Tuner
JP2007081982A (en) * 2005-09-15 2007-03-29 Ntt Electornics Corp Clock reproducing circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430493A2 (en) * 1989-11-27 1991-06-05 Seiko Instruments Inc. Signal processor
EP0430493A3 (en) * 1989-11-27 1991-11-27 Seiko Instruments Inc. Signal processor
KR100404395B1 (en) * 2001-09-24 2003-11-03 엘지이노텍 주식회사 Tuner
JP2007081982A (en) * 2005-09-15 2007-03-29 Ntt Electornics Corp Clock reproducing circuit
JP4531667B2 (en) * 2005-09-15 2010-08-25 Nttエレクトロニクス株式会社 Clock recovery circuit

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