JP3798078B2 - Tuning control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tuning control system that extracts only a desired frequency component.
[0002]
[Background Art and Problems to be Solved by the Invention]
Various tuning amplifiers using active elements and reactance elements have been proposed and put into practical use. For example, in a conventional tuning amplifier using LC resonance, the Q and gain depending on the LC circuit change when the tuning frequency is adjusted, and the tuning frequency and the gain at the tuning frequency change when the maximum attenuation is adjusted.
[0003]
As described above, in the conventional tuning amplifier, it is extremely difficult to adjust the tuning frequency, the gain at the tuning frequency, and the maximum attenuation amount without interfering with each other. Also, it has been difficult to form a tuning amplifier that can adjust the tuning frequency and the maximum attenuation amount by an integrated circuit.
[0004]
Even if components other than the inductor included in the tuning amplifier are formed on the semiconductor substrate, the element constants of the resistors and capacitors vary from production lot to production lot, making it difficult and practical to obtain the desired tuning frequency. There wasn't.
[0005]
The present invention was created in view of the above points, and its purpose is suitable for integration, and even when integrated, a tuning control system that can be easily adjusted to a desired tuning frequency. Is to provide.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problem, a tuning control system according to claim 1 includes a PLL control circuit that performs PLL control on the tuning circuit, and a frequency control that matches the tuning frequency of the tuning circuit with the frequency of the input signal of the tuning circuit. A circuit and a tuning control circuit. When the desired tuning frequency is not stably set in the tuning circuit, the tuning control circuit sets the loop gain of the feedback loop formed in the tuning circuit to a predetermined value or more to oscillate the tuning circuit. The PLL control is performed by the PLL control circuit. Therefore, a desired tuning frequency is set quickly and accurately in the tuning circuit. On the other hand, when a desired tuning frequency is stably set in the tuning circuit, the tuning control circuit sets the loop gain below a predetermined value and extracts only the tuning frequency component from the input signal of the tuning circuit. For this reason, the fluctuation | variation of a tuning frequency is suppressed.
[0007]
The tuning control system according to claim 2 is provided with an input switching means for inputting an input signal to the tuning circuit only when the tuning frequency of the tuning circuit is set.
[0008]
In the tuning control system according to the third aspect, the output of the PLL control circuit is input to the frequency control circuit, and when setting the tuning frequency of the tuning circuit, a signal corresponding to the output of the PLL control circuit is output from the frequency control circuit. The tuning circuit oscillates by this signal. On the other hand, after the tuning frequency of the tuning circuit is set, a signal corresponding to the phase difference between the input and output signals of the tuning circuit is output from the frequency control circuit, and the tuning circuit performs a tuning operation by this signal.
[0009]
The tuning control system according to claim 4 pays attention to the fact that the phase comparison result by the PLL control circuit coincides when the desired tuning frequency is stably set in the tuning circuit, and tunes based on the phase comparison result by the PLL control circuit. It is determined whether the tuning frequency of the circuit has been set.
[0010]
According to a fifth aspect of the present invention, the tuning control system includes two opening / closing means for passing or blocking a signal having a pulse width corresponding to the phase difference according to the polarity of the phase difference between the input and output of the tuning circuit. Then, when setting the tuning frequency of the tuning circuit, the tuning control circuit supplies a voltage according to the comparison result by the phase comparator to the charge pump to perform PLL control on the tuning circuit, thereby tuning the tuning circuit. After the frequency is set, the outputs of the two switching means are supplied to the charge pump so that the tuning frequency matches the frequency of the input signal to the tuning circuit.
[0011]
In the tuning control system according to the sixth aspect, two phase shift circuits each including a differential amplifier and a series circuit are connected in cascade to constitute a tuning circuit.
[0012]
In the tuning control system according to claim 7, a first resistor is connected between the inverting input terminal of the differential amplifier and the series circuit, and a second resistor is connected between the output terminal and the inverting input terminal of the differential amplifier. Connecting. The amplitude of the tuning signal can be adjusted by changing the resistance ratio of the first and second resistors.
[0013]
In the tuning control system according to the eighth aspect, the first voltage dividing circuit is connected to the output terminal of the differential amplifier, and the output of the subsequent phase shift circuit is fed back to the input side of the differential amplifier via the voltage dividing circuit. . By providing a voltage dividing circuit, a loop gain can be earned.
[0014]
In the tuning control system according to claim 9, a first resistor is provided between the inverting input terminal of the differential amplifier and the series circuit, and a second resistor is provided between the output terminal and the inverting input terminal of the differential amplifier. A third resistor connected to the inverting input terminal of the differential amplifier and grounded at the other end is provided. Since the third resistor is provided, the amplitude variation of the tuning output can be suppressed even if the resistance ratio between the first resistor and the second resistor is other than 1.
[0015]
In the tuning control system according to the tenth aspect, a potential difference between the potential of the output terminal of the voltage dividing circuit and the potential of the connection portion between the capacitor or the inductor and the resistor in the series circuit is amplified by the differential amplifier and outputted.
[0016]
In the tuning control system according to the eleventh aspect, a non-inverting circuit is inserted into a part of a feedback loop formed by two phase shift circuits connected in cascade. Even if a loss occurs by passing through the phase shift circuit, a gain can be gained by the non-inverting circuit.
[0017]
In the tuning control system according to the twelfth aspect, a phase inversion circuit is inserted into a part of a feedback loop formed by two cascaded phase shift circuits. Even if a loss occurs by passing through the phase shift circuit, a gain can be gained by the phase inversion circuit.
[0018]
In the tuning control system according to claim 13, a second voltage dividing circuit is connected to a part of a feedback loop formed by two phase shift circuits, and an AC signal input to the second voltage dividing circuit is used as a tuning signal. Output. The tuning signal can be amplified and output according to the voltage dividing ratio of the second voltage dividing circuit.
[0019]
The tuning control system according to claims 14 and 16 includes conversion means for converting the input AC signal into an in-phase and reverse-phase AC signal and outputting the same, and the conversion means is constituted by a transistor, for example. Each of the two phase shift circuits shifts the phase according to the frequency of the input signal.
[0020]
In the tuning control system according to claims 15 and 17, a voltage dividing circuit is inserted into a part of a feedback loop formed by two phase shift circuits and a non-inverting circuit, and an AC signal input to the voltage dividing circuit is used as a tuning signal. Output. The amplitude of the tuning output can be adjusted according to the voltage dividing ratio of the voltage dividing circuit.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a tuning control system of the present invention will be specifically described with reference to the drawings.
[0022]
[A. Overall configuration and operation of tuning mechanism]
The tuning control system of the present invention performs PLL control on the tuning circuit so as to set a desired tuning frequency in the tuning circuit, and after the desired tuning frequency is set in the tuning circuit, between the input and output of the tuning circuit. Control is performed to detect the phase difference and make the tuning frequency coincide with the frequency of the input signal.
[0023]
[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the first embodiment of the tuning mechanism. The tuning mechanism shown in FIG. 1 includes a tuning circuit 1, a frequency control circuit 2, a PLL control circuit 3, a tuning detection circuit 4, and an input switching circuit 5.
[0024]
As will be described later, the tuning circuit 1 includes two phase shift circuits, and the phase shift amount of the two phase shift circuits is set to 360 ° at a predetermined frequency. A series circuit composed of a CR circuit or an LR circuit is provided in the tuning circuit 1, and the time constant of the series circuit can be changed by a control signal from the PLL control circuit 3. That is, the PLL control circuit 3 changes and controls the time constant of the series circuit so that the total phase shift amount of the two phase shift circuits is 360 °, whereby the tuning circuit 1 oscillates at a predetermined frequency. . This predetermined frequency is a tuning frequency for the frequency control circuit 2 to perform a tuning operation.
[0025]
The frequency control circuit 2 performs a tuning operation for matching the tuning frequency with the frequency of the input signal of the tuning circuit 1. Specifically, the frequency control circuit 2 changes and controls the time constant of the series circuit described above so that the deviation between the tuning frequency and the frequency of the input signal of the tuning circuit 1 is eliminated.
[0026]
Thus, both the frequency control circuit 2 and the PLL control circuit 3 change and control the time constant of the series circuit in the tuning circuit 1, and the oscillation for the tuning circuit 1 to stably oscillate at a predetermined frequency. The conditions are the same as the tuning conditions for the tuning circuit 1 to perform a tuning operation for extracting only a predetermined frequency component.
[0027]
Specifically, the frequency control circuit 2 is configured to include a synchronous rectification circuit 21 and a control signal generation circuit 22, and synchronously rectifies the input signal of the tuning circuit 1 using the output signal of the tuning circuit 1 as a reference signal. The rectified output is supplied to the control signal generation circuit 22 at the subsequent stage.
[0028]
The control signal generation circuit 22 includes a pulse conversion circuit 23, a polarity determination circuit 24, and a voltage synthesis circuit 25. The control signal generation circuit 22 detects the phase difference between the input and output signals of the tuning circuit 1 described above, and the magnitude of this phase difference. The control signal is generated so as to eliminate the phase difference. The pulse conversion circuit 23 outputs a pulse train having a pulse width corresponding to a time interval in which a voltage component corresponding to a shift output from the synchronous rectification circuit 21 (phase shift between input and output signals of the tuning circuit 1) appears. The polarity discriminating circuit 24 discriminates the polarity of the phase difference depending on whether the voltage component corresponding to the phase shift outputted from the synchronous rectifying circuit 21 appears before or after the half-wave rectified waveform. The polarity of this phase difference indicates whether the tuning frequency is low or high with respect to the frequency of the input signal (more precisely, the frequency of the signal desired to be extracted from the input signal by passing through the tuning circuit 1). is there. The voltage synthesis circuit 25 generates a voltage according to the pulse width of the signal output from the pulse conversion circuit 23, and adds the generated voltage according to the polarity of the phase difference determined by the polarity determination circuit 24. The voltage is synthesized by subtraction, and the synthesized voltage is supplied to the tuning circuit 1 as a control signal.
[0029]
The PLL control circuit 3 includes an oscillator (OSC) 31, a phase comparator (PD) 32, a charge pump (CP) 33, and a low-pass filter (LPF) 34, and a tuning signal output from the tuning circuit 1 is predetermined. By comparing the phase with the reference frequency signal, the tuning circuit 1 is subjected to PLL control, and the tuning frequency is set. The phase comparator 32 includes two input terminals and two output terminals, and compares the phase and frequency of signals input to both input terminals. The charge pump 33 includes a capacitor therein, and charges and discharges the capacitor according to two types of pulse trains output from the two output terminals of the phase comparator 32. The low pass filter 34 removes the high frequency component from the output of the charge pump 33 to extract only the direct current component, and supplies this direct current component to the frequency control circuit 2 as a control signal for setting the tuning frequency. The oscillator 3 generates a reference frequency signal having the same frequency as the tuning frequency to be controlled to be constant. The output waveform of the oscillator 3 need not be a sine wave with little distortion, but may be a rectangular wave or a distorted sine wave. In order to stabilize the tuning frequency, the configuration of the oscillator 3 is preferably a PLL (phase locked loop) configuration using a crystal resonator.
[0030]
FIG. 2 is a diagram illustrating an example of an oscillator 3 having a PLL configuration. The oscillator 3 shown in the figure includes an oscillator (OSC) 300 that generates a reference signal fr having a stable frequency, a phase comparator (PD) 302 that compares the phase and frequency of the reference signal fr and the feedback signal, and a phase comparison. The charge pump (CP) 304 whose output voltage changes according to the comparison result by the device 302, the low-pass filter (LPF) 306 that removes high-frequency components from the output of the charge pump 304, and the oscillation according to the output voltage of the low-pass filter 306 A voltage controlled oscillator (VCO) 308 whose frequency is controlled and a frequency divider 310 that performs a frequency dividing operation with an arbitrary frequency dividing ratio N (N is an integer) with respect to the output of the voltage controlled oscillator 308. It is configured.
[0031]
The oscillator 300 amplifies a minute vibration generated in, for example, a crystal resonator and generates a 9 kHz reference signal fr. Further, the frequency divider 310 is configured by a programmable counter in which the frequency division ratio N can be arbitrarily set by, for example, external data input, and can continuously change the frequency division ratio N by one. Therefore, when the frequency division ratio N of the frequency divider 310 is changed, the voltage-controlled oscillator 308 outputs stepped reference frequency signals at 9 kHz intervals. If a voltage-controlled oscillator is used as the oscillator 300, the tuning frequency can be changed.
[0032]
The tuning detection circuit 4 performs PLL control and outputs a signal (detection signal) indicating whether or not the tuning frequency of the tuning circuit 1 is stabilized. This detection signal is the tuning circuit 1, the PLL control circuit 3, and the input switching. Input to the circuit 5. Specifically, the tuning detection circuit 4 determines whether or not a desired tuning frequency has been set in the tuning circuit 1 by comparing the phases of the two outputs of the phase comparator 32. For example, if the phases of the two outputs of the phase comparator 32 match, it is determined that a desired tuning frequency has been set, and the signal level of the detection signal is set to a high level.
[0033]
Next, the operation of the tuning mechanism shown in FIG. 1 will be described. Immediately after starting the tuning mechanism or immediately after switching the tuning frequency, since the desired tuning frequency is not set in the tuning circuit 1, the detection signal output from the tuning detection circuit 4 is at a low level, for example. This detection signal is input to the tuning circuit 1 and the input switching circuit 5. The input switching circuit 5 blocks the input signal to the tuning circuit 1, and the tuning circuit 1 sets the loop gain of the feedback loop to 1 or more. . The phase comparator 32 in the PLL control circuit 3 compares the phase and frequency of the output signal of the tuning circuit 1 and the output signal of the oscillator 31, and sends a control signal corresponding to the comparison result via the charge pump 33 and the low-pass filter 34. To the frequency control circuit 2. When the detection signal from the tuning detection circuit 4 is at a low level, the frequency control circuit 2 supplies a control signal corresponding to the output of the PLL control circuit 3 to the tuning circuit 1.
[0034]
As described above, the tuning circuit 1 oscillates at the same frequency as the reference frequency signal output from the oscillator 31. Since the oscillation condition for the tuning circuit 1 to oscillate and the tuning condition for the tuning operation are basically the same, the oscillation frequency when the tuning circuit 1 oscillates stably is the tuning frequency. Be the same.
[0035]
When the tuning circuit 1 oscillates stably at a desired frequency, the signal level of the detection signal output from the tuning detection circuit 4 is inverted and becomes, for example, a high level. As a result, the PLL control circuit 3 outputs a signal at a constant level, and the frequency control circuit 2 supplies the tuning circuit 1 with a control signal corresponding to the phase difference between the input and output signals of the tuning circuit 1. The input switching circuit 5 inputs an external input signal to the tuning circuit 1, and the loop gain of the feedback loop in the tuning circuit 1 is set to be less than 1, for example. As a result, the phase difference between the input and output signals of the tuning circuit 1 is eliminated, that is, the tuning frequency is controlled so as to always follow the frequency of the input signal.
[0036]
[B. Detailed configuration and operation of tuning circuit]
FIG. 2 is a circuit diagram showing a detailed configuration of the tuning circuit 1 shown in FIG. The tuning circuit 1 shown in the figure includes two phase shift circuits 110C and 130C, a voltage dividing circuit 160 including resistors 162 and 164 provided on the output side of the subsequent phase shift circuit 130C, a feedback resistor 170, and an input resistor. 174.
[0037]
Note that the input switching circuit 5 connected to the input side of the tuning circuit 1 is composed of, for example, an analog switch, and whether or not an external input signal is input to the tuning circuit 1 is detected by the detection signal from the tuning detection circuit 4. Switch accordingly.
[0038]
FIG. 3 is a circuit diagram showing the configuration of the preceding phase shift circuit 110C shown in FIG. The phase shift circuit 110C shown in the figure includes an operational amplifier 112, which is a kind of differential amplifier, and a variable resistor that shifts the phase of the AC signal input to the input terminal 122 by a predetermined amount and inputs it to the non-inverting input terminal of the operational amplifier 112. 116 and the capacitor 114, a resistor 118 inserted between the input terminal 122 and the inverting input terminal of the operational amplifier 112, resistors 121 and 123 connected to the output terminal of the operational amplifier 112 to form a voltage dividing circuit, The resistor 120 is connected between the output terminal of the voltage circuit and the inverting input terminal of the operational amplifier 112. The resistance value of the variable resistor 116 can be changed according to a control voltage from the outside. For example, the variable resistor 116 is formed using a channel resistance of an FET, and a control voltage supplied from the outside via the control terminal 194 shown in FIG. The resistance value is set by applying to the gate.
[0039]
Here, it is assumed that the resistance values of the resistor 118 and the resistor 120 are equal, the voltage across the variable resistor 116 is VR1, the voltage across the capacitor 114 and the resistors 118, 120 is VC1, the input voltage is Ei, and the output voltage is Eo. Then, the relationship between the magnitude of the input / output voltage and the phase is represented by the vector diagram of FIG. 4, the amplitude of the output signal is the same as the amplitude of the input signal regardless of the frequency, and the phase shift amount is φ1 shown in FIG. It is represented by
[0040]
FIG. 5 shows the configuration of the latter-stage phase shift circuit 130C shown in FIG. The phase shift circuit 130C shown in the figure includes an operational amplifier 132, which is a kind of differential amplifier, and a resistor 136 that shifts the phase of the AC signal input to the input terminal 142 by a predetermined amount and inputs the phase to the non-inverting input terminal of the operational amplifier 132. And a capacitor 134, a resistor 138 inserted between the input terminal 142 and the inverting input terminal of the operational amplifier 132, resistors 141 and 143 connected to the output terminal of the operational amplifier 132 to form a voltage dividing circuit, and this voltage division The resistor 140 is connected between the output terminal of the circuit and the inverting input terminal of the operational amplifier 132. The basic configuration of the phase shift circuit 130C is the same as that of the previous phase shift circuit 110C, and the connection order of the capacitor 134 and the resistor 136 constituting the CR circuit in the phase shift circuit 130C is the same as that of the CR in the phase shift circuit 110C. This is opposite to the connection order of the capacitor 114 and the variable resistor 116 constituting the circuit.
[0041]
Therefore, when the voltage across the capacitor 134 is VC2 and the voltage across the resistor 136 is VR2, the relationship between the magnitude of the input / output voltage and the phase is represented by the vector diagram of FIG. 6, and the amplitude of the output signal is input regardless of the frequency. It is the same as the amplitude of the signal, and the phase shift amount is represented by φ2 shown in FIG.
[0042]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 110C and 130C, and the total phase shift amount of the two phase shift circuits 110C and 130C is 360 ° at the predetermined frequency.
[0043]
Further, as shown in FIG. 2, a voltage dividing circuit 160 is connected to the output side of the subsequent phase shift circuit 130 </ b> C, and a variable resistor 166 is connected in parallel to the resistor 164 constituting the voltage dividing circuit 160. The variable resistor 166 is formed of, for example, a channel resistance of an FET, and a detection signal from the tuning detection circuit 4 shown in FIG. 1 is input to the gate terminal of the FET.
[0044]
For example, when the detection signal from the tuning detection circuit 4 becomes high level, the resistance value of the variable resistor 166 decreases and the loop gain of the feedback loop decreases and is set to less than 1. In this state, the input switching circuit 5 is switched and an input signal is input to the tuning circuit 1, and the tuning circuit 1 shown in FIG. 2 has a frequency at which the sum of the phase shift amounts by the two phase shift circuits 110C and 130C is 360 °. Performs a tuning operation to extract only the components.
[0045]
On the other hand, when the detection signal from the tuning detection circuit 4 is at a low level, the resistance value of the variable resistor 166 increases and the loop gain of the feedback loop increases to 1 or more. In this state, the input switching circuit 5 is switched, the signal input to the input terminal 190 is cut off, and the tuning circuit 1 is at a frequency at which the total phase shift amount of the two phase shift circuits 110C and 130C is 360 °. Oscillates.
[0046]
Thus, the tuning mechanism shown in FIG. 1 oscillates the tuning circuit 1 by setting the loop gain of the feedback loop of the tuning circuit 1 to 1 or more until the desired tuning frequency is stably set in the tuning circuit 1. Since the PLL control is performed in the state where it is set, the frequency can be set quickly and accurately.
[0047]
In addition, after a desired tuning frequency is set in the tuning circuit 1, the tuning circuit 1 can perform a predetermined tuning operation by setting the loop gain of the feedback loop to less than 1.
[0048]
Further, the tuning circuit 1 shown in FIG. 2 includes a voltage dividing circuit 160 on the output side of the subsequent phase shift circuit 130C. In order to take out the input voltage to the voltage dividing circuit 160 as a tuning output, the tuning circuit 1 itself Can have a gain, and the signal amplitude can be amplified simultaneously with the tuning operation.
[0049]
In the tuning circuit 1 shown in FIG. 2, the variable resistor 116 is provided in the preceding phase shift circuit 110C to change the time constant of the CR circuit. However, the time constant of the CR circuit in the phase shift circuit 110C is changed. Instead of changing, the time constant of the CR circuit in the subsequent phase shift circuit 130C may be changed. In this case, the resistor 136 in the phase shift circuit 130C may be formed using the FET channel resistance or the like.
[0050]
[C. Detailed configuration and operation of frequency control circuit]
Next, details of the frequency control circuit 2 shown in FIG. 1 will be described. FIG. 7 is a circuit diagram showing a specific configuration of the synchronous rectifier circuit 21, the pulse conversion circuit 23, the polarity determination circuit 24, and the voltage synthesis circuit 25 that constitute the frequency control circuit 2.
[0051]
The synchronous rectifier circuit 21 shown in the figure includes an analog switch (AS) 30, a voltage comparator 32, and a level shifter (LS) 34.
[0052]
The output signal of the tuning circuit 1 is input to one input terminal (for example, an inverting input terminal) of the voltage comparator 32, and the other input terminal (for example, a non-inverting input terminal) is grounded. The voltage comparator 32 includes two output terminals that output signals inverted from each other. One output terminal is connected to the level shifter 34 and the other output terminal is connected to a polarity determination circuit 24 described later.
[0053]
The level shifter 34 inverts the polarity of the signal output from the voltage comparator 32 and performs level shift, and outputs a rectangular wave having positive and negative voltage levels as a reference signal.
[0054]
The analog switch 30 operates in synchronization with the reference signal output from the level shifter 34, and passes or blocks the input signal of the tuning circuit 1 input in parallel with the reference signal at a predetermined timing.
[0055]
The synchronous rectifier circuit 21 may be configured by omitting the level shifter 34 inserted between the voltage comparator 32 and the analog switch 30.
[0056]
The pulse conversion circuit 23 includes a voltage comparator 50 and a voltage dividing circuit composed of resistors 52 and 54. The output signal of the analog switch 30 in the synchronous rectifier circuit 21 is input to one input terminal (for example, non-inverting input terminal) of the voltage comparator 50, and the voltage dividing circuit is connected to the other input terminal (for example, inverting input terminal). A partial pressure output is input. By setting the resistance value of the resistor 54 constituting the voltage dividing circuit to a value larger than the resistance value of the resistor 52 (for example, about 100 times), the voltage at the inverting input terminal of the voltage comparator 50 is slightly lower than 0V. Is set.
[0057]
The voltage comparator 50 compares the potentials at both input terminals, and outputs two types of pulse trains having different polarities indicating the comparison result. One pulse train is input to the voltage synthesis circuit 25, and the other pulse train is input to the polarity determination circuit 24.
[0058]
The polarity determination circuit 24 includes two inverter circuits 60 and 61 and two D-type flip-flops 62 and 63, and these two inverter circuits 60 and 61 function as a delay circuit. Signals that differ only in level at the same timing as the reference signal of the synchronous rectifier circuit 21 are input to the D input terminal of the D-type flip-flop 62 in the polarity determination circuit 24. The signal input to the D input terminal is latched in synchronization with the rising edge of the pulse train output from the pulse conversion circuit 23 and input to the D input terminal of the D-type flip-flop 63 at the next stage. As a result, the D-type flip-flop 63 in the next stage outputs an H or L level voltage indicating the phase direction based on the pulse train output from the voltage comparator 50 in the pulse conversion circuit 23.
[0059]
The voltage synthesis circuit 25 includes two tri-state buffers 700 and 702, a differential amplifier, and a variable bias circuit, and the differential amplifier includes an operational amplifier 704.
[0060]
One tri-state buffer 700 has an input terminal connected to the inverting output terminal of the voltage comparator 50 in the pulse conversion circuit 23, and an output terminal connected to the inverting input terminal of the operational amplifier 704 via the resistor 710. . An AND gate 721 is connected to the control terminal of the tri-state buffer 700, the output terminal Q of the flip-flop 63 in the subsequent stage in the polarity discrimination circuit 24 is connected to one input terminal of the AND gate 721, and the other input terminal is connected to the other input terminal. The output terminals of the tuning detection circuit 4 are connected to each other. Therefore, when the output of the tuning detection circuit 4 is at a low level, that is, when a desired tuning frequency is not set in the tuning circuit 1, the output of the tristate buffer 700 becomes high impedance. On the other hand, when the output of the tuning detection circuit 4 is at a high level, the output of the tristate buffer 700 operates according to the signal logic of the output terminal Q of the flip-flop 63.
[0061]
Similarly, the other tri-state buffer 702 has an input terminal connected to the inverting output terminal of the voltage comparator 50 in the pulse conversion circuit 23, and an output terminal connected to the non-inverting input terminal of the operational amplifier 704 via the resistor 708. It is connected. An AND gate 722 is connected to the control terminal of the tri-state buffer 702. One of the input terminals of the AND gate 722 is connected to the inverting output terminal of the flip-flop 63 in the subsequent stage in the polarity discrimination circuit 24, and the other input terminal is connected to the control terminal. The output terminals of the tuning detection circuit 4 are connected to each other. Therefore, when the output of the tuning detection circuit 4 is low level, the output of the tristate buffer 702 becomes high impedance, and when the output of the tuning detection circuit 4 is high level, the output of the tristate buffer 702 is the flip-flop 63. It operates according to the signal logic of the inverting output terminal.
[0062]
The operational amplifier 704 inputs the outputs of the above-described two tristate buffers 700 and 702 to each input terminal, amplifies the difference between them with a predetermined amplification degree, performs a predetermined smoothing operation, and removes high frequency components, Generate a control signal. Further, the non-inverting input terminal and the inverting input terminal of the operational amplifier 704 are connected to the output terminal of the PLL control circuit 3 via resistors 724 and 725, respectively. As described above, when the desired tuning frequency is not set in the tuning circuit 1, the operational amplifier 704 outputs a control signal corresponding to the output of the PLL control circuit 3, and the desired tuning frequency is set in the tuning circuit 1. Thereafter, the operational amplifier 704 outputs a control signal corresponding to the output of the polarity discrimination circuit 24.
[0063]
In addition to the operational amplifier 704, the differential amplifier described above includes a feedback resistor 712 inserted between the inverting input terminal and the output terminal of the operational amplifier 704, a capacitor 714 connected in parallel to the feedback resistor 712, and a tri-state buffer 702. In order to perform adjustment between two inputs of the operational amplifier 704 by dividing the voltage level of the signal output from the resistor 716, a resistor 716 inserted between the non-inverting input terminal of the operational amplifier 704 and the ground, and the resistor 716 are connected in parallel. And the capacitor 720 inserted between the inverting input terminal of the operational amplifier 704 and the ground. The output terminal of the PLL control circuit 3 is connected to the non-inverting input terminal of the operational amplifier 704 via a resistor.
[0064]
For example, when the output of the tuning detection circuit 4 is at a low level, that is, when the desired tuning frequency is not set in the tuning circuit 1, the operational amplifier 704 outputs a signal corresponding to the output of the PLL control circuit 3, and PLL control is performed on the circuit 1. On the other hand, when the output of the tuning circuit 1 becomes high level, the PLL control circuit 3 outputs a signal of a constant level, and the operational amplifier 704 operates according to the logic of the flip-flop 63. Thus, the tuning circuit 1 performs control so that the tuning frequency matches the frequency of the input signal.
[0065]
Next, operations of the frequency control circuit 2 and the tuning circuit 1 after a desired tuning frequency is set in the tuning circuit 1 will be described with reference to timing diagrams.
[0066]
[C-1. (When the tuning frequency is higher than the frequency of the input signal)
FIG. 8 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal input to the tuning circuit 1, and the input / output timing of each component in the frequency control circuit 2 is shown. Yes. FIGS. 9A to 9N correspond to reference signs A to N shown in the circuit diagram of FIG. In addition, the hatched areas included in the diagrams (I) to (N) correspond to the uncertain portions, and actually waveforms that are input / output at timings prior to the input / output waveforms of the respective components shown in the diagram. The state is determined according to the state.
[0067]
When the tuning frequency is higher than the frequency of the input signal of the tuning circuit 1, the sum of the phase shift amounts of the two phase shift circuits 110C and 130C is smaller than 360 °. When the two signals input and output to are observed, the phase relationship as shown in FIGS. 8A and 8B is obtained.
[0068]
The voltage comparator 32 in the synchronous rectifier circuit 21 outputs an H level signal when the voltage level of the output signal of the tuning circuit 1 is lower than 0V, and an L level signal when higher than 0V. Therefore, as shown in FIG. 8C, the voltage comparator 32 has the same frequency and phase as the tuning output, and when the voltage level of the tuning output is positive, the voltage level of the tuning output is reversed. A rectangular wave that is at H level is output when is negative.
[0069]
In addition to the above-described output, the voltage comparator 32 outputs a signal obtained by inverting the logic from the inverting output terminal, and FIG. 8D shows the waveform.
[0070]
The level shifter 34 inverts the logic with respect to the output of the voltage comparator 32 shown in FIG. 8C, so that the positive and negative voltage states having the same absolute value are obtained as shown in FIG. The rectangular wave which has is output.
[0071]
The analog switch 30 performs an on / off operation of the switch according to the voltage level of the rectangular wave output from the level shifter 34. When the tuning frequency of the tuning circuit 1 is higher than the frequency of the input signal, as shown in FIG. 8 (F), the waveform slightly shifted forward from the complete half-wave rectified waveform, that is, the tuning output The waveform extracted at a timing slightly earlier than the timing at which the upper half is extracted is output from the analog switch 30.
[0072]
The voltage comparator 50 becomes L level only when the voltage level of the output of the analog switch 30 becomes lower than 0V, and outputs an H level pulse train otherwise. Therefore, when the synchronous rectification output output from the analog switch 30 is slightly shifted forward from the half-wave rectified waveform, as shown in FIG. 8G, the voltage comparison is performed at a timing corresponding to this forward shift. The output of the device 50 becomes L level.
[0073]
In addition to the output described above, the voltage comparator 50 outputs a signal obtained by inverting the logic from the inverting output terminal, and FIG. 8 (H) shows the waveform.
[0074]
The flip-flop 62 in the preceding stage in the polarity discrimination circuit 24 is the timing at which the output of the voltage comparator 50 rises from the L level to the H level (exactly, the output of the voltage comparator 50 is passed through the two inverter circuits 60 and 61). At the timing when the subsequent signal rises), the logic of the signal output from the inverting output terminal of the voltage comparator 32 in the synchronous rectifier circuit 21 is captured and held. As shown in FIGS. 8G and 8D, when the signal output from the voltage comparator 50 rises, the signal output from the inverting output terminal of the voltage comparator 32 is at the H level. As shown in FIG. 8I, this logic H is held by the flip-flop 62 in the previous stage.
[0075]
Further, the subsequent flip-flop 63 captures and holds the output of the previous flip-flop 62 at the timing when the output of the voltage comparator 50 next rises from the L level to the H level, and outputs it as shown in FIG. A logic H signal is output from the terminal Q. As shown in FIG. 8K, a logic L signal obtained by inverting the logic H is output from the inverting output terminal of the flip-flop 63.
[0076]
As described above, when the tuning frequency is higher than the frequency of the input signal of the tuning circuit 1, a logic H signal is output from the output terminal Q of the flip-flop 63 in the subsequent stage, and a logic L signal is output from the inverting output terminal. Is output, the tri-state buffer 700 operates as a buffer, and the output of the tri-state buffer 702 becomes high impedance.
[0077]
Since the output terminal of the tristate buffer 702 is grounded via the resistors 708 and 716, the potential of this output terminal is 0 V as shown in FIG.
[0078]
By the way, in the tristate buffer 700, the inverting output terminal of the voltage comparator 50 is connected to the input terminal, and the inverting input terminal of the operational amplifier 704 is connected to the output terminal via the resistor 710. Therefore, when a logic H signal is input to the control terminal and the tri-state buffer 700 operates as a simple buffer, a signal output from the inverting output terminal of the voltage comparator 50 is input to the inverting input terminal of the operational amplifier 704 via the resistor 710. Is input.
[0079]
In this way, when a positive pulse is input to the inverting input terminal of the operational amplifier 704, the voltage at the output terminal of the operational amplifier 704 decreases corresponding to this pulse input. Actually, a capacitor 720 is connected between the inverting input terminal of the operational amplifier 704 and the ground, and a capacitor 714 is connected between the output terminal and the inverting input terminal of the operational amplifier 704, so that the output voltage is smoothed. Therefore, as shown in FIG. 8 (N), the differential amplifier including the operational amplifier 704 has a gentle output voltage, that is, a control voltage corresponding to the pulse width of the signal input via the tristate buffer 700. To drop.
[0080]
In this way, the control voltage fed back to the tuning circuit 1 is lowered, and the tuning frequency of the tuning circuit 1 is changed to the lower side. Such control is repeated until there is no deviation between the frequency of the input signal of the tuning circuit 1 and the tuning frequency, and the tuning frequency matches the frequency of the input signal after a predetermined time has elapsed.
[0081]
[C-2. (When the tuning frequency is lower than the frequency of the input signal)
FIG. 9 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal input to the tuning circuit 1, and the input / output timing of each component in the frequency control circuit 2 is shown. Similarly to FIG. 8, FIGS. 9A to 9N correspond to reference signs A to N shown in the circuit diagram of FIG.
[0082]
When the tuning frequency is lower than the frequency of the input signal of the tuning circuit 1, the total phase shift amount of the two phase shift circuits 110C and 130C is larger than 360 °. When the two signals input and output to are observed, the phase relationship as shown in FIGS. 9A and 9B is obtained.
[0083]
The voltage comparator 32 in the synchronous rectifier circuit 21 outputs a signal (FIG. 9C) synchronized with the tuning output of the tuning circuit 1, and the level shifter 34 inverts and amplifies this signal and simultaneously performs a predetermined level shift (FIG. 9C). FIG. 9 (E)). Since the analog switch 30 passes the input signal of the tuning circuit 1 only when the voltage level of the output signal of the level shifter 34 is positive, the output waveform shown in FIG.
[0084]
Therefore, the voltage comparator 50 in the pulse conversion circuit 23 generates a pulse train having a predetermined positive voltage at 0 V when the voltage level is negative in the output waveform shown in FIG. 9F and at other timings. Is output (FIG. 9G).
[0085]
Incidentally, the flip-flop 62 in the polarity discriminating circuit 24 takes in the signal (FIG. 9D) output from the inverting output terminal of the voltage comparator 32 in the synchronous rectifier circuit 21 in synchronization with the rise of this pulse train. However, since the rising timing of the rectangular wave described above and the falling timing of the output of the voltage comparator 32 shown in FIG. 9D are almost the same, the input data of the flip-flop 62 remains as it is. There is a risk of fetching data before it is confirmed. The inverter circuits 60 and 61 are delay circuits inserted in order to avoid such inconveniences, and delaying the data capture timing by a predetermined time prevents the data from being captured before the input data is determined. ing.
[0086]
In the configuration shown in FIG. 7, the delay circuit is configured by using the two inverter circuits 60 and 61. However, the delay circuit is realized when four or more inverter circuits or a plurality of buffers that do not invert the logic are used. Various methods can be considered.
[0087]
In this way, each of the two flip-flops 62 and 63 in the polarity discrimination circuit 24 has a 0V portion (corresponding to logic L) of the signal output from the inverting output terminal of the voltage comparator 32 in the synchronous rectification circuit 21. ), The logic L and logic H signals are output from the output terminal Q of the flip-flop 63 and its inverted output terminal, respectively, as shown in FIGS.
[0088]
Each output signal of the flip-flop 63 has an opposite logic state as compared with the case shown in FIG. 8, that is, when the tuning frequency is higher than the frequency of the input signal. Only the tri-state buffer 702 operates as a buffer (FIGS. 9L and 9M). Therefore, a positive pulse having a predetermined pulse width is input to the non-inverting input terminal of the differential amplifier including the operational amplifier 704, and a control voltage output from the differential amplifier toward the tuning circuit 1 is obtained. It gradually rises (FIG. 9 (N)), and the tuning frequency of the tuning circuit 1 is changed to a higher one. Such control is repeated until there is no difference between the frequency of the input signal of the tuning circuit 1 and the tuning frequency, and the tuning frequency matches the frequency of the input signal after a predetermined time has elapsed.
[0089]
As described above, the frequency control circuit 2 shown in detail in FIG. 7 performs control so that the phase difference between the input and output signals of the tuning circuit 1 is eliminated, so that the tuning frequency always follows and matches the frequency of the input signal. It becomes like this. Therefore, for example, when used in a superheterodyne receiver, the tuning frequency can be easily matched with the frequency of a carrier such as an input broadcast wave.
[0090]
Further, when the tuning frequency is controlled by the frequency control circuit 2, the loop gain of the feedback loop in the tuning circuit 1 is controlled so as to be less than 1, so that the tuning circuit 1 does not oscillate, and stable tuning is achieved. Operation is performed.
[0091]
In addition, the tuning circuit 1 and the frequency control circuit 2 that realize the tuning mechanism of the present embodiment are configured by various digital circuits such as flip-flops, operational amplifiers, capacitors, and resistors, and all elements are formed on a semiconductor substrate. Therefore, the entire tuning mechanism or the entire tuning mechanism and its peripheral circuit can be integrated on the semiconductor substrate.
[0092]
In particular, when the entire tuning mechanism is integrated, it is conceivable that the circuit constant varies greatly for each manufactured chip and the frequency characteristics are not constant. Even in such a case, the tuning of the present embodiment is also possible. According to the mechanism, the tuning frequency of the tuning circuit 1 changes so as to follow the input signal having a predetermined frequency after the frequency setting by the PLL control at the time of setting the tuning frequency. There is no effect, and stable characteristics are always obtained.
[0093]
In addition, when the entire tuning mechanism is integrated, various element constants such as resistance may change as the temperature changes during use. However, in the tuning control method of this embodiment, the frequency of the input signal is always maintained. Therefore, even if various element constants change, appropriate feedback is applied, and fluctuations in the tuning frequency can be suppressed.
[0094]
Although the voltage synthesis circuit 25 in the frequency control circuit 2 shown in FIG. 7 includes a tristate buffer, it uses elements other than the tristate buffer, for example, logic elements such as NOR gates and analog switches. It can also be configured.
[0095]
[Second Embodiment]
FIG. 10 is a circuit diagram showing the configuration of the second embodiment of the tuning mechanism. The tuning mechanism shown in the figure includes a tuning circuit 1, a tuning detection circuit 4, a synchronous rectification circuit 21, a pulse conversion circuit 23, and a polarity determination circuit 24 having the same configuration as in FIG. 7.
[0096]
The tristate buffers 700 and 702 are connected to the output terminal of the voltage comparator 50 in the pulse conversion circuit 23 as in FIG. 7, and the tristate buffers 801 and 802 are further connected to the tristate buffers 700 and 702, respectively. Has been. These tristate buffers 801 and 802 are controlled by a detection signal from the tuning detection circuit 4. In addition, pull-down resistors 803 and 804 are connected to output terminals of the tri-state buffers 700 and 702, respectively.
[0097]
On the other hand, the PLL control circuit 3 includes tristate buffers 35 and 36 in addition to the oscillator 31, the phase comparator 32, the charge pump 33, and the low pass filter 34. The tristate buffers 35 and 36 are similarly controlled by a detection signal from the tuning detection circuit 4.
[0098]
The outputs of the tristate buffers 35 and 801 are connected to each other and input to one input terminal of the charge pump 33. Similarly, the outputs of the tristate buffers 36 and 802 are connected to each other and input to the other input terminal of the charge pump 33. Is done.
[0099]
The phase comparator 32 includes two output terminals X and Y, and pulse signals having different phases are output from the output terminals X and Y, respectively. For example, when the frequency of the output signal of the tuning circuit 1 is equal to the frequency of the signal output from the oscillator 31, pulses having the same period and pulse width are alternately output from the two output terminals X and Y of the phase comparator 32. The charge amount and the discharge amount with respect to the capacitor built in the charge pump 33 become equal, and the average level of the output voltage of the charge pump 33 is maintained at a predetermined value. On the other hand, when the frequencies of the two inputs of the phase comparator 32 are different, a difference occurs in the pulse width of the pulse train output from each of the two output terminals X and Y of the phase comparator 32, so that the charge pump 33 The charge / discharge balance with respect to the built-in capacitor is lost, resulting in an excessive charge or excessive discharge state, and the average level of the output voltage of the charge pump 33 changes in one direction.
[0100]
On the other hand, the tri-state buffers 700 and 702 operate in accordance with the logic of the output terminal of the subsequent flip-flop 63 in the polarity determination circuit 24. When a pulse is output from one tri-state buffer, the other tri-state buffer The output of the buffer is in a high impedance state. That is, a pulse is output only from one of the tristate buffers according to the phase shift direction of the input / output signal of the tuning circuit 1.
[0101]
Thus, since the functionally equal signal is output from the phase comparator 32 and the tristate buffers 700 and 702, the tuning mechanism shown in FIG. The output of 702 is input to the charge pump 33 via the tristate buffers 35, 36, 800, and 801, thereby simplifying the circuit.
[0102]
Next, the operation of the tuning mechanism shown in FIG. 10 will be described. Immediately after starting the tuning mechanism or immediately after switching the tuning frequency, the detection signal output from the tuning detection circuit 4 becomes low level, the outputs of the tristate buffers 801 and 802 become high impedance, and the tristate. The buffers 35 and 36 operate as buffers, and the output of the phase comparator 32 is supplied to the charge pump 33 via the tristate buffers 35 and 36. The output of the charge pump 33 is fed back to the tuning circuit 1 through the low pass filter 34. At this time, the loop gain of the feedback loop in the tuning circuit 1 is set to 1 or more by the detection signal from the tuning detection circuit 4, so that the tuning circuit 1 oscillates at a desired oscillation frequency. Is controlled by PLL.
[0103]
When the tuning circuit 1 oscillates stably at a desired frequency, the output of the tuning detection circuit 4 is inverted and becomes high level, the outputs of the tristate buffers 35 and 36 become high impedance, and the tristate buffer. Reference numerals 801 and 802 operate as buffers. Therefore, the output of the pulse conversion circuit 23 is fed back to the tuning circuit 1 via the charge pump 33 and the low pass filter 34. Further, the input switching circuit 5 is switched to input an input signal to the tuning circuit 1, and the tuning circuit 1 performs a tuning operation for extracting only a predetermined frequency component included in the input signal.
[0104]
In the circuit diagram shown in FIG. 10, instead of providing the tristate buffers 801 and 802, as in FIG. 7, AND gates are connected to the control terminals of the tristate buffers 700 and 702, and the tuning detection circuit 4 The outputs of the tristate buffers 700 and 702 may be switched according to the output.
[0105]
[First Modification of Tuning Circuit]
In the tuning circuit 1 shown in FIG. 2, the phase shift circuits 110C and 130C including a CR circuit are connected in cascade, but the CR circuit can be replaced with an LR circuit.
[0106]
A phase shift circuit 110L illustrated in FIG. 11 has a configuration in which the CR circuit including the capacitor 114 and the variable resistor 116 in the phase shift circuit 110C illustrated in FIG. 2 is replaced with an LR circuit including the variable resistor 116 and the inductor 117. ing. 12 has a configuration in which the CR circuit including the capacitor 134 and the resistor 136 in the phase shift circuit 130C illustrated in FIG. 2 is replaced with an LR circuit including the resistor 136 and the inductor 137. ing.
[0107]
11 is equivalent to the previous phase shift circuit 110C shown in FIG. 2, and the phase shift circuit 130L shown in FIG. 12 is equivalent to the subsequent phase shift circuit 130C shown in FIG. At least one of the two phase shift circuits 110C and 130C shown in FIG. 2 can be replaced with the phase shift circuits 110L and 130L shown in FIG.
[0108]
By the way, when the phase shift circuit 110C is included in the tuning circuit 1 and when the phase shift circuit 110L is included, the control direction of the tuning frequency is opposite, so the phase shift circuit 110C is simply replaced with the phase shift circuit 110L. Simply tuning does not stabilize the tuning frequency. Therefore, when the phase shift circuit 110C is replaced with the phase shift circuit 110L, the connection between the input terminals A and B of the phase comparator 32 and the tuning circuit 1 and the oscillator 31 shown in FIG. It is necessary to reverse the connection between the output terminals X and Y of the charger 32 and the charge pump 33.
[0109]
[Second Modification of Tuning Circuit]
FIG. 13 is a circuit diagram showing a second modification of the tuning circuit. The preceding phase shift circuit 210C included in the tuning circuit 1A shown in the figure does not include a voltage dividing circuit inside, but sets the resistance value of the resistor 120 'larger than the resistance value of the resistor 118'. The gain of the phase shift circuit 210C is made larger than unity.
[0110]
Similarly, the phase-shift circuit 230C in the subsequent stage does not include a voltage dividing circuit inside, but the gain of the phase-shift circuit 230C is set by setting the resistance value of the resistor 140 ′ larger than the resistance value of the resistor 138 ′. Is larger than 1.
[0111]
The resistors 119 and 139 are provided to suppress fluctuations in gain of the phase shift circuits 210C and 230C, and the resistance value R of the resistors 119 and 139 satisfies the relationship of R = mr / (m−1). It is desirable to set. Here, r is the resistance value of the resistors 118 'and 138', and mr is the resistance value of the resistors 120 'and 140'. Note that one end of each of the resistors 119 and 139 may be connected to a fixed potential other than the ground level.
[0112]
Although the tuning circuit 1A shown in FIG. 13 shows an example in which a CR circuit is included in the phase shift circuit, the CR circuit can be replaced with an LR circuit. For example, the phase shift circuit 210L shown in FIG. 14 is equivalent to the previous phase shift circuit 210C shown in FIG. 13, and can be replaced with the phase shift circuit 210C. Similarly, the phase shift circuit 230L shown in FIG. 15 is equivalent to the subsequent phase shift circuit 230C shown in FIG. 13, and can be replaced with the phase shift circuit 130C.
[0113]
[Third Modification of Tuning Circuit]
FIG. 16 is a circuit diagram showing a third modification of the tuning circuit. The basic configuration of the tuning circuit 1B shown in FIG. 2 is the same as that of the tuning circuit 1 shown in FIG. 2, and is shown in FIG. 2 in that a follower circuit 50 including a transistor is inserted further before the phase shift circuit 110C of the previous stage. This is different from the tuning circuit 1. Note that the follower circuit 50 shown in FIG. 16 is configured by a so-called source follower circuit, but may be configured by an emitter follower circuit.
[0114]
As described above, if a transistor follower circuit is cascade-connected to the previous stage such as the phase shift circuit 110C of the previous stage, the resistance values of the feedback resistor 170 and the input resistor 174 are compared with those of the tuning circuit 1 shown in FIG. Can be bigger. In particular, when the entire tuning circuit is integrated on a semiconductor substrate, if the resistance value of the feedback resistor 170 or the like is to be reduced, the area occupied by the element must be increased. desirable. Therefore, in the case of integration, it is effective to connect a follower circuit 50 as shown in FIG.
[0115]
[Fourth Modification of Tuning Circuit]
FIG. 17 is a circuit diagram showing a fourth modification of the tuning circuit. The tuning circuit 1C shown in the figure has a configuration in which the phase shift circuit 310C shown in FIG. 2 is configured by removing the resistors 121 and 123, and the phase shift circuit 130C is configured by removing the resistors 141 and 143. The phase shift circuit 330C and the non-inverting circuit 150 are connected in cascade.
[0116]
The non-inverting circuit 150 includes an operational amplifier 152 and resistors 154 and 156, and has a predetermined gain corresponding to the resistance ratio of the two resistors 154 and 156. Therefore, the loss when the feedback loop is formed can be compensated by this gain, and the loop gain of the feedback loop can be easily set to 1 or more. Further, the non-inverting circuit 150 can have a function as a power amplification stage.
[0117]
Note that the non-inverting circuit 150 shown in FIG. 17 can also be connected to a part of the feedback loop of the tuning circuit 1A shown in FIG.
[0118]
[Fifth Modification of Tuning Circuit]
FIG. 18 is a circuit diagram showing a fifth modification of the tuning circuit. The tuning circuit 1D shown in the figure has a phase shift circuit 310C ′ connected in place of the subsequent phase shift circuit 330C shown in FIG. 17, and a phase inversion circuit 180 connected in place of the non-inversion circuit 150. The phase shift circuit 310C ′ has the same configuration as the phase shift circuit 310C in the previous stage except that a resistor 115 having a fixed resistance value is connected instead of the variable resistor 116.
[0119]
Since the signal is inverted by the phase inversion circuit 180, the phase shift amount in the entire feedback loop is 360 ° at the frequency at which the phase shift amount of the two phase shift circuits 310C and 310C ′ is 180 °. A predetermined tuning operation is performed.
[0120]
On the other hand, FIG. 19 is a circuit diagram showing a configuration of a tuning circuit 1E in which phase shift circuits 330C ′ and 330C and a phase inverting circuit 180 are cascade-connected instead of the phase shift circuits 310C and 310C ′. Similarly to the tuning circuit 1D, the tuning circuit 1E also has a total phase shift amount of the two phase shift circuits 330C ′ and 330C and the phase inverting circuit 180 of 360 ° at a predetermined frequency. Is done.
[0121]
[Sixth Modification of Tuning Circuit]
FIG. 20 is a circuit diagram showing a sixth modification of the tuning circuit. The tuning circuit 1F shown in the figure includes two phase shift circuits 410C and 430C, a non-inverting circuit 450, a voltage dividing circuit 160 connected to the output side of the non-inverting circuit 450, a feedback resistor 470, and an input resistor 474. It is comprised including. The feedback resistor 470 has a finite resistance value from 0Ω. A capacitor 472 connected in series with the feedback resistor 470 is for blocking a direct current.
[0122]
A front-stage phase shift circuit 410C shown in FIG. 20 includes an FET 412 whose gate is connected to the input terminal of the phase shift circuit 410C, a capacitor 414 and a variable resistor 416 connected in series between the source and drain of the FET 412. And a resistor 418 connected between the drain of the FET 412 and the positive power supply, and a resistor 420 connected between the source of the FET 412 and the ground. The resistor 426 in the phase shift circuit 410C is for applying an appropriate bias voltage to the FET 412. Further, at least one of the FET 412 and the later-described FET 432 may be replaced with a bipolar transistor.
[0123]
The resistance value of the variable resistor 416 can be changed in accordance with an external control voltage. For example, the variable resistor 416 is formed by using a channel resistance of an FET, and applies a control voltage supplied from the outside via a control terminal 194 to the gate. Thus, the resistance value is set.
[0124]
Here, the resistance values of the two resistors 418 and 420 connected to the source and drain of the FET 412 described above are set to be approximately equal, and focusing on the AC component of the input voltage applied to the gate, the signals having the same phase Is output from the source of the FET 412, and a signal whose phase is inverted and whose amplitude is equal to that of the signal output from the source is output from the drain of the FET 412. Let Ei be the amplitude of the AC voltage appearing at the source and drain.
[0125]
When the voltage across the variable resistor 416 is VR1, the voltage across the capacitor 414 is VC1, and the potential difference between the connection point between the capacitor 414 and the variable resistor 416 and the ground level is the output voltage Eo, these relationships are represented by the vector diagram of FIG. The amplitude of the output signal is constant regardless of the frequency, and the phase shift amount is represented by φ3 shown in FIG.
[0126]
On the other hand, a phase-shift circuit 430C in the subsequent stage shown in FIG. 20 includes an FET 432 whose gate is connected to the input terminal of the phase-shift circuit 430C, a resistor 436 and a capacitor 434 connected in series between the source and drain of the FET 432, The resistor 438 is connected between the drain of the FET 432 and the positive power supply, and the resistor 440 is connected between the source of the FET 432 and the ground. The resistor 446 in the phase shift circuit 430C is for applying an appropriate bias voltage to the FET 432, and the capacitor 448 inserted between the phase shift circuits 430C and 410C is for DC current blocking.
[0127]
The basic configuration of the phase shift circuit 430C is the same as that of the previous phase shift circuit 410C, and the connection of the CR circuit composed of the resistor 436 and the capacitor 434 is made up of the capacitor 414 and the variable resistor 416 in the previous phase shift circuit 410C. The difference is that it is the opposite of the connection of the CR circuit.
[0128]
The relationship between the output voltage Eo of the phase shift circuit 430C, the voltage VC2 across the capacitor 434 and the voltage VR2 across the resistor 436 is represented by the vector diagram of FIG. 22, and the amplitude of the output signal is constant regardless of the frequency. The shift amount is represented by φ4 shown in FIG.
[0129]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 410C and 430C, and the sum of the phase shift amounts of the two phase shift circuits combined is 360 ° at the predetermined frequency.
[0130]
The non-inverting circuit 450 includes an FET 452 in which a resistor 454 is connected between the drain and the positive power source, and a resistor 456 is connected between the source and the ground, and a base is connected to the drain of the FET 452 and a collector is connected. A transistor 458 connected to the source via a resistor 460 and a resistor 462 for applying an appropriate bias voltage to the FET 452 are configured.
[0131]
The amplification degree of the non-inverting circuit 450 is determined by the resistance values of the resistors 454, 456, and 460 described above, and by adjusting the resistance values of these resistors, the two phase shift circuits 410C, 430C shown in FIG. The loop gain of the feedback loop formed including the resistor 470 can be adjusted.
[0132]
Note that the tuning circuit 1F shown in FIG. 20 is configured so that both of the two phase shift circuits include a CR circuit, but at least one of the phase shift circuits may be replaced with a phase shift circuit including an LR circuit.
[0133]
23 and 24 are circuit diagrams showing configurations of phase shift circuits 410L and 430L including LR circuits. At least one of the two phase shift circuits 410C and 430C shown in FIG. 20 can be replaced with the phase shift circuits 410L and 430L.
[0134]
[Seventh Modification of Tuning Circuit]
FIG. 25 is a circuit diagram showing a seventh modification of the tuning circuit. The tuning circuit 1G shown in the figure includes a preceding phase shift circuit 410C shown in FIG. 20, a phase shift circuit 410C ′ in which the resistance value of the variable resistor 416 in the phase shift circuit 410C is fixed, a phase inversion circuit 480, Are connected in cascade, and the output of the phase inversion circuit 480 is fed back to the input side of the preceding phase shift circuit 410C via the resistor 470.
[0135]
Since the signal is inverted by the phase inversion circuit 480, the phase shift amount in the entire feedback loop is 360 ° at the frequency at which the phase shift amount of the two phase shift circuits 410C and 410C ′ is 180 °. A predetermined tuning operation is performed.
[0136]
FIG. 26 is a circuit diagram showing a configuration of a tuning circuit 1H in which phase-shifting circuits 430C ′ and 430C are cascade-connected instead of the phase-shifting circuit 410C and a phase inverting circuit 480 is connected at the subsequent stage. Similarly to the tuning circuit 1G, the tuning circuit 1H also has a total phase shift amount of the two phase shift circuits 430C ′ and 430C and the phase inversion circuit 480 at a predetermined frequency of 360 °, and a predetermined tuning operation at this frequency. Is done.
[0137]
[Eighth Modification of Tuning Circuit]
FIG. 27 is a circuit diagram showing an eighth modification of the tuning circuit. The tuning circuit 1J shown in the figure includes a non-inverting circuit 550 that outputs the input AC signal without changing the phase, and two phase shift circuits 510C and 530C that perform a total phase shift of 360 ° at a predetermined frequency. The feedback resistor 570 is included.
[0138]
The non-inverting circuit 550 functions as a buffer circuit, and includes, for example, an emitter follower circuit, a source follower circuit, or the like. If the element constants of each element such as the feedback resistor 570 are selected so as to minimize the loss or the like when directly connected, the tuning circuit 1J may be configured by omitting the non-inverting circuit 550. Good.
[0139]
The phase-shift circuit 510C in the previous stage shown in FIG. 27 includes a differential amplifier 512 that amplifies and outputs a differential voltage of two inputs with a predetermined amplification degree, and a differential amplifier that shifts the phase of the input AC signal by a predetermined amount. The voltage level of the capacitor 514 and the variable resistor 516 input to the non-inverting input terminal 512 and the variable resistor 516 are divided by about 1/2 without changing the phase of the input AC signal and input to the inverting input terminal of the differential amplifier 512. And resistors 518 and 520.
[0140]
The resistance value of the variable resistor 516 can be changed according to a control voltage from the outside. For example, the variable resistor 516 is formed using a channel resistance of an FET, and applies a control voltage supplied from the outside via the control terminal 194 to the gate. Thus, the resistance value is set.
[0141]
FIG. 28 is a vector diagram showing the relationship between the input / output voltage of phase shift circuit 510C shown in FIG. 27 and the voltage appearing in the capacitor and the like.
[0142]
As shown in the figure, the voltage VR1 appearing across the variable resistor 516 and the voltage VC1 appearing across the capacitor 514 are 90 degrees out of phase with each other. This corresponds to the voltage Ei. Therefore, when the amplitude of the input voltage Ei is constant and only the frequency changes, the voltage VR1 across the variable resistor 516 and the voltage VC1 across the capacitor 514 change along the circumference of the semicircle shown in FIG.
[0143]
Further, the voltage applied to the inverting input terminal (the voltage Ei / 2 across the resistor 520) is subtracted in vector from the voltage applied to the non-inverting input terminal of the differential amplifier 512 (the voltage VR1 across the variable resistor 516). The differential voltage Eo ′ becomes the differential voltage Eo ′, and the differential voltage Eo ′ amplified by a predetermined amplification becomes the differential amplifier 512 output voltage Eo.
[0144]
In addition, as apparent from FIG. 28, the voltage VC1 and the voltage VR1 intersect at right angles on the circumference, so that the phase difference between the input voltage Ei and the voltage VC1 increases as the frequency ω changes from 0 to ∞. The voltage Ei changes from 180 ° to 270 ° in the clockwise direction (phase delay direction) with reference to the voltage Ei. The phase shift amount φ5 of the entire phase shift circuit 510C changes from 180 ° to 360 ° depending on the frequency.
[0145]
On the other hand, the latter-stage phase shift circuit 530C shown in FIG. 27 differs from the differential amplifier 532 that amplifies and outputs the differential voltage of two inputs with a predetermined amplification degree by shifting the phase of the input AC signal by a predetermined amount. The voltage level of the capacitor 534 and the resistor 536 input to the non-inverting input terminal of the dynamic amplifier 532 and the voltage level of the capacitor 534 and the inverting input terminal of the differential amplifier 512 are divided without changing the phase of the input AC signal. Input resistors 538 and 540 are included.
[0146]
FIG. 29 is a vector diagram showing the relationship between the input / output voltage of phase shift circuit 530C shown in FIG. 27 and the voltage appearing at the capacitor or the like.
[0147]
As shown in the figure, the voltage VC2 appearing at both ends of the capacitor 534 and the voltage VR2 appearing at both ends of the resistor 536 are out of phase with each other by 90 °, and the sum of these voltages is the input voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VC2 of the capacitor 534 and the both-ends voltage VR2 of the resistor 536 change along the circumference of the semicircle shown in FIG.
[0148]
Also, the voltage applied to the inverting input terminal (voltage Ei / 2 across the resistor 540) subtracted in vector from the voltage applied to the non-inverting input terminal of the differential amplifier 532 (the voltage VC2 across the capacitor 534). Becomes the differential voltage Eo ′, and the differential voltage Eo ′ amplified by a predetermined amplification becomes the output voltage Eo of the differential amplifier 532.
[0149]
As is clear from FIG. 29, since the voltage VR2 and the voltage VC2 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR2 is 0 ° as the frequency ω changes from 0 to ∞. From 90 to 90 degrees. Then, the phase shift amount φ6 of the entire phase shift circuit 530C changes from 0 ° to 180 ° depending on the frequency.
[0150]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 510C and 530C, and the total phase shift amount of the two phase shift circuits 510C and 530C is 360 ° at a predetermined frequency.
[0151]
In the tuning circuit 1J described above, the two phase shift circuits are both configured to include the CR circuit, but may be replaced with a phase shift circuit including the LR circuit.
[0152]
30 and 31 are circuit diagrams showing the configuration of the phase shift circuit including the LR circuit. A phase shift circuit 510L illustrated in FIG. 30 has a configuration in which the CR circuit including the capacitor 514 and the variable resistor 516 in the phase shift circuit 510C illustrated in FIG. 27 is replaced with an LR circuit including the variable resistor 516 and the inductor 517. ing.
[0153]
Further, the phase shift circuit 530L illustrated in FIG. 31 has a configuration in which the CR circuit including the capacitor 534 and the resistor 536 in the phase shift circuit 530C illustrated in FIG. 27 is replaced with an LR circuit including the resistor 536 and the inductor 537. ing.
[0154]
30 is equivalent to the preceding phase shift circuit 510C shown in FIG. 27, and the phase shift circuit 530L shown in FIG. 31 is equivalent to the subsequent phase shift circuit 530C shown in FIG. 27, at least one of the two phase shift circuits 510C and 530C shown in FIG. 27 can be replaced with the phase shift circuits 510L and 530L.
[0155]
[Ninth Modification of Tuning Circuit]
FIG. 32 is a circuit diagram showing a ninth modification of the tuning circuit. The tuning circuit 1K shown in the figure includes a phase inversion circuit 580 that inverts and outputs the phase of an input AC signal, and two phase shift circuits 510C and 510C ′ that perform a total phase shift of 180 ° at a predetermined frequency. And a feedback resistor 570 and an input resistor 574.
[0156]
The phase relationship between the input / output signals of the two phase shift circuits 510C and 510C ′ is as described with reference to FIG. 28, and the total phase shift amount of the two phase shift circuits 510C at the predetermined frequency is 180 °. It becomes.
[0157]
A phase inverting circuit 580 connected to the preceding stage of the two phase shift circuits 510C and 510C 'inverts the phase of the input AC signal. For example, a grounded emitter circuit, a source grounded circuit, an operational amplifier and a resistor It is composed of a circuit that combines
[0158]
Since the signal is inverted by the phase inversion circuit 580, the phase shift amount in the entire feedback loop is 360 ° at the frequency at which the phase shift amount of the two phase shift circuits 510C and 510C ′ is 180 °. A predetermined tuning operation is performed.
[0159]
FIG. 33 is a circuit diagram showing a configuration of a tuning circuit 1L in which phase shift circuits 530C ′ and 530C are cascade-connected in place of phase shift circuits 510C ′ and 510C. Similarly to the tuning circuit 1K, the tuning circuit 1L also has a total phase shift amount of the two phase shift circuits 530C ′ and 530C and the phase inversion circuit 580, which is 360 ° at a predetermined frequency. Is done.
[0160]
By the way, the above-described tuning circuits 1C, 1D, 1E, 1F, 1G, 1H, 1J, and the like are configured to include a non-inverting circuit and two phase shift circuits or a phase inverting circuit and two phase shifting circuits. A predetermined tuning operation is performed by setting the total phase shift amount to 360 degrees at a predetermined frequency by the three circuits as a whole. Therefore, focusing only on the phase shift amount, there is a certain degree of freedom in which of the two phase shift circuits is used in the preceding stage, or in what order the three circuits described above are connected. Connection order can be determined.
[0161]
[Other Embodiments]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0162]
For example, the above-described tuning circuits 1, 1A, 1B, 1C, 1D, and 1E can achieve high stability by configuring a tuning circuit using a phase shift circuit including an operational amplifier. In this case, since the offset voltage and the voltage gain are not required to be highly accurate, a differential amplifier having a predetermined gain may be used instead of the operational amplifier in each phase shift circuit.
[0163]
FIG. 34 is a circuit diagram in which a portion necessary for the operation of the phase shift circuit is extracted from the configuration of the operational amplifier, and the whole operates as a differential amplifier having a predetermined gain. The differential amplifier shown in FIG. 1 includes a differential input stage 100 composed of FETs, a constant current circuit 102 that supplies a constant current to the differential input stage 100, and a bias that applies a predetermined bias voltage to the constant current circuit 102. The circuit 104 and the output amplifier 106 connected to the differential input stage 100 are configured. As shown in the figure, the configuration of the differential amplifier can be simplified and the bandwidth can be increased by omitting the multi-stage amplifier circuit for increasing the voltage gain included in the actual operational amplifier. Thus, by simplifying the circuit, the upper limit of the operating frequency can be increased, and accordingly, the upper limit of the output frequency of the tuning circuit configured using this differential amplifier can be increased.
[0164]
The phase shift circuit 10C included in the tuning circuit 1 described above includes a variable resistor 16. More specifically, the variable resistor 16 can be realized by using the channel resistance of a junction-type or MOS-type field effect transistor (FET). When the channel formed between the source and drain of the FET is used as a resistor instead of the variable resistor 16, the gate voltage is variably controlled and the channel resistance is arbitrarily changed within a certain range to change each phase shift. The amount of phase shift in the circuit can be changed.
[0165]
Also, instead of configuring the variable resistor by one FET, that is, a p-channel or n-channel FET, a p-channel FET and an n-channel FET are connected in parallel to form one variable resistor, and the gate of each FET The resistance value may be varied by applying a gate voltage having the same size and different polarity between the substrate and the substrate. If a variable resistor is configured by combining two FETs, the nonlinear region of the FET can be improved, and thus the distortion of the tuning signal can be reduced.
[0166]
Further, the phase shift circuit 10C and the like shown in each of the above-described embodiments change the overall tuning frequency by changing the phase shift amount by changing the resistance value of the variable resistor 16 and the like connected in series with the capacitor 14 and the like. The overall tuning frequency may be changed by changing the capacitance of the capacitor 14 or the like.
[0167]
For example, by changing the capacitance by replacing the capacitor 14 or the like included in at least one of the two phase shift circuits with a variable capacitance element, the phase shift shift amount by each phase shift circuit is changed, and the tuning frequency is changed. Can be changed. More specifically, the variable capacitance element described above can be formed by a variable capacitance diode that can change the reverse bias voltage applied between the anode and the cathode, or by an FET whose gate capacitance can be changed by the gate voltage.
[0168]
In order to vary the reverse bias voltage applied to the above-described variable capacitance element, a DC current blocking capacitor may be connected in series with the variable capacitance element.
[0169]
In the tuning circuit 1 and the like described above, the feedback resistor 70 having a fixed resistance value is used as the feedback impedance element, and the input resistor 74 having a fixed resistance value is used as the input impedance element. However, at least one of the resistors is variable. It may be configured by a resistor so that the tuning bandwidth in the tuning circuit 1 or the like can be varied.
[0170]
【The invention's effect】
As described above in detail, according to the present invention, the PLL circuit is controlled with the tuning circuit in a state where the input of the input signal to the tuning circuit is cut off and the tuning circuit is oscillated. It becomes possible to set quickly and accurately. After the desired tuning frequency is stably set in the tuning circuit, the tuning operation is performed by setting the loop gain of the tuning circuit to less than a predetermined value, and based on the phase difference between the input and output signals of the tuning circuit. Therefore, the tuning frequency can be accurately matched with the frequency of the input signal.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a tuning mechanism to which a tuning control system of the present invention is applied.
2 is a circuit diagram showing a detailed configuration of a tuning circuit shown in FIG. 1; FIG.
3 is a circuit diagram showing an extracted configuration of the previous phase shift circuit shown in FIG. 2; FIG.
4 is a diagram showing the relationship between the magnitude of input / output voltage and the phase of the phase shift circuit shown in FIG. 3;
5 is a circuit diagram showing an extracted configuration of a subsequent phase shift circuit shown in FIG. 2; FIG.
6 is a diagram showing the relationship between the magnitude of input / output voltage and the phase of the phase shift circuit shown in FIG. 5;
FIG. 7 is a circuit diagram showing a detailed configuration of a frequency control circuit.
FIG. 8 is a timing diagram when the tuning frequency is higher than the frequency of the input signal to the tuning circuit.
FIG. 9 is a timing diagram when the tuning frequency is lower than the frequency of the input signal to the tuning circuit.
FIG. 10 is a circuit diagram showing a configuration of a second embodiment of a tuning mechanism.
FIG. 11 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit therein;
FIG. 12 is a circuit diagram showing another configuration of a phase shift circuit including an LR circuit therein;
FIG. 13 is a circuit diagram showing a second modification of the tuning circuit.
FIG. 14 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit therein;
FIG. 15 is a circuit diagram showing another configuration of a phase shift circuit including an LR circuit therein;
FIG. 16 is a circuit diagram showing a third modification of the tuning circuit.
FIG. 17 is a circuit diagram showing a fourth modification of the tuning circuit.
FIG. 18 is a circuit diagram showing a configuration of a tuning circuit including a phase inverting circuit.
FIG. 19 is a circuit diagram showing another configuration of a tuning circuit including a phase inverting circuit.
FIG. 20 is a circuit diagram showing a sixth modification of the tuning circuit.
21 is a diagram showing the relationship between the magnitude of input / output voltage and the phase of the preceding phase shift circuit shown in FIG. 20;
22 is a diagram showing the relationship between the magnitude of input / output voltage and the phase of the subsequent phase shift circuit shown in FIG. 20;
FIG. 23 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit therein;
FIG. 24 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit therein;
FIG. 25 is a circuit diagram showing a seventh modification of the tuning circuit.
FIG. 26 is a circuit diagram showing a configuration of a tuning circuit including a phase inverting circuit.
FIG. 27 is a circuit diagram showing another configuration of a tuning circuit including a phase inverting circuit.
28 is a diagram illustrating the relationship between the magnitude and phase of the input / output voltage of the preceding phase shift circuit shown in FIG. 27;
29 is a diagram showing the relationship between the magnitude and phase of the input / output voltage of the latter-stage phase shift circuit shown in FIG. 27;
FIG. 30 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit therein;
FIG. 31 is a circuit diagram showing another configuration of a phase shift circuit including an LR circuit therein;
FIG. 32 is a circuit diagram showing a configuration of a tuning circuit including a phase inverting circuit.
FIG. 33 is a circuit diagram showing another configuration of a tuning circuit including a phase inverting circuit.
FIG. 34 is a circuit diagram in which a portion necessary for the operation of the phase shift circuit is extracted from the configuration of the operational amplifier.
[Explanation of symbols]
1 Tuning circuit
2 Frequency control circuit
3 PLL control circuit
4 Tuning detection circuit
5 Input switching circuit
6 Control signal switching circuit

Claims (18)

Including two cascaded all-pass phase shift circuits, and an adder circuit that adds the feedback signal and the input signal output from the subsequent phase shift circuit and inputs them to the previous phase shift circuit. A tuning circuit for extracting only a predetermined frequency component from the input signal;
A PLL control circuit that compares the phase of the output of the tuning circuit with a predetermined reference frequency signal and performs PLL control on the tuning circuit;
When a signal having a frequency close to the predetermined frequency is input to the tuning circuit, the tuning frequency of the tuning circuit is determined based on the phase difference between the input and output signals of the tuning circuit. A frequency control circuit to match the frequency;
When setting the tuning frequency of the tuning circuit, the PLL control by the PLL control circuit is performed in a state where the loop gain of the feedback loop formed in the tuning circuit is set to a predetermined value or more and the tuning circuit is oscillated. After the tuning frequency of the tuning circuit is set, the tuning control circuit sets the loop gain below the predetermined value and extracts only the tuning frequency component from the input signal by the frequency control circuit. A tuning control system characterized by comprising: In claim 1,
The tuning control circuit cuts off the input signal input to the tuning circuit when setting the tuning frequency of the tuning circuit, and after setting the tuning frequency of the tuning circuit, the tuning control circuit cuts the input signal to the tuning circuit. A tuning control system comprising an input switching means for inputting to a circuit. In claim 1 or 2,
When the tuning frequency of the tuning circuit is set, the frequency control circuit outputs a signal corresponding to the output of the PLL control circuit, and after the tuning frequency of the tuning circuit is set, an input / output signal of the tuning circuit A tuning control method characterized by outputting a signal corresponding to the phase difference between the two. In claim 3,
The tuning control system, wherein the tuning control circuit determines whether or not a tuning frequency of the tuning circuit is set based on a phase comparison result by the PLL control circuit. In claim 1 or 2,
The PLL control circuit includes:
A phase comparator that performs a frequency comparison between the output of the tuning circuit and the reference frequency signal;
A charge pump that outputs a voltage according to a comparison result by the phase comparator;
A high-frequency component is removed from the output of the charge pump to generate a control signal, and a low-pass filter that applies the control signal to the tuning circuit,
The frequency control circuit includes:
A synchronous rectification circuit that performs synchronous rectification on an input signal of the tuning circuit based on a reference signal synchronized with an output signal of the tuning circuit;
A pulse conversion circuit that outputs a signal having a pulse width corresponding to the phase difference between the input and output signals of the tuning circuit based on the output of the synchronous rectifier circuit;
A polarity determination circuit that determines the polarity of the phase difference based on one of the input and output signals of the tuning circuit;
Two opening / closing means for passing or blocking the output signal of the pulse conversion circuit based on the determination result by the polarity determination circuit;
The tuning control circuit, when setting the tuning frequency of the tuning circuit, supplies a voltage according to the comparison result by the phase comparator to the charge pump, and after the tuning frequency of the tuning circuit is set, A tuning control system, wherein outputs of the two opening / closing means are supplied to the charge pump. In claim 5 ,
Either one of the two phase shift circuits includes a differential amplifier and a series circuit including a CR circuit or an LR circuit whose time constant can be changed by the control signal.
The tuning control system characterized in that the tuning circuit outputs the output of either of the two phase shift circuits as a tuning signal. In claim 6,
At least one of the two cascade-connected phase shift circuits includes a first resistor having one end connected to the inverting input terminal of the differential amplifier and the other end connected to the series circuit, and the differential amplifier A second resistor connected between the output terminal and the inverting input terminal, and an AC signal is input to the inverting input terminal of the differential amplifier via the first resistor. A tuning control system characterized in that a connecting portion between a capacitor or an inductor and a resistor is connected to a non-inverting input terminal of the differential amplifier. In claim 6,
At least one of the two cascade-connected phase shift circuits includes a first resistor having one end connected to the inverting input terminal of the differential amplifier and the other end connected to the series circuit, and the differential amplifier A first voltage dividing circuit connected to the output terminal; and a second resistor connected between the output terminal of the first voltage dividing circuit and the inverting input terminal of the differential amplifier. A tuning control system characterized in that a connection part between a capacitor or an inductor and a resistor in the series circuit is connected to a non-inverting input terminal of the differential amplifier. In claim 6,
At least one of the two cascade-connected phase shift circuits includes a first resistor having one end connected to the inverting input terminal of the differential amplifier and the other end connected to the series circuit, and the differential amplifier A second resistor connected between the output terminal and the inverting input terminal; and a third resistor having one end connected to the inverting input terminal of the differential amplifier and the other end grounded. An AC signal is input to the inverting input terminal of the differential amplifier via the first resistor, and a connection portion between the capacitor or the inductor and the resistor in the series circuit is connected to the non-inverting input terminal of the differential amplifier. Tuning control system characterized by that. In claim 6,
At least one of the two cascade-connected phase shift circuits has a first voltage dividing circuit configured by first and second resistors having substantially equal resistance values, and the first voltage dividing circuit A tuning control system characterized in that the potential difference between the potential of the output terminal of the capacitor and the potential of the connection portion between the capacitor or the inductor and the resistor in the series circuit is amplified by the differential amplifier with a predetermined amplification and output. In any one of Claims 6-10,
The tuning circuit includes a non-inverting circuit that is inserted into a part of a feedback loop formed by the two cascaded phase shift circuits and outputs the input signal without changing the phase, and is connected in cascade. A tuning control system characterized by performing a tuning operation at a frequency in the vicinity of a frequency at which the total of the phase shift amounts of the two phase shift circuits is 360 °. In any one of Claims 6-10,
The tuning circuit includes a phase inverting circuit that is inserted into a part of a feedback loop formed by the two cascaded phase shift circuits and that inverts the phase of an input signal and outputs the inverted signal. A tuning control system characterized by performing a tuning operation at a frequency in the vicinity of a frequency at which the sum of the phase shift amounts of the two phase shift circuits is 180 °. In any one of Claims 6-10,
Inserting a second voltage divider in part of the feedback loop;
The tuning control system characterized in that the tuning circuit outputs an AC signal input to the second voltage dividing circuit as a tuning signal. In claim 5 ,
Either one of the two phase shift circuits comprises a conversion means for converting an input AC signal into an in-phase AC signal and a reverse-phase AC signal, and a CR circuit or an LR circuit. The time constant is changed by the control signal. A possible series circuit, and combining means for synthesizing one AC signal converted by the converting means via one end of the series circuit and the other AC signal via the other end of the series circuit. And
The tuning circuit includes a non-inverting circuit that amplifies and outputs an input AC signal without changing the phase, and cascades the two phase shift circuits and the non-inverting circuit in a predetermined order. The tuning control system is characterized in that the tuning operation is performed at a frequency near the frequency at which the total amount of phase shift is 360 °. In claim 14,
A voltage dividing circuit is inserted into a part of a feedback loop formed by the two cascaded phase shift circuits and the non-inverting circuit;
The tuning control system characterized in that the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal. In claim 5 ,
Either one of the two phase shift circuits comprises a conversion means for converting an input AC signal into an in-phase AC signal and a reverse-phase AC signal, and a CR circuit or an LR circuit. The time constant is changed by the control signal. A possible series circuit, and combining means for synthesizing one AC signal converted by the converting means via one end of the series circuit and the other AC signal via the other end of the series circuit. And
Said tuning circuit has a phase inversion circuit and outputting the inverted and amplified the phase of the input AC signal, wherein by cascade connecting the two phase shifting circuits and said phase inverting circuit in a predetermined sequence A tuning control system characterized by performing a tuning operation at a frequency in the vicinity of a frequency at which a total of phase shift amounts of two phase shift circuits is 180 °. In claim 16,
A voltage dividing circuit is inserted into a part of a feedback loop formed by the two cascaded phase shifting circuits and the phase inverting circuit;
The tuning control system characterized in that the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal. In any one of Claims 1-17,
A tuning control system characterized in that component parts are integrally formed on a semiconductor substrate.

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