JP3628408B2 - Tuning control method - Google Patents

Description

となる。
【００５２】
この（５）式によれば、ω＝０（直流の領域）のときにＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。また、ω＝∞のときにもＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。さらに、ω＝１／Ｔの同調点（各移相回路の時定数が異なる場合には、ω＝１／√（Ｔ_１ ・Ｔ_２ ）の同調点）においてはＡ＝１であって帰還抵抗７０と入力抵抗７４の抵抗比ｎに無関係であることがわかる。換言すれば、図１０に示すように、ｎの値を変化させても同調点がずれることなく、かつ同調点の減衰量も変化しない。
【００５３】
しかも、前段の移相回路１０Ｃ内の可変抵抗１６の抵抗値を変えることにより、移相回路１０Ｃに含まれるＣＲ回路の時定数を変化させることができ、同調周波数ωをある範囲で任意に変化させることができる。
【００５４】
なお、（２）式あるいは（３）式から図５、図７に示したφ１ 、φ２ を求めると、
φ１ ＝ｔａｎ｛２ωＴ_１ ／（１−ω^２ Ｔ_１ ^２ ）｝ ・・・（６）
φ２ ＝−ｔａｎ｛２ωＴ_２ ／（１−ω^２ Ｔ_２ ^２ ）｝ ・・・（７）
となる。なお、ここでは図５に示したφ１ を基準に考えて、図７に示したφ２ の符号を「−」として表した。
【００５５】
例えばＴ_１ ＝Ｔ_２ （＝Ｔ）の場合には、ω＝１／Ｔのときに２つの移相回路１０Ｃ、３０Ｃによる位相シフト量の合計が３６０°となって上述した同調動作が行われ、このときφ１ ＝９０°、φ２ ＝−９０°となる。
【００５６】
ところで、図７では前段の移相回路３０Ｃの入力電圧と同相の電圧Ｅｉ よりも出力電圧Ｅｏ の方が位相が進んでいるように図示したが、実際には入力信号を基準に考えると出力信号は常に遅れ位相の状態にある。
【００５７】
図１１は、２つの移相回路１０Ｃ、３０Ｃに入出力される信号間の位相関係を示す図であり、前段の移相回路１０Ｃに同調周波数と等しい周波数の信号が入力された場合であって、一例として各移相回路１０Ｃ、３０Ｃの時定数Ｔ_１ 、Ｔ_２ が等しい場合が示されている。
【００５８】
前段の移相回路１０Ｃは、図１１（Ａ）に示すように、入力信号Ｓ１に対してφ１ （＝９０°）の位相シフトを行って、出力信号Ｓ２を出力している。
【００５９】
また、後段の移相回路３０Ｃは、図１１（Ｂ）に示すように、入力信号Ｓ２（前段の移相回路１０Ｃの出力信号と共通）に対してφ２ の位相シフトを行って、出力信号Ｓ３を出力している。ここで、出力信号Ｓ３は入力信号Ｓ２に対して、一見９０°位相が進んでいるように見えるが、実際には信号が反転してさらに９０°の位相遅れになるので、位相遅れ方向にφ２ ′＝２７０°の位相シフトが行われる。
【００６０】
したがって、２つの移相回路１０Ｃ、３０Ｃを縦続接続した場合には、図１１（Ｃ）に示すように、上述したφ１ ＝９０°とφ２ ′＝２７０°が足し合わされて、全体として３６０°の位相シフトが行われる。
【００６１】
別の見方をすれば、同調増幅器１に入力される信号の中で２つの移相回路１０Ｃ、３０Ｃによる位相シフト量の合計が３６０°以外の周波数成分は閉ループを循環する際に減衰し、位相シフト量の合計が３６０°となる周波数成分のみが選択、出力されて所定の同調動作が行われる。
【００６２】
上述した同調増幅器１によれば、入力抵抗７４の抵抗値を可変して帰還抵抗７０と入力抵抗７４の抵抗比ｎを変えても同調周波数および同調時の利得が一定であり、最大減衰量のみを変化させることができる。なお、帰還抵抗７０と入力抵抗７４の抵抗比を変えるには、少なくとも一方を可変抵抗によって形成すればよい。
【００６３】
また、移相回路１０Ｃ内のＣＲ回路を構成する可変抵抗の抵抗値を変えることにより、このＣＲ回路の時定数を変化させることができるため、１／√（Ｔ_１ Ｔ_２ ）によって算出される同調周波数ωもある範囲で可変することができる。
【００６４】
また、最大減衰量は、帰還抵抗７０と入力抵抗７４の抵抗比ｎによって決定されるため、移相回路１０Ｃ内のＣＲ回路を構成する可変抵抗の抵抗値を変えて同調周波数を変えた場合であっても、この最大減衰量に影響を与えることはなく、同調周波数や最大減衰量を互いに干渉しあうことなく調整することができる。
【００６５】
また、移相回路３０Ｃの後段に分圧回路６０を接続して、この分圧回路６０による分圧出力を帰還信号として用いるとともに分圧前の信号を同調増幅器１の出力として取り出すことにより、同調動作と同時に信号の増幅を行うことができる。
【００６６】
また、上述した同調増幅器１は、差動増幅器、キャパシタおよび抵抗を組み合わせて構成しており、どの構成素子も半導体基板上に形成することができることから、同調周波数および最大減衰量を調整し得る同調増幅器１の全体を半導体基板上に形成して集積回路とすることも容易である。
【００６７】
このように、上述した同調機構に含まれる同調増幅器１は、外部からの制御電圧に応じて同調周波数が設定可能であって、同調周波数を変化させた場合であっても出力振幅が一定であり、一般的に発振器の周波数制御に用いられているＰＬＬ構成とすることにより、容易に同調周波数の変動を防止し、周波数が安定した同調出力を得ることができる。
【００６８】
また、発振器３で発生する基準信号の周波数を変えることにより、この基準信号の周波数に追随して同調周波数を変化させることができるため、複数の受信周波数を有するラジオ受信機等に上述した同調制御方式を適用することもできる。この場合には、同調周波数を任意に、しかも正確に変化させることができるため、従来から用いられているスーパーヘテロダイン方式を用いることなく受信機を構成することができる。
【００６９】
また、図１に示した同調機構のほとんどは半導体基板上に形成することが可能であり、半導体基板上に形成した各素子の素子定数が製造ロットあるいは使用温度等によって変化した場合であっても、同調増幅器１の同調周波数を正確に所定の周波数に合わせることができる。
【００７０】
ところで、図１に示した同調機構に含まれる同調増幅器１は各移相回路１０Ｃ、３０ＣをＣＲ回路を含んで構成したが、ＣＲ回路を抵抗とインダクタからなるＬＲ回路に置き換えた移相回路を用いて同調増幅器を構成することもできる。
【００７１】
図１２は、ＬＲ回路を含む移相回路の他の構成を示す回路図であり、図３に示した同調増幅器１の前段の移相回路１０Ｃと置き換え可能な構成が示されている。同図に示す移相回路１０Ｌは、２入力の差分電圧を所定の増幅度で増幅して出力する差動増幅器１２と、入力端２２に入力された信号の位相を所定量シフトさせて差動増幅器１２の非反転入力端子に入力するインダクタ１７および可変抵抗１６と、入力端２２に入力された信号の位相を変えずにその電圧レベルを約１／２に分圧して差動増幅器１２の反転入力端子に入力する抵抗１８および２０とを含んで構成されている。なお、インダクタ１７に直列に接続されたキャパシタ１９は直流電流阻止用であり、そのインピーダンスは動作周波数において極めて小さく設定され、すなわち大きな静電容量を有している。
【００７２】
この移相回路１０Ｌは、図４に示した移相回路１０Ｃ内の可変抵抗１６とキャパシタ１４からなるＣＲ回路を、インダクタ１７と可変抵抗１６からなるＬＲ回路に置き換えた構成を有している。
【００７３】
図１３は、移相回路１０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。図４に示した移相回路１０Ｃと同様に、差動増幅器１２の非反転入力端子に印加される電圧（可変抵抗１６の両端電圧ＶＲ３）から反転入力端子に印加される電圧（抵抗２０の両端電圧Ｅｉ ／２）をベクトル的に減算したものが差分電圧Ｅｏ ′となる。この差分電圧Ｅｏ ′は、図１３に示した半円において、その中心点を始点とし、電圧ＶＲ３とインダクタ１７の両端電圧ＶＬ１とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ ／２に等しくなる。差動増幅器１２の出力電圧Ｅｏ はこの差分電圧Ｅｏ ′を所定の増幅度で増幅したものであり、移相回路１０Ｌは、出力電圧Ｅｏ が入力信号の周波数によらず一定であって全域通過回路として動作する。
【００７４】
また、図１３に示した移相回路１０Ｌの位相シフト量φ３ は、インダクタ１７と可変抵抗１６により構成されるＬＲ回路の時定数をＴ_１ （インダクタ１７のインダクタンスをＬ、可変抵抗１６の抵抗値をＲとするとＴ_１ ＝Ｌ／Ｒ）とすると、上述した（６）式に示したφ１ と同じとなる。
【００７５】
図１４は、ＬＲ回路を含む移相回路の構成を示す回路図であり、図３に示した同調増幅器１の後段の移相回路３０Ｃと置き換え可能な構成が示されている。同図に示す移相回路３０Ｌは、２入力の差分電圧を所定の増幅度で増幅して出力する差動増幅器３２と、入力端４２に入力された信号の位相を所定量シフトさせて差動増幅器３２の非反転入力端子に入力する抵抗３６およびインダクタ３７と、入力端４２に入力された信号の位相を変えずにその電圧レベルを約１／２に分圧して差動増幅器３２の反転入力端子に入力する抵抗３８および４０とを含んで構成されている。なお、インダクタ３７に直列に接続されたキャパシタ３９は直流電流阻止用であり、そのインピーダンスは動作周波数において極めて小さく設定され、すなわち大きな静電容量を有している。
【００７６】
この移相回路３０Ｌは、図６に示した移相回路３０Ｃ内のキャパシタ３４と抵抗３６からなるＣＲ回路を、抵抗３６とインダクタ３７からなるＬＲ回路に置き換えた構成を有している。
【００７７】
図１５は、移相回路３０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。図６に示した移相回路３０Ｃと同様に、差動増幅器３２の非反転入力端子に印加される電圧（インダクタ３７の両端電圧ＶＬ２）から反転入力端子に印加される電圧（抵抗４０の両端電圧Ｅｉ ／２）をベクトル的に減算したものが差分電圧Ｅｏ ′となる。この差分電圧Ｅｏ ′は、図１５に示した半円において、その中心点を始点とし、電圧ＶＬ２と抵抗３６の両端電圧ＶＲ４とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ ／２に等しくなる。差動増幅器３２の出力電圧Ｅｏ はこの差分電圧Ｅｏ ′を所定の増幅度で増幅したものであり、移相回路３０Ｌは、出力電圧Ｅｏ が入力信号の周波数によらず一定であって全域通過回路として動作する。
【００７８】
また、図１５に示した移相回路３０Ｌの位相シフト量φ４ は、抵抗３６とインダクタ３７により構成されるＬＲ回路の時定数をＴ_２ （抵抗３６の抵抗値をＲ、インダクタ３７のインダクタンスをＬとするとＴ_２ ＝Ｌ／Ｒ）とすると、上述した（７）式に示したφ２ と同じとなる。
【００７９】
このように、図１２に示した移相回路１０Ｌおよび図１４に示した移相回路３０Ｌのそれぞれは、図４あるいは図６に示した移相回路１０Ｃ、３０Ｃと等価であり、図３に示した同調増幅器１において、前段の移相回路１０Ｃを図１２に示した移相回路１０Ｌに、後段の移相回路３０Ｃを図１４に示した移相回路３０Ｌにそれぞれ置き換えることが可能である。
【００８０】
また、上述した２つの移相回路１０Ｌ、３０Ｌのそれぞれは、各移相回路１０Ｌ、３０Ｌに含まれるＬＲ回路の時定数によって同調周波数が決まることになるが、各時定数Ｔは例えばＬ／Ｒであって、同調周波数ωは１／Ｔ＝Ｒ／Ｌに比例する。ここで、ＬＲ回路を構成するインダクタは、写真触刻法等により渦巻き形状の導体を半導体基板上に形成することにより実現できるが、このようにして形成したインダクタを用いることにより、同調増幅器の全体を半導体基板上に集積化することができる。
【００８１】
但し、この場合にはインダクタが有するインダクタンスが極めて小さくなるため、同調周波数が高くなる。別の見方をすれば、同調増幅器の同調周波数は例えば各移相回路１０Ｌ、３０Ｌ内のＬＲ回路の時定数の逆数Ｒ／Ｌに比例し、この中でインダクタンスＬは集積化等により小さくすることが容易であるため、２つの移相回路１０Ｌ、３０Ｌを含んで構成した同調増幅器全体を集積化することにより同調周波数の高周波化が容易となる。
【００８２】
また、図３に示した同調増幅器１において、移相回路１０Ｃ、３０Ｃのいずれか一方を図１２あるいは図１４に示した移相回路１０Ｌ、３０Ｌに置き換えるようにしてもよい。特に、このような同調増幅器全体を集積化した場合には、温度変化による同調周波数の変動を防止する、いわゆる温度補償が可能となる。すなわち、ＣＲ回路の時定数ＴはＣＲであり、ＬＲ回路の時定数ＴはＬ／Ｒであって、それぞれにおいて抵抗値Ｒが分子と分母に分かれるため、集積化によってＣＲ回路およびＬＲ回路を構成する抵抗を半導体材料によって形成するような場合には、これら各抵抗の温度変化に対する同調周波数の変動を抑制する効果がある。
【００８３】
また、図１に示した同調機構に含まれる同調増幅器１は、互いに移相方向が異なる２つの移相回路を含んで構成したが、基本的に同じ構成を有する２つの移相回路を組み合わせて同調増幅器を構成することもできる。
【００８４】
図１６は、同調増幅器の他の構成を示す回路図である。同図に示す同調増幅器１Ａは、入力される交流信号の位相を反転して出力する位相反転回路８０と、それぞれが入力される交流信号の位相を所定量シフトさせることにより所定の周波数において合計で１８０°の位相シフトを行う２つの移相回路１０Ｃおよび１０Ｃ′と、後段の移相回路１０Ｃ′のさらに後段に設けられた抵抗６２および６４からなる分圧回路６０と、帰還抵抗７０および入力抵抗７４（入力抵抗７４は帰還抵抗７０の抵抗値のｎ倍の抵抗値を有しているものとする）のそれぞれを介することにより分圧回路６０の分圧出力（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。
【００８５】
前段の移相回路１０Ｃはその詳細構成および入出力信号の位相関係は図４および図５を用いて説明した通りであり、後段の移相回路１０Ｃ′は前段の移相回路１０Ｃ内の可変抵抗１６を抵抗値が固定の抵抗１５に置き換えた構成を有している。したがって、所定の周波数において、２つの移相回路１０Ｃ、１０Ｃ′の全体による位相シフト量の合計が１８０°となる。
【００８６】
また、２つの移相回路１０Ｃ、１０Ｃ′の前段に接続された位相反転回路８０は、入力される交流信号の位相を反転するものであり、例えば、エミッタ接地回路やソース接地回路あるいはオペアンプと抵抗を組み合わせた回路によって実現される。
【００８７】
このように、所定の周波数において、２つの移相回路１０Ｃ、１０Ｃ′によって位相が１８０°シフトされ、さらにその前段に接続された位相反転回路８０によって位相が反転され、これら３つの回路の全体による位相シフト量の合計が３６０°となる。
【００８８】
また、後段の移相回路１０Ｃ′の出力は出力端子９２から同調増幅器１Ａの出力として取り出されるとともに、後段の移相回路１０Ｃ′の出力を分圧回路６０を通した信号が帰還抵抗７０を介して位相反転回路８０の入力側に帰還されている。そして、この帰還される信号と入力抵抗７４を介して入力される信号とが加算され、この加算された信号が位相反転回路８０に入力されている。
【００８９】
このように、分圧回路６０の出力を帰還抵抗７０を介して位相反転回路８０の入力側に帰還させ、この帰還信号に入力抵抗７４を介して入力した信号を加算するとともに、２つの移相回路１０Ｃ、１０Ｃ′の利得を調整して分圧回路６０や帰還抵抗７０と入力抵抗７４の接続部において生じる損失等を補って帰還ループのオープンループゲインを１以下に設定することにより、図３に示した同調増幅器１と同様の同調動作および増幅動作を行うことができる。なお、移相回路１０Ｃ、１０Ｃ′の各利得を調整する代わりに、位相反転回路８０の利得を調整してもよい。
【００９０】
図１７は、同調増幅器の他の構成を示す回路図である。同図に示す同調増幅器１Ｂは、入力される交流信号の位相を反転して出力する位相反転回路８０と、それぞれが入力される交流信号の位相を所定量シフトさせることにより所定の周波数において合計で１８０°の位相シフトを行う２つの移相回路３０Ｃ′および３０Ｃと、後段の移相回路３０Ｃのさらに後段に設けられた抵抗６２および６４からなる分圧回路６０と、帰還抵抗７０および入力抵抗７４（入力抵抗７４は帰還抵抗７０の抵抗値のｎ倍の抵抗値を有しているものとする）のそれぞれを介することにより分圧回路６０の分圧出力（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。
【００９１】
後段の移相回路３０Ｃはその詳細構成および入出力信号の位相関係は図６および図７を用いて説明した通りであり、前段の移相回路３０Ｃ′は後段の移相回路３０Ｃ内の抵抗３６を外部から印加されるゲート電圧（制御電圧）によって抵抗値が変更可能な可変抵抗３５に置き換えた構成を有している。したがって、所定の周波数において、２つの移相回路３０Ｃ′、３０Ｃの全体による位相シフト量の合計が１８０°となる。
【００９２】
このように、上述した２つの移相回路３０Ｃ′、３０Ｃを用いた場合であっても、所定の周波数において２つの移相回路３０Ｃ′、３０Ｃによって位相が１８０°シフトされ、さらにその前段に接続された位相反転回路８０によって位相が反転され、これら３つの回路の全体による位相シフト量の合計が３６０°となる。
【００９３】
したがって、上述した同調増幅器１Ｂは、分圧回路６０の出力を帰還抵抗７０を介して位相反転回路８０の入力側に帰還させ、この帰還信号に入力抵抗７４を介して入力した信号を加算するとともに、２つの移相回路３０Ｃ′、３０Ｃの利得を調整して分圧回路６０や帰還抵抗７０と入力抵抗７４の接続部において生じる損失等を補って帰還ループのオープンループゲインを１以下に設定することにより、図１６に示した同調増幅器１Ａ等と同様の同調動作および増幅動作を行うことができる。
【００９４】
なお、図１６、図１７に示した同調増幅器１Ａ、１Ｂは、いずれも２つの移相回路をＣＲ回路を含んで構成したが、少なくとも一方をＬＲ回路を含んで構成するようにしてもよい。
【００９５】
具体的には、図１６に示した同調増幅器１Ａにおいて、前段の移相回路１０Ｃを図１２に示した移相回路１０Ｌ、あるいは、後段の移相回路１０Ｃ′を図１２に示した移相回路１０Ｌ内の可変抵抗１６の代わりに抵抗値が固定の抵抗１５を用いた移相回路１０Ｌ′に置き換える。または、２つの移相回路１０Ｃ、１０Ｃ′の両方を上述した移相回路１０Ｌ、１０Ｌ′に置き換える。
【００９６】
また、図１７に示した同調増幅器１Ｂにおいて、前段の移相回路３０Ｃ′を図１４に示した移相回路３０Ｌ内の抵抗３６の代わりに可変抵抗３５を用いた移相回路３０Ｌ′、あるいは、後段の移相回路３０Ｃを図１４に示した移相回路３０Ｌに置き換える。または、２つの移相回路３０Ｃ′、３０Ｃの両方を上述した移相回路３０Ｌ′、３０Ｌに置き換える。
【００９７】
特に、両方の移相回路をＬＲ回路を有する移相回路に置き換えた場合には、同調増幅器全体を集積化することにより同調周波数の高周波化が容易となり、一方の移相回路をＬＲ回路を有する移相回路に置き換えた場合には、温度変化による同調周波数の変動を防止する、いわゆる温度補償が可能となる。
【００９８】
ところで、上述した各種の同調増幅器は、非反転回路と２つの移相回路あるいは位相反転回路と２つの移相回路を含んで構成されており、位相シフトに着目すると接続された３つの回路の全体によって所定の周波数において合計の位相シフト量を３６０°にすることにより所定の同調動作を行うようになっている。したがって、位相シフト量だけに着目すると、２つの移相回路のどちらを前段に用いるか、あるいは上述した３つの回路をどのような順番で接続するかはある程度の自由度があり、必要に応じて接続順番を決めることができる。
【００９９】
図１８は、２つの移相回路と非反転回路５０を組み合わせて同調増幅器を構成した場合において、その接続状態を示す図である。なお、これらの図において、帰還インピーダンス素子７０ａおよび入力インピーダンス素子７４ａは、各同調増幅器の出力信号と入力信号とを所定の割合で加算するためのものであり、最も一般的には図３等に示すように、帰還インピーダンス素子７０ａとして帰還抵抗７０を、入力インピーダンス素子７４ａとして入力抵抗７４を使用する。
【０１００】
但し、帰還インピーダンス素子７０ａおよび入力インピーダンス素子７４ａは、それぞれの素子に入力された信号の位相関係を変えることなく加算できればよいことから、帰還インピーダンス素子７０ａおよび入力インピーダンス素子７４ａをともにキャパシタにより形成したり、抵抗やキャパシタ等を組み合わせてインピーダンスの実数分と虚数分の比を同時に調整しうるようにしてもよい。
【０１０１】
また、図１８および後述する図１９に示した同調増幅器の構成には分圧回路６０を除いた構成を示したが、実際には最終段の回路のさらに後段にこの分圧回路６０を接続し、分圧後の信号を帰還信号として用いるとともに分圧前の信号を出力として取り出せばよい。
【０１０２】
図１８（Ａ）には２つの移相回路の後段に非反転回路５０を配置した構成が示されている。このように、後段に非反転回路５０を配置した場合には、この非反転回路５０に出力バッファの機能を持たせることにより、大きな出力電流を取り出すこともできる。
【０１０３】
図１８（Ｂ）には２つの移相回路の間に非反転回路５０を配置した構成が示されている。このように、中間に非反転回路５０を配置した場合には、前段の移相回路と後段の移相回路の相互干渉を完全に防止することができる。
【０１０４】
図１８（Ｃ）には２つの移相回路のさらに前段に非反転回路５０を配置した構成が示されており、図３に示した同調増幅器１に対応している。このように、初段に非反転回路５０を配置した場合には、帰還インピーダンス素子７０ａや入力インピーダンス素子７４ａと非反転回路５０の接続部において生じる損失等を防止することができる。
【０１０５】
同様に、図１９は、２つの移相回路と位相反転回路を組み合わせて同調増幅器を構成した場合において、その接続状態を示す図である。
【０１０６】
図１９（Ａ）には２つの移相回路の後段に位相反転回路８０を配置した構成が示されている。このように、後段に位相反転回路８０を配置した場合には、この位相反転回路８０に出力バッファの機能を持たせることにより、大きな出力電流を取り出すこともできる。
【０１０７】
図１９（Ｂ）には２つの移相回路の間に位相反転回路８０を配置した構成が示されており、この場合には２つの移相回路間の相互干渉を完全に防止することができる。図１９（Ｃ）には２つの移相回路のさらに前段に位相反転回路８０を配置した構成が示されており、図１６に示した同調増幅器１Ａあるいは図１７に示した同調増幅器１Ｂに対応している。この場合には帰還インピーダンス素子７０ａや入力インピーダンス素子７４ａと位相反転回路８０の接続部において生じる損失等を防止することができる。
【０１０８】
本発明は上述した各種の実施形態に限定されるものではなく、この発明の要旨の範囲内で種々の変形実施が可能である。
【０１０９】
例えば、上述した各種の同調増幅器に含まれる可変抵抗１６は、接合型のＦＥＴで構成した場合を図示したが、ＭＯＳ型のＦＥＴを用いてもよい。また、上述した可変抵抗１６をｐチャネルのＦＥＴとｎチャネルのＦＥＴとを並列接続して構成してもよい。２つのＦＥＴを組み合わせて可変抵抗を構成することにより、ＦＥＴの非線形領域の改善を行うことができるため、同調出力の歪みを少なくすることができる。
【０１１０】
また、上述した同調増幅器１等は、２つの移相回路の一方に可変抵抗を含ませたが、両方の移相回路に可変抵抗を含ませて（例えば図３において抵抗３６を可変抵抗に置き換えて）同調周波数を変化させるようにしてもよい。２つの移相回路に可変抵抗を含ませた場合には、これらの抵抗値を同時に可変することにより同調周波数の可変範囲を大きく設定できる利点がある。
【０１１１】
また、ＣＲ回路を有する移相回路においては、各移相回路内のＣＲ回路を構成する抵抗の抵抗値を変化させるのではなく、キャパシタの静電容量を変えることによりＣＲ回路の時定数を変化させ、これにより移相回路の位相シフト量、すなわち同調増幅器の同調周波数を変化させるようにしてもよい。
【０１１２】
具体的には、ＣＲ回路を構成するキャパシタ（例えば図４に示したキャパシタ１４）を可変容量ダイオードと直流電流阻止用のキャパシタに置き換える。可変容量ダイオードは、印加する逆バイアス電圧を変えることによりアノード・カソード間の静電容量が変化するものである。このような可変容量ダイオードと抵抗とを直列接続してＣＲ回路を構成することにより、印加する制御電圧（逆バイアス電圧）を変えてこのＣＲ回路の時定数を変えることができ、移相回路による位相シフト量を変化させることができる。
【０１１３】
また、この可変容量ダイオードの代わりに、ゲートに印加する制御電圧に応じてそのゲート容量がある範囲で変更可能なＦＥＴを可変容量素子として用いるようにしてもよい。
【０１１４】
また、上述した各種の同調増幅器は、後段の移相回路３０Ｃ等と出力端子９２との間に分圧回路６０を挿入し、この分圧回路６０によって分圧された信号を帰還信号としたが、この分圧回路６０を省略してもよい。この場合には、後段の移相回路３０Ｃ等の出力がそのまま帰還信号として用いられるが、分圧回路６０を省略するということは分圧回路６０の分圧比を１に設定することであり、このように考えると分圧回路６０を省略した同調増幅器も図３等に示した各種の同調増幅器に含まれると考えることができる。
【０１１５】
【発明の効果】
以上の実施形態に基づく説明から明らかなように、この発明の同調制御方式は、外部からの制御電圧に応じて同調周波数が設定可能であって、同調周波数を変化させた場合であっても出力振幅が一定な同調増幅器を用い、一般的に発振器の周波数制御に用いられているＰＬＬ構成としており、容易に同調周波数の変動を防止し、周波数が安定した同調出力を得ることができる。
【０１１６】
また、基準周波数信号の周波数を変えることにより、この周波数に追随して同調周波数を変化させることができるため、複数の受信周波数を有するラジオ受信機等に上述した同調制御方式を適用することもでき、同調周波数を任意かつ正確に変化させることができる。
【０１１７】
また、同調制御方式を適用した回路のほとんどを半導体基板上に形成することが可能であり、半導体基板上に形成した各素子の素子定数が製造ロットあるいは使用温度等によって変化した場合であっても、同調増幅器の同調周波数を正確に所定の周波数に合わせることができる。
【図面の簡単な説明】
【図１】本発明の同調制御方式を適用した一の実施形態である同調機構の構成を示す図である。
【図２】図１に示す同調機構に含まれる発振器の具体的構成を示す図である。
【図３】図１に示す同調増幅器の詳細構成を示す回路図である。
【図４】図３に示した前段の移相回路の構成を抜き出して示した回路図である。
【図５】前段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図６】図３に示した後段の移相回路の構成を抜き出して示した回路図である。
【図７】後段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図８】２つの移相回路の全体を所定の伝達関数を有する回路に置き換えた回路図である。
【図９】図８に示す構成をミラーの定理によって変換した回路図である。
【図１０】図３に示した同調増幅器の同調特性を示す図である。
【図１１】同調増幅器に含まれる２つの移相回路に入出力される信号間の位相関係を示す図である。
【図１２】図４に示した移相回路と置き換え可能な移相回路の構成を示す回路図である。
【図１３】図１２に示した移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１４】図６に示した移相回路と置き換え可能な移相回路の構成を示す回路図である。
【図１５】図１４に示した移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１６】同調増幅器の他の構成を示す回路図である。
【図１７】同調増幅器の他の構成を示す回路図である。
【図１８】同調増幅器に含まれる移相回路と非反転回路の接続形態を示す図である。
【図１９】同調増幅器に含まれる移相回路と位相反転回路の接続形態を示す図である。
【符号の説明】
１ 同調増幅器
２ 位相比較器（ＰＤ）
３ 発振器（ＯＳＣ）
４ チャージポンプ（ＣＰ）
５ ローパスフィルタ（ＬＰＦ）
１０Ｃ、３０Ｃ 移相回路
１２、３２ 差動増幅器
１４、３４ キャパシタ
１６ 可変抵抗
１８、２０、３６、３８、４０ 抵抗
５０ 非反転回路
７０ 帰還抵抗
７４ 入力抵抗
９０ 入力端子
９２ 出力端子
６０ 分圧回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tuning control system that allows only a set predetermined frequency signal to pass.
[0002]
[Background Art and Problems to be Solved by the Invention]
Conventionally, various amplifier circuits using active elements and reactance elements as tuning amplifiers have been proposed and put into practical use.
[0003]
For example, in a conventional tuning amplifier using LC resonance, the Q and gain depending on the LC circuit change when the tuning frequency is adjusted, and the tuning frequency changes when the maximum attenuation is adjusted. Alternatively, adjusting the maximum attenuation changes the gain at the tuning frequency.
[0004]
As described above, in the conventional tuning amplifier, it is extremely difficult to adjust the tuning frequency, the gain at the tuning frequency, and the maximum attenuation amount without interfering with each other. In addition, it has been difficult to form a tuning amplifier that can adjust the tuning frequency and the maximum attenuation amount by an integrated circuit.
[0005]
Even if a configuration other than the inductor included in the tuning amplifier is formed on the semiconductor substrate, it is difficult to obtain a stable tuning frequency because each element constant of the resistor and the capacitor varies depending on the manufacturing lot or the operating temperature. Was not practical.
[0006]
The present invention was created in view of the above points, and its purpose is suitable for integration, and a tuning control system capable of preventing fluctuations in tuning frequency even when integrated is provided. It is to provide.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, the tuning control method of the present invention performs a frequency comparison between a tuning amplifier whose tuning frequency can be changed according to a control voltage and a predetermined reference frequency signal and an output signal of the tuning amplifier. A phase comparator, a charge pump having an output voltage corresponding to a comparison result by the phase comparator, and a low-pass filter that extracts a direct current component from the output of the charge pump and applies it to the tuning amplifier as the control voltage. ing.
[0008]
The tuning amplifier included in this tuning control method can set the tuning frequency according to the control voltage from the outside, and the output amplitude is constant even when the tuning frequency is changed. By using the PLL configuration used for the frequency control, it is possible to easily prevent fluctuations in the tuning frequency and obtain a tuning output with a stable frequency.
[0009]
Further, since the tuning frequency can be changed following the frequency by changing the frequency of the reference frequency signal, the above-described tuning control method can be applied to a radio receiver having a plurality of reception frequencies. . In this case, since the tuning frequency can be changed arbitrarily and accurately, the receiver can be configured without using the conventionally used superheterodyne system.
[0010]
In addition, most of the circuits to which the tuning control method is applied can be formed on a semiconductor substrate, and even when the element constant of each element formed on the semiconductor substrate changes depending on the manufacturing lot or operating temperature, etc. The tuning frequency of the tuning amplifier can be accurately adjusted to a predetermined frequency.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a tuning mechanism according to an embodiment to which the tuning control system of the present invention is applied will be described in detail with reference to the drawings.
[0012]
[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of a tuning mechanism according to an embodiment. The tuning mechanism shown in the figure includes a tuning amplifier 1, a phase comparator (PD) 2, an oscillator (OSC) 3, a charge pump (CP) 4, and a low-pass filter (LPF) 5.
[0013]
The tuning amplifier 1 is a voltage control type circuit in which a tuning frequency is set in accordance with an applied control voltage, and selects and outputs only those in the vicinity of the tuning frequency from input signals. The detailed configuration and operation of the tuning amplifier 1 will be described later.
[0014]
The phase comparator 2 compares the phase and frequency of two inputs. A signal having a predetermined frequency output from the tuning amplifier 1 is output to one input terminal A, and an output from the oscillator 3 is output to the other input terminal B. The predetermined frequency signal (reference frequency signal) is input. The phase comparator 2 has two output terminals X and Y.
[0015]
For example, when the two inputs of the phase comparator 2 have the same frequency, pulses having the same pulse width synchronized with the input signal are alternately output from the two output terminals X and Y. When the frequency of the signal input to one input terminal A is higher than the output frequency of the oscillator 3 input to the other input terminal B, the frequency of the signal input to the two input terminals Accordingly, the output pulse width of one output terminal X is widened, and the output pulse width of the other output terminal Y is narrowed. On the other hand, when the frequency of the signal input to one input terminal A is lower than the output frequency of the oscillator 3 input to the other input terminal B, the signals input to the two input terminals Depending on the difference in frequency, the pulse width of the output at one output end Y is widened, and the pulse width of the output at the other output end X is narrowed.
[0016]
The oscillator 3 generates a reference frequency signal having the same frequency as the tuning frequency to be controlled to be constant, and the output waveform does not have to be a sine wave with little distortion, but may be a rectangular wave or a distorted sine wave. In order to stabilize the tuning frequency, it is preferable to adopt a PLL (phase locked loop) configuration using a crystal resonator.
[0017]
FIG. 2 is a diagram showing the configuration of the oscillator 3 in the case of the PLL configuration. The oscillator 3 shown in the figure includes an oscillator (OSC) 300 that generates a reference signal fr having a stable frequency, a phase comparator (PD) 302 that compares the phase and frequency of the reference signal fr and the feedback signal, and a phase comparison. The charge pump (CP) 304 whose output voltage changes according to the comparison result by the device 302, the low-pass filter (LPF) 306 that removes high-frequency components from the output of the charge pump 304, and the oscillation according to the output voltage of the low-pass filter 306 A voltage controlled oscillator (VCO) 308 whose frequency is controlled and a frequency divider 310 that performs a frequency dividing operation with an arbitrary frequency dividing ratio N (N is an integer) with respect to the output of the voltage controlled oscillator 308. It is configured.
[0018]
The oscillator 300 amplifies a minute vibration generated in, for example, a crystal resonator and generates a reference signal fr of 100 kHz. Further, the frequency divider 310 is configured by a programmable counter in which the frequency division ratio N can be arbitrarily set by, for example, external data input, and can continuously change the frequency division ratio N by one. Accordingly, when the frequency division ratio N of the frequency divider 310 is changed, the voltage-controlled oscillator 308 outputs stepped reference frequency signals at intervals of 100 kHz.
[0019]
The charge pump 4 shown in FIG. 1 has a capacitor inside, and the capacitor is charged and discharged according to two types of pulse trains output from the two output terminals X and Y of the phase comparator 2. . For example, when a pulse is output from the output terminal X of the phase comparator 2, discharging is performed for a time corresponding to the pulse width, and when a pulse is output from the output terminal Y, only a time corresponding to the pulse width is output. Charging is performed.
[0020]
That is, when the frequency of the output signal of the tuning amplifier 1 is equal to the frequency of the signal output from the oscillator 3, a pulse having the same period and the same pulse width is output from each of the two output terminals X and Y of the phase comparator 2. Since the outputs are alternately output, the charge amount and the discharge amount with respect to the capacitor built in the charge pump 4 become equal, and the average level of the output voltage of the charge pump 4 is maintained at a predetermined value. On the other hand, when the frequencies of the two inputs of the phase comparator 2 are different, a difference occurs in the pulse width of the pulse train output from each of the two output terminals X and Y of the phase comparator 2. The charge / discharge balance with respect to the capacitor built in the capacitor is lost, and the battery is overcharged or overdischarged, and the average level of the output voltage of the charge pump 4 changes in one direction.
[0021]
The low-pass filter 5 extracts only a DC component from the output of the charge pump 4, and this DC component is applied to the tuning amplifier 1 as a control voltage for setting a tuning frequency.
[0022]
As described above, the voltage of the output of the charge pump 4 changes in one direction while the frequencies of the two inputs of the phase comparator 2 are different. Therefore, when the output frequency of the oscillator 3 is different from the tuning frequency of the tuning amplifier 1, the output voltage of the low-pass filter 5 changes to the higher side or the lower side. In the tuning amplifier 1, the tuning frequency changes according to the change in the control voltage. When the tuning frequency coincides with the output frequency of the oscillator 3, the change in the output voltage of the low-pass filter 5 is stopped, and thereafter a constant tuning frequency is maintained.
[0023]
FIG. 3 is a circuit diagram showing a detailed configuration of the tuning amplifier 1 described above. The tuning amplifier 1 shown in the figure includes a non-inverting circuit 50 that outputs an input AC signal without changing the phase thereof, and each of them shifts the phase of the input signal by a predetermined amount so that a total of 360 ° is obtained at a predetermined frequency. Two voltage-shifting circuits 10C and 30C that perform phase shift, a voltage dividing circuit 60 including resistors 62 and 64 provided further downstream of the latter-stage phase-shifting circuit 30C, a feedback resistor 70, and an input resistor 74 (input resistor 74) Is assumed to have a resistance value that is n times that of the feedback resistor 70), and the divided output (feedback signal) of the voltage dividing circuit 60 and the signal (input signal) input to the input terminal 90 And an adder circuit for adding them at a predetermined ratio.
[0024]
Note that the non-inverting circuit 50 functions as a buffer circuit, and is provided to prevent loss of a signal or the like that occurs when the preceding phase shift circuit 10C and the above-described addition circuit are directly connected. For example, it is configured by an emitter follower circuit, a source follower circuit, or the like. When the element constant of each element such as the feedback resistor 70 is selected so as to minimize the loss or the like when directly connected, the non-inverting circuit 50 may be omitted to constitute a tuning circuit.
[0025]
FIG. 4 shows an extracted configuration of the preceding phase shift circuit 10C shown in FIG. The front-stage phase shift circuit 10C shown in the figure shifts the phase of the signal input to the input terminal 22 by a predetermined amount by a differential amplifier 12 that amplifies and outputs a differential voltage of two inputs with a predetermined amplification degree. A variable resistor 16 and a capacitor 14 (a second series circuit is constituted by the variable resistor 16 and the capacitor 14) input to the non-inverting input terminal of the differential amplifier 12, and a phase of a signal input to the input terminal 22 Resistors 18 and 20 that divide the voltage level by about ½ and input to the inverting input terminal of the differential amplifier 12 without changing (the first series circuit is constituted by these two resistors 18 and 20). It is comprised including.
[0026]
Here, the resistance value of the variable resistor 16 described above can be changed according to the control voltage from the outside. For example, as shown in FIG. The resistance value is set by applying the control voltage to the gate.
[0027]
In the phase shift circuit 10 </ b> C having such a configuration, when a predetermined AC signal is input to the input terminal 22, the voltage Ei applied to the input terminal 22 is applied to the inverting input terminal of the differential amplifier 12 and the resistor 18. A voltage divided by about 1/2 by the resistor 20 is applied.
[0028]
On the other hand, when an input signal is input to the input terminal 22, a signal appearing at the connection point between the variable resistor 16 and the capacitor 14 is input to the non-inverting input terminal of the differential amplifier 12. Since an input signal is input to one end of the CR circuit constituted by the variable resistor 16 and the capacitor 14, a signal obtained by shifting the phase of the input signal by a predetermined amount by the CR circuit is a non-inverting input terminal of the differential amplifier 12. Is input.
[0029]
The differential amplifier 12 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals in this way with a predetermined amplification degree.
[0030]
FIG. 5 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10C and the voltage appearing in the capacitor or the like.
[0031]
As shown in the figure, the voltage VC1 appearing at both ends of the capacitor 14 and the voltage VR1 appearing at both ends of the variable resistor 16 are 90 degrees out of phase with each other, and the vector addition of these is the input voltage Ei. . Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VC1 of the capacitor 14 and the both-ends voltage VR1 of the variable resistor 16 change along the circumference of the semicircle shown in FIG.
[0032]
Also, the voltage applied to the inverting input terminal (the voltage Ei / 2 across the resistor 20) subtracted in a vector from the voltage applied to the non-inverting input terminal of the differential amplifier 12 (the voltage VC1 across the capacitor 14). Becomes the differential voltage Eo ′. This differential voltage Eo ′ can be expressed by a vector having a center point in the semicircle shown in FIG. 5 as a start point and a point on the circumference where the voltage VC1 and the voltage VR1 intersect as an end point. Is equal to the radius Ei / 2 of the semicircle.
[0033]
The output voltage Eo of the differential amplifier 12 is obtained by amplifying the differential voltage Eo ′ with a predetermined amplification degree. Therefore, in the above-described phase shift circuit 10C, the output voltage Eo is constant regardless of the frequency of the input signal, and operates as an all-pass circuit.
[0034]
Further, as apparent from FIG. 5, since the voltage VC1 and the voltage VR1 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VC1 is 0 ° as the frequency ω changes from 0 to ∞. From 90 to 90 degrees. The phase shift amount φ1 of the entire phase shift circuit 10C is twice that, and varies from 0 ° to 180 ° depending on the frequency.
[0035]
Similarly, FIG. 6 shows an extracted configuration of the subsequent phase shift circuit 30C shown in FIG. The latter phase shift circuit 30C shown in the figure shifts the phase of the signal input to the input terminal 42 by a predetermined amount by a differential amplifier 32 that amplifies and outputs the differential voltage of two inputs with a predetermined amplification degree. The capacitor 34 and the resistor 36 (the second series circuit is constituted by the capacitor 34 and the resistor 36) input to the non-inverting input terminal of the differential amplifier 32, and the phase of the signal input to the input terminal 42 is changed. First, resistors 38 and 40 (the first series circuit is constituted by these two resistors 38 and 40) that are divided into about ½ and input to the inverting input terminal of the differential amplifier 32. It is configured to include.
[0036]
In the phase shift circuit 30C having such a configuration, when a predetermined AC signal is input to the input terminal 42, the voltage Ei applied to the input terminal 42 is applied to the inverting input terminal of the differential amplifier 32 and the resistor 38. A voltage divided by about 1/2 by the resistor 40 is applied.
[0037]
On the other hand, when an input signal is input to the input terminal 42, a signal appearing at the connection point between the capacitor 34 and the resistor 36 is input to the non-inverting input terminal of the differential amplifier 32. Since an input signal is input to one end of the CR circuit constituted by the capacitor 34 and the resistor 36, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by the CR circuit is the non-inverting input of the differential amplifier 32. Applied to the terminal.
[0038]
The differential amplifier 32 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals in this way with a predetermined amplification degree.
[0039]
FIG. 7 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30C and the voltage appearing in the capacitor or the like.
[0040]
As shown in the figure, the voltage VR2 appearing at both ends of the resistor 36 and the voltage VC2 appearing at both ends of the capacitor 34 are out of phase with each other by 90 °, and the sum of these voltages is the input voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR2 across the resistor 36 and the voltage VC2 across the capacitor 34 change along the circumference of the semicircle shown in FIG.
[0041]
Also, the voltage applied to the inverting input terminal (voltage Ei / 2 across the resistor 40) subtracted in vector from the voltage applied to the non-inverting input terminal of the differential amplifier 32 (voltage VR2 across the resistor 36). Becomes the differential voltage Eo ′. This differential voltage Eo ′ can be represented by a vector having a center point in the semicircle shown in FIG. 7 as a start point and a point on the circumference where the voltage VR2 and the voltage VC2 intersect as an end point. Is equal to the radius Ei / 2 of the semicircle.
[0042]
The output voltage Eo of the differential amplifier 32 is obtained by amplifying the differential voltage Eo ′ with a predetermined amplification degree. Therefore, in the above-described phase shift circuit 30C, the output voltage Eo is constant regardless of the frequency of the input signal, and operates as an all-pass circuit.
[0043]
Further, as apparent from FIG. 7, since the voltage VR2 and the voltage VC2 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR2 is 90 ° as the frequency ω changes from 0 to ∞. From 0 to 0 °. The phase shift amount φ2 of the entire phase shift circuit 30C is twice that and changes from 180 ° to 0 ° depending on the frequency.
[0044]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10C and 30C. Moreover, as shown in FIGS. 5 and 7, the relative phase relationship between the input and output voltages in each of the phase shift circuits 10C and 30C is in the opposite direction, and the two phase shift circuits 10C and 30C at a predetermined frequency. As a result, a signal having a total phase shift amount of 360 ° is output.
[0045]
The output of the subsequent phase shift circuit 30C is taken out as an output of the tuning amplifier 1 from the output terminal 92, and a signal obtained by passing the output of the phase shift circuit 30C through the voltage dividing circuit 60 is not passed through the feedback resistor 70. It is fed back to the input side of the inverting circuit 50. The fed back signal and the signal input via the input resistor 74 are added, and the added signal is input to the preceding phase shift circuit 10C via the non-inverting circuit 50.
[0046]
Further, the feedback formed by including the two phase shift circuits 10C, 30C, the voltage dividing circuit 60 and the feedback resistor 70 shown in FIG. 3 by adjusting the gains of the two phase shift circuits 10C, 30C described above. The open loop gain of the loop is set to be 1 or less. That is, the signal amplitude is attenuated by passing through the voltage dividing circuit 60 and the feedback resistor 70. By compensating for this attenuation by amplification by the phase shift circuits 10C and 30C, the open loop gain of the feedback loop of the entire tuning amplifier can be increased. It is set to be 1 or less. Instead of adjusting each gain of the phase circuits 10C and 30C, the non-inverting circuit 50 may have a gain of 1 or more, and this value may be adjusted.
[0047]
Further, since the output signal of the phase shift circuit 30C before being input to the voltage dividing circuit 60 is extracted from the output terminal 92 of the tuning amplifier 1, the gain of the tuning amplifier 1 itself can be given. The signal amplitude can be amplified simultaneously with the tuning operation.
[0048]
FIG. 8 is a system diagram in which the two phase shift circuits 10C and 30C having the above-described configuration and the whole of the non-inverting circuit 50 and the voltage dividing circuit 60 connected to the front and rear thereof are replaced with a circuit having a transfer function K1. A feedback resistor 70 having a resistor R0 is connected in parallel with a circuit having a transfer function K1, and an input resistor 74 having a resistance value (nR0) n times that of the feedback resistor 70 is connected in series. FIG. 9 is a system diagram in which the system shown in FIG. 8 is converted by Miller's theorem, and the transfer function A of the entire system after conversion is
A = Vo / Vi = K1 / {n (1-K1) +1} (1)
Can be expressed as
[0049]
By the way, the transfer function K2 of the preceding phase shift circuit 10C is the time constant of the CR circuit composed of the variable resistor 16 and the capacitor 14 as T₁(T is assumed that the resistance value of the variable resistor 16 is R and the capacitance of the capacitor 14 is C)₁= CR)
K2 = a₁(1-T₁s) / (1 + T₁s) (2)
It becomes. Where s = jω, a₁Is the gain of the phase shift circuit 10C and takes a value of 1 or more.
[0050]
Further, the transfer function K3 of the phase shift circuit 30C at the subsequent stage is obtained by setting the time constant of the CR circuit composed of the capacitor 34 and the resistor 36 to T₂(T is assumed that the resistance value of the resistor 36 is R and the capacitance of the capacitor 34 is C)₂= CR)
K3 = -a₂(1-T₂s) / (1 + T₂s) (3)
It becomes. Where a₂Is the gain of the phase shift circuit 30C and takes a value of 1 or more.
[0051]
The gain of the voltage dividing circuit 60 is set to a₃(≦ 1), the gain of the non-inverting circuit 50 is a₄And the gain a of the two phase shift circuits 10C and 30C in order to compensate for the signal attenuation and the like by the voltage dividing circuit 60 and the non-inverting circuit 50.₁, A₂When the non-inverting circuit 50, the phase shift circuits 10C and 30C, and the voltage dividing circuit 60 are connected in cascade, the overall transfer function K1 is
K1 =-{1+ (Ts)²-2Ts} / {1+ (Ts)²+ 2Ts} (4)
It becomes. In order to simplify the calculation, the time constant T of each phase shift circuit₁, T₂  Both are T. Substituting this equation (4) into the above equation (1),

It becomes.
[0052]
According to the equation (5), it can be seen that when ω = 0 (DC region), A = −1 / (2n + 1), and the maximum attenuation is given. Further, it can be seen that even when ω = ∞, A = −1 / (2n + 1), which gives the maximum attenuation. Further, the tuning point of ω = 1 / T (when the time constants of the phase shift circuits are different, ω = 1 / √ (T₁・ T₂  It can be seen that A = 1 at the tuning point)) and is independent of the resistance ratio n of the feedback resistor 70 and the input resistor 74. In other words, as shown in FIG. 10, even if the value of n is changed, the tuning point is not shifted and the attenuation at the tuning point is not changed.
[0053]
In addition, the time constant of the CR circuit included in the phase shift circuit 10C can be changed by changing the resistance value of the variable resistor 16 in the preceding phase shift circuit 10C, and the tuning frequency ω can be arbitrarily changed within a certain range. Can be made.
[0054]
When φ1 and φ2 shown in FIGS. 5 and 7 are obtained from the equation (2) or (3),
φ1 = tan {2ωT₁/ (1-ω²T₁ ²)} (6)
φ2 = -tan {2ωT₂/ (1-ω²T₂ ²)} (7)
It becomes. Here, with reference to φ1 shown in FIG. 5, the sign of φ2 shown in FIG. 7 is represented as “−”.
[0055]
For example, T₁= T₂In the case of (= T), when ω = 1 / T, the total phase shift amount by the two phase shift circuits 10C and 30C is 360 °, and the above-described tuning operation is performed. At this time, φ1 = 90 °, φ2 = -90 °.
[0056]
In FIG. 7, the output voltage Eo is shown to have a phase that is more advanced than the voltage Ei in phase with the input voltage of the preceding phase shift circuit 30C. Is always in a delayed phase.
[0057]
FIG. 11 is a diagram illustrating a phase relationship between signals input to and output from the two phase shift circuits 10C and 30C, in which a signal having a frequency equal to the tuning frequency is input to the previous phase shift circuit 10C. As an example, the time constant T of each phase shift circuit 10C, 30C₁, T₂  The case where is equal is shown.
[0058]
As shown in FIG. 11A, the preceding phase shift circuit 10C performs a phase shift of φ1 (= 90 °) on the input signal S1 and outputs an output signal S2.
[0059]
Further, as shown in FIG. 11B, the rear-stage phase shift circuit 30C shifts the phase of φ2 with respect to the input signal S2 (common with the output signal of the front-stage phase shift circuit 10C), and outputs the output signal S3. Is output. Here, although the output signal S3 appears to be 90 ° out of phase with respect to the input signal S2, in reality, the signal is inverted and further delayed by 90 °. A phase shift of '= 270 ° is performed.
[0060]
Therefore, when the two phase shift circuits 10C and 30C are connected in cascade, as shown in FIG. 11C, the above-described φ1 = 90 ° and φ2 ′ = 270 ° are added to form a total of 360 °. A phase shift is performed.
[0061]
From another viewpoint, in the signal input to the tuning amplifier 1, frequency components whose total phase shift amount by the two phase shift circuits 10C and 30C is other than 360 ° are attenuated when circulating through the closed loop, Only frequency components with a total shift amount of 360 ° are selected and output, and a predetermined tuning operation is performed.
[0062]
According to the tuning amplifier 1 described above, even if the resistance value of the input resistor 74 is varied to change the resistance ratio n between the feedback resistor 70 and the input resistor 74, the tuning frequency and the gain at the time of tuning are constant, and only the maximum attenuation amount is obtained. Can be changed. In order to change the resistance ratio between the feedback resistor 70 and the input resistor 74, at least one of them may be formed by a variable resistor.
[0063]
Further, since the time constant of the CR circuit can be changed by changing the resistance value of the variable resistor constituting the CR circuit in the phase shift circuit 10C, 1 / √ (T₁T₂) Can also be varied within a certain range.
[0064]
Further, since the maximum attenuation is determined by the resistance ratio n of the feedback resistor 70 and the input resistor 74, when the tuning frequency is changed by changing the resistance value of the variable resistor constituting the CR circuit in the phase shift circuit 10C. Even if it exists, this maximum attenuation is not affected, and the tuning frequency and the maximum attenuation can be adjusted without interfering with each other.
[0065]
Further, the voltage dividing circuit 60 is connected to the subsequent stage of the phase shift circuit 30C, and the divided output from the voltage dividing circuit 60 is used as a feedback signal, and the signal before voltage division is taken out as the output of the tuning amplifier 1, thereby tuning. Signal amplification can be performed simultaneously with operation.
[0066]
Further, the tuning amplifier 1 described above is configured by combining a differential amplifier, a capacitor, and a resistor, and any component can be formed on a semiconductor substrate. Therefore, tuning frequency and maximum attenuation can be adjusted. It is easy to form the entire amplifier 1 on a semiconductor substrate to form an integrated circuit.
[0067]
Thus, the tuning amplifier 1 included in the tuning mechanism described above can set the tuning frequency according to the control voltage from the outside, and the output amplitude is constant even when the tuning frequency is changed. By adopting a PLL configuration generally used for frequency control of an oscillator, tuning frequency fluctuation can be easily prevented and a tuning output with a stable frequency can be obtained.
[0068]
Further, since the tuning frequency can be changed following the frequency of the reference signal by changing the frequency of the reference signal generated by the oscillator 3, the tuning control described above is applied to a radio receiver having a plurality of reception frequencies. A scheme can also be applied. In this case, since the tuning frequency can be changed arbitrarily and accurately, the receiver can be configured without using the conventionally used superheterodyne system.
[0069]
Further, most of the tuning mechanisms shown in FIG. 1 can be formed on a semiconductor substrate, and even when the element constant of each element formed on the semiconductor substrate changes depending on the manufacturing lot or operating temperature. The tuning frequency of the tuning amplifier 1 can be accurately adjusted to a predetermined frequency.
[0070]
By the way, the tuning amplifier 1 included in the tuning mechanism shown in FIG. 1 includes each phase shift circuit 10C, 30C including a CR circuit, but a phase shift circuit in which the CR circuit is replaced with an LR circuit composed of a resistor and an inductor. It is also possible to configure a tuning amplifier.
[0071]
FIG. 12 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and shows a configuration that can replace the phase shift circuit 10C in the previous stage of the tuning amplifier 1 shown in FIG. The phase shift circuit 10L shown in the figure is a differential amplifier 12 that amplifies and outputs a differential voltage of two inputs at a predetermined amplification degree, and shifts the phase of a signal input to the input terminal 22 by a predetermined amount to perform differential operation. Inverting the differential amplifier 12 by dividing the voltage level by about 1/2 without changing the phase of the signal input to the inductor 17 and the variable resistor 16 input to the non-inverting input terminal of the amplifier 12 and the input terminal 22. It includes resistors 18 and 20 that are input to the input terminal. The capacitor 19 connected in series to the inductor 17 is for DC current blocking, and its impedance is set to be extremely small at the operating frequency, that is, has a large capacitance.
[0072]
The phase shift circuit 10L has a configuration in which the CR circuit including the variable resistor 16 and the capacitor 14 in the phase shift circuit 10C illustrated in FIG. 4 is replaced with an LR circuit including the inductor 17 and the variable resistor 16.
[0073]
FIG. 13 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10L and the voltage appearing in the inductor or the like. Similar to the phase shift circuit 10C shown in FIG. 4, the voltage applied to the non-inverting input terminal of the differential amplifier 12 (the voltage VR3 across the variable resistor 16) to the voltage applied to the inverting input terminal (both ends of the resistor 20). The difference voltage Eo ′ is obtained by subtracting the voltage Ei / 2) in vector. This differential voltage Eo ′ can be expressed by a vector whose starting point is the center point in the semicircle shown in FIG. 13 and whose end point is one point on the circumference where the voltage VR3 and the voltage VL1 across the inductor 17 intersect. And its size is equal to the radius Ei / 2 of the semicircle. The output voltage Eo of the differential amplifier 12 is obtained by amplifying the differential voltage Eo ′ with a predetermined amplification degree. The phase shift circuit 10L has an output voltage Eo that is constant regardless of the frequency of the input signal, and is an all-pass circuit. Works as.
[0074]
The phase shift amount φ3 of the phase shift circuit 10L shown in FIG. 13 is the time constant of the LR circuit composed of the inductor 17 and the variable resistor 16 as T₁(If the inductance of the inductor 17 is L and the resistance value of the variable resistor 16 is R, T₁= L / R), it is the same as φ1 shown in the above-described equation (6).
[0075]
FIG. 14 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit, and shows a configuration that can be replaced with a phase shift circuit 30C in the subsequent stage of the tuning amplifier 1 shown in FIG. The phase shift circuit 30L shown in the figure is a differential amplifier 32 that amplifies and outputs a differential voltage of two inputs with a predetermined amplification degree, and shifts the phase of a signal input to the input terminal 42 by a predetermined amount to perform a differential operation. The resistor 36 and the inductor 37 that are input to the non-inverting input terminal of the amplifier 32 and the voltage level of the resistor 36 and the inductor 37 that are input to the input terminal 42 are divided by about 1/2 without changing the phase of the signal. Resistors 38 and 40 are input to the terminals. Note that the capacitor 39 connected in series to the inductor 37 is for blocking direct current, and its impedance is set to be extremely small at the operating frequency, that is, has a large capacitance.
[0076]
The phase shift circuit 30L has a configuration in which the CR circuit including the capacitor 34 and the resistor 36 in the phase shift circuit 30C illustrated in FIG. 6 is replaced with an LR circuit including the resistor 36 and the inductor 37.
[0077]
FIG. 15 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30L and the voltage appearing in the inductor or the like. Similar to the phase shift circuit 30C shown in FIG. 6, the voltage applied to the non-inverting input terminal of the differential amplifier 32 (the voltage VL2 across the inductor 37) to the voltage applied to the inverting input terminal (the voltage across the resistor 40). The difference voltage Eo ′ is obtained by subtracting Ei / 2) in a vector manner. This differential voltage Eo ′ can be expressed by a vector whose starting point is the center point in the semicircle shown in FIG. 15 and whose end point is one point on the circumference where the voltage VL2 and the voltage VR4 across the resistor 36 intersect. And its size is equal to the radius Ei / 2 of the semicircle. The output voltage Eo of the differential amplifier 32 is obtained by amplifying the differential voltage Eo 'with a predetermined amplification degree. The phase shift circuit 30L has an all-pass circuit in which the output voltage Eo is constant regardless of the frequency of the input signal. Works as.
[0078]
The phase shift amount φ4 of the phase shift circuit 30L shown in FIG. 15 is the time constant of the LR circuit composed of the resistor 36 and the inductor 37 as T₂(If the resistance value of the resistor 36 is R and the inductance of the inductor 37 is L, T₂= L / R), it is the same as φ2 shown in the above equation (7).
[0079]
Thus, each of the phase shift circuit 10L shown in FIG. 12 and the phase shift circuit 30L shown in FIG. 14 is equivalent to the phase shift circuits 10C and 30C shown in FIG. 4 or FIG. In the tuned amplifier 1, the preceding phase shift circuit 10C can be replaced with the phase shift circuit 10L shown in FIG. 12, and the subsequent phase shift circuit 30C can be replaced with the phase shift circuit 30L shown in FIG.
[0080]
In each of the two phase shift circuits 10L and 30L described above, the tuning frequency is determined by the time constant of the LR circuit included in each phase shift circuit 10L and 30L. Each time constant T is, for example, L / R The tuning frequency ω is proportional to 1 / T = R / L. Here, the inductor constituting the LR circuit can be realized by forming a spiral conductor on a semiconductor substrate by a photolithography method or the like, but by using the inductor thus formed, the entire tuning amplifier can be realized. Can be integrated on a semiconductor substrate.
[0081]
However, in this case, since the inductance of the inductor becomes extremely small, the tuning frequency becomes high. From another viewpoint, the tuning frequency of the tuning amplifier is proportional to, for example, the reciprocal R / L of the time constant of the LR circuit in each of the phase shift circuits 10L and 30L, in which the inductance L is reduced by integration or the like. Therefore, the tuning frequency can be easily increased by integrating the entire tuning amplifier including the two phase shift circuits 10L and 30L.
[0082]
In the tuning amplifier 1 shown in FIG. 3, any one of the phase shift circuits 10C and 30C may be replaced with the phase shift circuits 10L and 30L shown in FIG. In particular, when such a tuning amplifier as a whole is integrated, so-called temperature compensation that prevents fluctuations in the tuning frequency due to temperature changes becomes possible. In other words, the time constant T of the CR circuit is CR, and the time constant T of the LR circuit is L / R, and the resistance value R is divided into a numerator and a denominator in each, so that the CR circuit and the LR circuit are configured by integration. In the case where the resistor to be formed is formed of a semiconductor material, there is an effect of suppressing the fluctuation of the tuning frequency with respect to the temperature change of each of these resistors.
[0083]
In addition, the tuning amplifier 1 included in the tuning mechanism shown in FIG. 1 is configured to include two phase shift circuits having different phase shift directions, but by combining two phase shift circuits having basically the same configuration. A tuned amplifier can also be constructed.
[0084]
FIG. 16 is a circuit diagram showing another configuration of the tuning amplifier. The tuning amplifier 1A shown in the figure includes a phase inverting circuit 80 that inverts and outputs the phase of the input AC signal, and shifts the phase of the AC signal that is input by a predetermined amount to add a total at a predetermined frequency. Two phase shift circuits 10C and 10C 'for performing a phase shift of 180 °, a voltage dividing circuit 60 comprising resistors 62 and 64 provided further downstream of the subsequent phase shift circuit 10C', a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times the resistance value of the feedback resistor 70), and the divided output (feedback signal) of the voltage dividing circuit 60 and the input terminal 90 are connected to each other. And an adding circuit for adding an input signal (input signal) at a predetermined ratio.
[0085]
The detailed configuration of the front-stage phase shift circuit 10C and the phase relationship of the input / output signals are as described with reference to FIGS. 4 and 5. The rear-stage phase shift circuit 10C ′ is a variable resistor in the front-stage phase shift circuit 10C. 16 is replaced by a resistor 15 having a fixed resistance value. Therefore, at a predetermined frequency, the total amount of phase shift by the two phase shift circuits 10C and 10C ′ is 180 °.
[0086]
The phase inverting circuit 80 connected in front of the two phase shift circuits 10C and 10C 'inverts the phase of the input AC signal. For example, the grounded emitter circuit, the source grounded circuit, the operational amplifier and the resistor This is realized by a circuit combining the above.
[0087]
Thus, at a predetermined frequency, the phase is shifted by 180 ° by the two phase shift circuits 10C and 10C ′, and the phase is inverted by the phase inversion circuit 80 connected to the preceding stage. The total phase shift amount is 360 °.
[0088]
The output of the subsequent phase shift circuit 10C ′ is taken out from the output terminal 92 as the output of the tuning amplifier 1A. And fed back to the input side of the phase inverting circuit 80. The signal fed back and the signal inputted via the input resistor 74 are added, and the added signal is inputted to the phase inverting circuit 80.
[0089]
In this way, the output of the voltage dividing circuit 60 is fed back to the input side of the phase inverting circuit 80 through the feedback resistor 70, and the signal input through the input resistor 74 is added to this feedback signal, and two phase shifts are made. By adjusting the gains of the circuits 10C and 10C ′ to compensate for loss and the like generated at the connection between the voltage dividing circuit 60 and the feedback resistor 70 and the input resistor 74, the open loop gain of the feedback loop is set to 1 or less. Tuning operation and amplification operation similar to those of the tuning amplifier 1 shown in FIG. Instead of adjusting the gains of the phase shift circuits 10C and 10C ′, the gain of the phase inversion circuit 80 may be adjusted.
[0090]
FIG. 17 is a circuit diagram showing another configuration of the tuning amplifier. The tuning amplifier 1B shown in the figure includes a phase inverting circuit 80 that inverts and outputs the phase of the input AC signal, and shifts the phase of the AC signal that is input by a predetermined amount to add a total at a predetermined frequency. Two phase shift circuits 30C ′ and 30C that perform a phase shift of 180 °, a voltage dividing circuit 60 including resistors 62 and 64 provided in a further subsequent stage of the subsequent phase shift circuit 30C, a feedback resistor 70, and an input resistor 74 (The input resistor 74 is assumed to have a resistance value that is n times the resistance value of the feedback resistor 70), and the divided output (feedback signal) of the voltage dividing circuit 60 and the input terminal 90 are input. And an adding circuit for adding the signal (input signal) to be added at a predetermined ratio.
[0091]
The detailed configuration of the rear-stage phase shift circuit 30C and the phase relationship of the input / output signals are as described with reference to FIGS. 6 and 7. The front-stage phase shift circuit 30C ′ is a resistor 36 in the rear-stage phase shift circuit 30C. Is replaced with a variable resistor 35 whose resistance value can be changed by a gate voltage (control voltage) applied from the outside. Therefore, at a predetermined frequency, the sum of the phase shift amounts of the two phase shift circuits 30C ′ and 30C as a whole is 180 °.
[0092]
As described above, even when the two phase shift circuits 30C ′ and 30C described above are used, the phase is shifted by 180 ° by the two phase shift circuits 30C ′ and 30C at a predetermined frequency, and further connected to the preceding stage. The phase is inverted by the phase inverting circuit 80, and the total amount of phase shift by these three circuits is 360 °.
[0093]
Therefore, the above-described tuning amplifier 1B feeds back the output of the voltage dividing circuit 60 to the input side of the phase inverting circuit 80 via the feedback resistor 70, and adds the signal input via the input resistor 74 to this feedback signal. The gains of the two phase shift circuits 30C ′ and 30C are adjusted to compensate for loss or the like generated at the connection portion of the voltage dividing circuit 60 or the feedback resistor 70 and the input resistor 74, and the open loop gain of the feedback loop is set to 1 or less. Thus, the same tuning operation and amplification operation as the tuning amplifier 1A shown in FIG. 16 can be performed.
[0094]
16 and 17, both of the tuning amplifiers 1A and 1B include two phase shift circuits including a CR circuit, but at least one of them may include an LR circuit.
[0095]
Specifically, in the tuning amplifier 1A shown in FIG. 16, the phase shift circuit 10C at the front stage is the phase shift circuit 10L shown in FIG. 12, or the phase shift circuit 10C ′ at the rear stage is the phase shift circuit shown in FIG. Instead of the variable resistor 16 in 10L, a phase shift circuit 10L ′ using a resistor 15 having a fixed resistance value is used. Alternatively, both of the two phase shift circuits 10C and 10C ′ are replaced with the above-described phase shift circuits 10L and 10L ′.
[0096]
In the tuning amplifier 1B shown in FIG. 17, a phase shift circuit 30L ′ using a variable resistor 35 instead of the resistor 36 in the phase shift circuit 30L shown in FIG. Subsequent phase shift circuit 30C is replaced with phase shift circuit 30L shown in FIG. Alternatively, both of the two phase shift circuits 30C ′ and 30C are replaced with the above-described phase shift circuits 30L ′ and 30L.
[0097]
In particular, when both of the phase shift circuits are replaced with phase shift circuits having LR circuits, it is easy to increase the tuning frequency by integrating the entire tuning amplifier, and one of the phase shift circuits has an LR circuit. When the phase shift circuit is used, so-called temperature compensation that prevents fluctuations in the tuning frequency due to temperature changes is possible.
[0098]
By the way, the various tuning amplifiers described above are configured to include a non-inverting circuit and two phase shift circuits or a phase inverting circuit and two phase shift circuits, and the whole of the three circuits connected when focusing on the phase shift. Thus, a predetermined tuning operation is performed by setting the total phase shift amount to 360 ° at a predetermined frequency. Therefore, focusing only on the phase shift amount, there is a certain degree of freedom in which of the two phase shift circuits is used in the preceding stage, or in what order the three circuits described above are connected. Connection order can be determined.
[0099]
FIG. 18 is a diagram illustrating a connection state in the case where a tuning amplifier is configured by combining two phase shift circuits and the non-inverting circuit 50. In these figures, the feedback impedance element 70a and the input impedance element 74a are for adding the output signals and input signals of the respective tuning amplifiers at a predetermined ratio, and most commonly in FIG. As shown, a feedback resistor 70 is used as the feedback impedance element 70a, and an input resistor 74 is used as the input impedance element 74a.
[0100]
However, since the feedback impedance element 70a and the input impedance element 74a may be added without changing the phase relationship of the signals input to the respective elements, both the feedback impedance element 70a and the input impedance element 74a are formed by capacitors. A ratio of the real number and the imaginary number of the impedance may be adjusted at the same time by combining resistors and capacitors.
[0101]
Further, the configuration of the tuning amplifier shown in FIG. 18 and later-described FIG. 19 shows a configuration in which the voltage dividing circuit 60 is omitted, but actually, the voltage dividing circuit 60 is connected to the subsequent stage of the final stage circuit. The signal after the voltage division may be used as a feedback signal and the signal before the voltage division may be taken out as an output.
[0102]
FIG. 18A shows a configuration in which a non-inverting circuit 50 is disposed after the two phase shift circuits. As described above, when the non-inverting circuit 50 is disposed in the subsequent stage, a large output current can be taken out by providing the non-inverting circuit 50 with the function of an output buffer.
[0103]
FIG. 18B shows a configuration in which a non-inverting circuit 50 is arranged between two phase shift circuits. In this way, when the non-inverting circuit 50 is arranged in the middle, mutual interference between the front-stage phase shift circuit and the rear-stage phase shift circuit can be completely prevented.
[0104]
FIG. 18C shows a configuration in which a non-inverting circuit 50 is arranged further upstream of the two phase shift circuits, and corresponds to the tuning amplifier 1 shown in FIG. As described above, when the non-inverting circuit 50 is arranged in the first stage, it is possible to prevent a loss or the like generated at the connection portion between the feedback impedance element 70 a or the input impedance element 74 a and the non-inverting circuit 50.
[0105]
Similarly, FIG. 19 is a diagram illustrating a connection state when a tuning amplifier is configured by combining two phase shift circuits and a phase inversion circuit.
[0106]
FIG. 19A shows a configuration in which a phase inverting circuit 80 is disposed after the two phase shift circuits. As described above, when the phase inverting circuit 80 is disposed in the subsequent stage, a large output current can be extracted by providing the phase inverting circuit 80 with the function of an output buffer.
[0107]
FIG. 19B shows a configuration in which a phase inversion circuit 80 is disposed between two phase shift circuits. In this case, mutual interference between the two phase shift circuits can be completely prevented. . FIG. 19C shows a configuration in which a phase inverting circuit 80 is arranged further upstream of the two phase shift circuits, and corresponds to the tuning amplifier 1A shown in FIG. 16 or the tuning amplifier 1B shown in FIG. ing. In this case, it is possible to prevent a loss or the like generated at the connection portion between the feedback impedance element 70a or the input impedance element 74a and the phase inverting circuit 80.
[0108]
The present invention is not limited to the various embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
[0109]
For example, although the variable resistor 16 included in the above-described various tuning amplifiers is configured as a junction type FET, a MOS type FET may be used. The variable resistor 16 described above may be configured by connecting a p-channel FET and an n-channel FET in parallel. By combining the two FETs to form the variable resistor, the nonlinear region of the FET can be improved, so that the distortion of the tuning output can be reduced.
[0110]
In the tuning amplifier 1 and the like described above, a variable resistor is included in one of the two phase shift circuits, but a variable resistor is included in both phase shift circuits (for example, the resistor 36 in FIG. 3 is replaced with a variable resistor). The tuning frequency may be changed. When variable resistors are included in the two phase shift circuits, there is an advantage that a variable range of the tuning frequency can be set large by simultaneously changing these resistance values.
[0111]
In a phase shift circuit having a CR circuit, the time constant of the CR circuit is changed by changing the capacitance of the capacitor instead of changing the resistance value of the resistor constituting the CR circuit in each phase shift circuit. Thus, the phase shift amount of the phase shift circuit, that is, the tuning frequency of the tuning amplifier may be changed.
[0112]
Specifically, the capacitor constituting the CR circuit (for example, the capacitor 14 shown in FIG. 4) is replaced with a variable capacitance diode and a direct current blocking capacitor. In the variable capacitance diode, the capacitance between the anode and the cathode is changed by changing the applied reverse bias voltage. By constructing a CR circuit by connecting such variable capacitance diodes and resistors in series, the time constant of the CR circuit can be changed by changing the applied control voltage (reverse bias voltage). The amount of phase shift can be changed.
[0113]
Further, instead of the variable capacitance diode, an FET that can be changed within a certain range according to the control voltage applied to the gate may be used as the variable capacitance element.
[0114]
In the various tuning amplifiers described above, the voltage dividing circuit 60 is inserted between the phase shift circuit 30C and the like at the subsequent stage and the output terminal 92, and the signal divided by the voltage dividing circuit 60 is used as a feedback signal. The voltage dividing circuit 60 may be omitted. In this case, the output of the subsequent phase shift circuit 30C or the like is used as it is as a feedback signal, but omitting the voltage dividing circuit 60 means that the voltage dividing ratio of the voltage dividing circuit 60 is set to 1. Considering this, it can be considered that a tuning amplifier in which the voltage dividing circuit 60 is omitted is also included in the various tuning amplifiers shown in FIG.
[0115]
【The invention's effect】
As is clear from the description based on the above embodiments, the tuning control system of the present invention can set the tuning frequency according to the control voltage from the outside, and can output even when the tuning frequency is changed. A tuning amplifier having a constant amplitude is used, and a PLL configuration generally used for frequency control of an oscillator is used, so that a tuning output with a stable frequency can be obtained by easily preventing fluctuations in the tuning frequency.
[0116]
Further, since the tuning frequency can be changed following the frequency by changing the frequency of the reference frequency signal, the above-described tuning control method can be applied to a radio receiver having a plurality of reception frequencies. The tuning frequency can be changed arbitrarily and accurately.
[0117]
In addition, most of the circuits to which the tuning control method is applied can be formed on a semiconductor substrate, and even when the element constant of each element formed on the semiconductor substrate changes depending on the manufacturing lot or operating temperature, etc. The tuning frequency of the tuning amplifier can be accurately adjusted to a predetermined frequency.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a tuning mechanism that is one embodiment to which a tuning control system of the present invention is applied.
FIG. 2 is a diagram showing a specific configuration of an oscillator included in the tuning mechanism shown in FIG.
3 is a circuit diagram showing a detailed configuration of a tuning amplifier shown in FIG. 1. FIG.
4 is a circuit diagram showing an extracted configuration of the previous phase shift circuit shown in FIG. 3; FIG.
FIG. 5 is a vector diagram showing the relationship between the input / output voltage of the previous phase shift circuit and the voltage appearing in a capacitor or the like.
6 is a circuit diagram showing an extracted configuration of the subsequent phase shift circuit shown in FIG. 3; FIG.
FIG. 7 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit and the voltage appearing in a capacitor or the like.
FIG. 8 is a circuit diagram in which two phase shift circuits are entirely replaced with a circuit having a predetermined transfer function.
FIG. 9 is a circuit diagram obtained by converting the configuration shown in FIG. 8 by the mirror theorem.
10 is a diagram illustrating a tuning characteristic of the tuning amplifier illustrated in FIG. 3;
FIG. 11 is a diagram illustrating a phase relationship between signals input to and output from two phase shift circuits included in the tuning amplifier.
12 is a circuit diagram showing a configuration of a phase shift circuit that can replace the phase shift circuit shown in FIG. 4; FIG.
13 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 12 and voltages appearing in an inductor or the like.
14 is a circuit diagram showing a configuration of a phase shift circuit that can replace the phase shift circuit shown in FIG. 6;
15 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 14 and voltages appearing in an inductor or the like.
FIG. 16 is a circuit diagram showing another configuration of a tuning amplifier.
FIG. 17 is a circuit diagram showing another configuration of a tuning amplifier.
FIG. 18 is a diagram showing a connection form of a phase shift circuit and a non-inverting circuit included in a tuning amplifier.
FIG. 19 is a diagram illustrating a connection form of a phase shift circuit and a phase inversion circuit included in a tuning amplifier.
[Explanation of symbols]
1 Tuning amplifier
2 Phase comparator (PD)
3 Oscillator (OSC)
4 Charge pump (CP)
5 Low-pass filter (LPF)
10C, 30C phase shift circuit
12, 32 Differential amplifier
14, 34 capacitors
16 Variable resistance
18, 20, 36, 38, 40 Resistance
50 Non-inverting circuit
70 Feedback resistance
74 Input resistance
90 input terminals
92 Output terminal
60 voltage divider circuit

Claims (6)

A tuning amplifier that selects and outputs one in the vicinity of the tuning frequency set according to the control voltage from the input signal, and a phase comparator that performs frequency comparison between a predetermined reference frequency signal and the output signal of the tuning amplifier In a tuning control system having a charge pump having an output voltage corresponding to a comparison result by the phase comparator, and a low-pass filter that extracts a direct current component from the output of the charge pump and applies it to the tuning amplifier as the control voltage,
The tuning amplifier is:
An adder circuit that includes an input impedance element to which the input signal is input to one end and a feedback impedance element to which the feedback signal is input to one end, and adds the input signal and the feedback signal;
The first and second resistors have substantially the same resistance value, and include a first series circuit to which an input AC signal is applied to both ends, a reactance element such as a capacitor or an inductor, and a third resistor. A time constant that can be changed in accordance with the control voltage, and a second series circuit in which the AC signal is applied to both ends, and the first and second resistors that constitute the first series circuit. A differential amplifier that amplifies and outputs a difference between a potential at a connection point and the reactance element constituting the second series circuit and a potential at the connection point of the third resistor at a predetermined amplification degree, Two phase shift circuits with opposite phase shift directions;
A voltage dividing circuit that divides the input AC signal at a predetermined voltage dividing ratio;
Each of the two phase shift circuits and the voltage dividing circuit are connected in cascade, and a signal added by the adder circuit is input to a first stage circuit among the plurality of cascaded circuits. A tuning control system characterized in that a signal output from a circuit at the final stage is input to the one end of the feedback impedance element as the feedback signal, and a signal before input to the voltage dividing circuit is extracted as a tuning output. A tuning amplifier that selects and outputs one in the vicinity of the tuning frequency set according to the control voltage from the input signal, and a phase comparator that performs frequency comparison between a predetermined reference frequency signal and the output signal of the tuning amplifier In a tuning control system having a charge pump having an output voltage corresponding to a comparison result by the phase comparator, and a low-pass filter that extracts a direct current component from the output of the charge pump and applies it to the tuning amplifier as the control voltage,
The tuning amplifier is:
An adder circuit that includes an input impedance element to which the input signal is input to one end and a feedback impedance element to which the feedback signal is input to one end, and adds the input signal and the feedback signal;
The first and second resistors have substantially the same resistance value, and include a first series circuit to which an input AC signal is applied to both ends, a reactance element such as a capacitor or an inductor, and a third resistor. The time constant can be changed by the control voltage, and the potential of the connection point between the first and second resistors constituting the first series circuit, and the second series circuit in which the AC signal is applied to both ends. And a differential amplifier that amplifies and outputs the difference between the reactance element constituting the second series circuit and the potential of the connection point of the third resistor with a predetermined amplification degree, and the phase shift direction is mutually Two opposite phase-shift circuits,
A non-inverting circuit that outputs the input AC signal without changing the phase;
A voltage dividing circuit that divides the input AC signal at a predetermined voltage dividing ratio;
Each of the two phase shift circuits, the non-inverting circuit, and the voltage dividing circuit is cascade-connected, and the first circuit among the plurality of cascade-connected circuits is added by the adder circuit. A signal is input, a signal output from a circuit at the final stage is input to the one end of the feedback impedance element as the feedback signal, and a signal before input to the voltage dividing circuit is extracted as a tuning output. Tuning control method. A tuning amplifier that selects and outputs one in the vicinity of the tuning frequency set according to the control voltage from the input signal, and a phase comparator that performs frequency comparison between a predetermined reference frequency signal and the output signal of the tuning amplifier In a tuning control system having a charge pump having an output voltage corresponding to a comparison result by the phase comparator, and a low-pass filter that extracts a direct current component from the output of the charge pump and applies it to the tuning amplifier as the control voltage,
The tuning amplifier is:
An adder circuit that includes an input impedance element to which the input signal is input to one end and a feedback impedance element to which the feedback signal is input to one end, and adds the input signal and the feedback signal;
The first and second resistors have substantially the same resistance value, and include a first series circuit to which an input AC signal is applied to both ends, a reactance element such as a capacitor or an inductor, and a third resistor. The time constant can be changed by the control voltage, and the potential of the connection point between the first and second resistors constituting the first series circuit, and the second series circuit in which the AC signal is applied to both ends. And a differential amplifier that amplifies and outputs the difference between the reactance element constituting the second series circuit and the potential of the connection point of the third resistor with a predetermined amplification degree, and the phase shift direction is mutually Two phase-shift circuits that are the same,
A phase inversion circuit that inverts and outputs the phase of the input AC signal;
A voltage dividing circuit that divides the input AC signal at a predetermined voltage dividing ratio;
Each of the two phase shift circuits, the phase inverting circuit, and the voltage dividing circuit is cascade-connected, and the first circuit among the plurality of cascade-connected circuits is added by the adder circuit. A signal is input, a signal output from a circuit at the final stage is input to the one end of the feedback impedance element as the feedback signal, and a signal before input to the voltage dividing circuit is extracted as a tuning output. Tuning control method. In any one of Claims 1-3,
A tuning control system, wherein the third resistor included in at least one of the two phase shift circuits is formed by a variable resistor whose resistance value is set according to the control voltage. In claim 4,
The variable resistor is formed by connecting a p-channel FET and an n-channel FET in parallel, and the channel resistance of each FET connected in parallel is set by applying the control voltage to the gate. Tuning control method. In any one of Claims 1-5,
A tuning control system characterized in that component parts are integrally formed on a semiconductor substrate.

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