JP3628402B2 - Tuning amplifier - Google Patents

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となる。
【００５８】
この（５）式によれば、ω＝０（直流の領域）のときにＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。また、ω＝∞のときにもＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。さらに、ω＝１／Ｔの同調点（各移相回路の時定数が異なる場合には、ω＝１／√（Ｔ_１ ・Ｔ_２ ）の同調点）においてはＡ＝１であって帰還抵抗７０と入力抵抗７４の抵抗比ｎに無関係であることがわかる。換言すれば、図８に示すように、ｎの値を変化させても同調点がずれることなく、かつ同調点の減衰量も変化しない。
【００５９】
しかも、後段の移相回路３０Ｃ内の可変抵抗３６の抵抗値を変えることにより、可変抵抗３６とキャパシタ３４からなるＣＲ回路の時定数Ｔ_２ を変化させることができ、同調周波数ωをある範囲で任意に変化させることができる。
【００６０】
なお、（２）式あるいは（３）式から図３、図５に示したφ１ 、φ２ を求めると、
φ１ ＝ｔａｎ｛２ωＴ_１ ／（１−ω^２ Ｔ_１ ^２ ）｝ ・・・（６）
φ２ ＝−ｔａｎ｛２ωＴ_２ ／（１−ω^２ Ｔ_２ ^２ ）｝ ・・・（７）
となる。なお、ここでは図３に示したφ１ を基準に考えて、図５に示したφ２ の符号を「−」として表した。
【００６１】
例えばＴ_１ ＝Ｔ_２ （＝Ｔ）の場合には、ω＝１／Ｔのときに２つの移相回路１０Ｃ、３０Ｃによる位相シフト量の合計が３６０°となって上述した同調動作が行われ、このときφ１ ＝９０°、φ２ ＝−９０°となる。
【００６２】
ところで、図５では前段の移相回路３０Ｃの入力電圧と同相の電圧Ｅｉ よりも出力電圧Ｅｏ の方が位相が進んでいるように図示したが、実際には入力信号を基準に考えると出力信号は常に遅れ位相の状態にある。
【００６３】
図９は、２つの移相回路１０Ｃ、３０Ｃに入出力される信号間の位相関係を示す図であり、前段の移相回路１０Ｃに同調周波数と等しい周波数の信号が入力された場合であって、一例として各移相回路１０Ｃ、３０Ｃの時定数Ｔ_１ 、Ｔ_２ が等しい場合が示されている。
【００６４】
前段の移相回路１０Ｃは、図９（Ａ）に示すように、入力信号Ｓ１に対してφ１ （＝９０°）の位相シフトを行って、出力信号Ｓ２を出力している。
【００６５】
また、後段の移相回路３０Ｃは、図９（Ｂ）に示すように、入力信号Ｓ２（前段の移相回路１０Ｃの出力信号と共通）に対してφ２ の位相シフトを行って、出力信号Ｓ３を出力している。ここで、出力信号Ｓ３は入力信号Ｓ２に対して、一見９０°位相が進んでいるように見えるが、実際には信号が反転したさらに９０°の位相遅れになるので、位相遅れ方向にφ２ ′＝２７０°の位相シフトが行われる。
【００６６】
したがって、２つの移相回路１０Ｃ、３０Ｃを縦続接続した場合には、図９（Ｃ）に示すように、上述したφ１ ＝９０°とφ２ ′＝２７０°が足し合わされて、全体として３６０°の位相シフトが行われる。
【００６７】
別の見方をすれば、同調増幅器１に入力される信号の中で２つの移相回路１０Ｃ、３０Ｃによる位相シフト量の合計が３６０°以外の周波数成分は閉ループを循環する際に減衰し、位相シフト量の合計が３６０°となる周波数成分のみが選択、出力されて所定の同調動作が行われる。
【００６８】
このように、上述した同調増幅器１によれば、入力抵抗７４の抵抗値を可変して帰還抵抗７０と入力抵抗７４の抵抗比ｎを変えても同調周波数および同調時の利得が一定であり、最大減衰量のみを変化させることができる。なお、入力抵抗７４を可変抵抗ではなく抵抗値が固定の抵抗とし、反対に帰還抵抗７０を可変抵抗によって構成し、この帰還抵抗７０の抵抗値を可変して上述した抵抗比ｎを変えるようにしてもよい。
【００６９】
また、後段の移相回路３０Ｃ内の可変抵抗３６の抵抗値を変えることにより、キャパシタ３４と可変抵抗３６からなるＣＲ回路の時定数Ｔ_２ を変化させることができるため、１／√（Ｔ_１ Ｔ_２ ）によって算出される同調周波数ωもある範囲で可変することができる。
【００７０】
また、最大減衰量は、帰還抵抗７０と入力抵抗７４の抵抗比ｎによって決定されるため、移相回路３０Ｃ内の可変抵抗３６の抵抗値を変えて同調周波数を変えた場合であっても、この最大減衰量に影響を与えることはなく、同調周波数や最大減衰量を互いに干渉しあうことなく調整することができる。
【００７１】
また、非反転回路５０の後段に分圧回路１６０を接続して、この分圧回路１６０による分圧出力を帰還信号として用いるとともに分圧前の信号を同調増幅器１の出力として取り出すことにより、同調動作と同時に信号の増幅を行うことができる。
【００７２】
また、上述した同調増幅器１は、トランジスタ、キャパシタおよび抵抗を組み合わせて構成しており、どの構成素子も半導体基板上に形成することができることから、同調周波数および最大減衰量を調整し得る同調増幅器１の全体を半導体基板上に形成して集積回路とすることも容易である。
【００７３】
なお、上述した同調増幅器１に含まれる非反転回路５０は、バイポーラトランジスタ５８を含んで構成したが、これをＦＥＴに置き換えて、２段のソース接地回路によって構成するようにしてもよい。この場合には、同調増幅器１に使用されるトランジスタの全てがＦＥＴで統一されるため、製造プロセスの簡略化が可能となる。
【００７４】
〔第２の実施形態〕
上述した第１の実施形態の同調増幅器１は、各移相回路１０Ｃ、３０ＣをＣＲ回路を含んで構成したが、ＣＲ回路を抵抗とインダクタからなるＬＲ回路に置き換えた移相回路を用いて同調増幅器を構成することもできる。
【００７５】
図１０は、本発明を適用した第２の実施形態の同調増幅器の構成を示す回路図である。同図に示す同調増幅器１Ａは、それぞれが入力される交流信号の位相を所定量シフトさせることにより所定の周波数において合計で３６０°の位相シフトを行う２つの移相回路１０Ｌ、３０Ｌと、移相回路３０Ｌの出力信号の位相を変えずに所定の増幅度で増幅して出力する非反転回路５０と、非反転回路５０の後段に設けられた抵抗１６２および１６４からなる分圧回路１６０と、帰還抵抗７０および入力抵抗７４のそれぞれを介することにより分圧回路１６０の分圧出力（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。同図に示す同調増幅器１Ａは、図１に示した同調増幅器１に対して前段の移相回路１０Ｃを移相回路１０Ｌに、後段の移相回路３０Ｃを移相回路３０Ｌにそれぞれ置き換えた構成を有している。
【００７６】
図１１は、図１０に示した前段の移相回路１０Ｌの構成を抜き出して示したものである。同図に示す移相回路１０Ｌは、図２に示した移相回路１０Ｃ内のキャパシタ１４と抵抗１６からなるＣＲ回路を、抵抗１６とインダクタ１７からなるＬＲ回路に置き換えた構成を有している。なお、抵抗１６とＦＥＴ１２のドレインとの間に挿入されたキャパシタ１９は直流電流阻止用であり、そのインピーダンスは動作周波数において極めて小さく設定され、すなわち大きな静電容量を有している。
【００７７】
図１２は、移相回路１０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【００７８】
抵抗１６の両端に現れる電圧ＶＲ３とインダクタ１７の両端に現れる電圧ＶＬ１とは互いに９０°位相がずれており、これらをベクトル的に合成したものがＦＥＴ１２のソース・ドレイン間の電圧２Ｅｉ に等しくなる。したがって、図１２に示すように、電圧Ｅｉ の２倍を斜辺とし、抵抗１６の両端電圧ＶＲ３とインダクタ１７の両端電圧ＶＬ１とが直交する２辺を構成する直角三角形を形成することになる。このため、入力信号の振幅が一定で周波数のみが変化した場合には、図１２に示す半円の円周に沿って抵抗１６の両端電圧ＶＲ３とインダクタ１７の両端電圧ＶＬ１とが変化する。
【００７９】
抵抗１６とインダクタ１７の接続点とグランドレベルとの電位差を出力電圧Ｅｏ として取り出すものとすると、この出力電圧Ｅｏ は、図１２に示した半円においてその中心点を始点とし、電圧ＶＲ３と電圧ＶＬ１とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ に等しくなる。しかも、入力信号の周波数が変化しても、このベクトルの終点は円周上を移動するだけであるため、周波数に応じて出力振幅が変化しない安定した出力を得ることができる。
【００８０】
また、図１２から明らかなように、電圧ＶＲ３と電圧ＶＬ１とは円周上で直角に交わるため、理論的にはＦＥＴ１２のゲートに印加される入力電圧と電圧ＶＲ３との位相差は、周波数ωが０から∞まで変化するに従って０°から９０°まで変化する。そして、移相回路１０Ｌ全体の位相シフト量φ３ はその２倍であり、周波数に応じて０°から１８０°まで変化する。
【００８１】
また、この位相シフト量φ３ は、抵抗１６とインダクタ１７により構成されるＬＲ回路の時定数をＴ_１ （抵抗１６の抵抗値をＲ、インダクタ１７のインダクタンスをＬとするとＴ_１ ＝Ｌ／Ｒ）とすると、上述した（６）式に示したφ１ と同じとなる。
【００８２】
同様に、図１３は、図１０に示した後段の移相回路３０Ｌの構成を抜き出して示したものである。同図に示す移相回路３０Ｌは、図４に示した移相回路３０Ｃ内の可変抵抗３６とキャパシタ３４からなるＣＲ回路を、インダクタ３７と可変抵抗３６からなるＬＲ回路に置き換えた構成を有している。なお、インダクタ３７とＦＥＴ３２のドレインとの間に挿入されたキャパシタ３９は直流電流阻止用であり、そのインピーダンスは動作周波数において極めて小さく設定され、すなわち大きな静電容量を有している。
【００８３】
図１４は、移相回路３０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【００８４】
インダクタ３７の両端に現れる電圧ＶＬ２と可変抵抗３６の両端に現れる電圧ＶＲ４とは互いに９０°位相がずれており、これらをベクトル的に合成したものがＦＥＴ３２のソース・ドレイン間の電圧２Ｅｉ に等しくなる。したがって、図１４に示すように、電圧Ｅｉ の２倍を斜辺とし、インダクタ３７の両端電圧ＶＬ２と可変抵抗３６の両端電圧ＶＲ４とが直交する２辺を構成する直角三角形を形成することになる。このため、入力信号の振幅が一定で周波数のみが変化した場合には、図１４に示す半円の円周に沿ってインダクタ３７の両端電圧ＶＬ２と可変抵抗３６の両端電圧ＶＲ４とが変化する。
【００８５】
インダクタ３７と可変抵抗３６の接続点とグランドレベルとの電位差を出力電圧Ｅｏ として取り出すものとすると、この出力電圧Ｅｏ は、図１４に示した半円においてその中心点を始点とし、電圧ＶＬ２と電圧ＶＲ４とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ に等しくなる。しかも、入力信号の周波数が変化しても、このベクトルの終点は円周上を移動するだけであるため、周波数に応じて出力振幅が変化しない安定した出力を得ることができる。
【００８６】
また、図１４から明らかなように、電圧ＶＬ２と電圧ＶＲ４とは円周上で直角に交わるため、理論的にはＦＥＴ３２のゲートに印加される入力電圧と電圧ＶＬ２との位相差は、周波数ωが０から∞まで変化するに従って９０°から０°まで変化する。そして、移相回路３０Ｌ全体の位相シフト量φ４ はその２倍であり、周波数に応じて１８０°から０°まで変化する。
【００８７】
また、この位相シフト量φ４ は、インダクタ３７と可変抵抗３６により構成されるＬＲ回路の時定数をＴ_２ （インダクタ３７のインダクタンスをＬ、可変抵抗３６の抵抗値をＲとするとＴ_２ ＝Ｌ／Ｒ）とすると、上述した（７）式に示したφ２ と同じとなる。
【００８８】
このように、図１０に示した同調増幅器１Ａに含まれる２つの移相回路１０Ｌ、３０Ｌのそれぞれは、時定数を用いて表すと図１に示した同調増幅器１に含まれる２つの移相回路１０Ｃ、３０Ｃと等価であり、同調増幅器１Ａは同調増幅器１と同様の同調動作および増幅動作が可能となる。
【００８９】
また、同調増幅器１Ａを構成する２つの移相回路１０Ｌ、３０Ｌのそれぞれは、各移相回路１０Ｌ、３０Ｌに含まれるＬＲ回路の時定数によって同調周波数が決まることになるが、各時定数Ｔは例えばＬ／Ｒであって、同調周波数ωは１／Ｔ＝Ｒ／Ｌに比例する。ここで、ＬＲ回路を構成するインダクタは、写真触刻法等により渦巻き形状の導体を半導体基板上に形成することにより実現できるが、このようにして形成したインダクタを用いることにより、同調増幅器の全体を半導体基板上に集積化することができる。
【００９０】
但し、この場合にはインダクタが有するインダクタンスが極めて小さくなるため、同調周波数が高くなる。別の見方をすれば、同調増幅器の同調周波数は例えば各移相回路１０Ｌ、３０Ｌ内のＬＲ回路の時定数の逆数Ｒ／Ｌに比例し、この中でインダクタンスＬは集積化等により小さくすることが容易であるため、上述した同調増幅器１Ａ全体をを集積化することにより同調周波数の高周波化が容易となる。
【００９１】
なお、図１０に示した同調増幅器１Ａは、図１に示した同調増幅器１に含まれる移相回路１０Ｃ、３０Ｃの両方を等価な移相回路１０Ｌ、３０Ｌに置き換えて構成したが、同調増幅器１に含まれる移相回路１０Ｃ、３０Ｃのいずれか一方のみを移相回路１０Ｌあるいは３０Ｌに置き換えて同調増幅器を構成してもよい。特に、このような同調増幅器全体を集積化した場合には、温度変化による同調周波数の変動を防止する、いわゆる温度補償が可能となる。すなわち、ＣＲ回路の時定数ＴはＣＲであり、ＬＲ回路の時定数ＴはＬ／Ｒであって、それぞれにおいて抵抗値Ｒが分子と分母に分かれるため、集積化によってＣＲ回路およびＬＲ回路を構成する抵抗を半導体材料によって形成するような場合には、これら各抵抗の温度変化に対する同調周波数の変動を抑制する効果がある。
【００９２】
〔第３の実施形態〕
上述した第１および第２の実施形態の同調増幅器１、１Ａは、互いに移相方向が異なる２つの移相回路を含んで構成したが、基本的に同じ構成を有する２つの移相回路を組み合わせて同調増幅器を構成することもできる。
【００９３】
図１５は、本発明の第３の実施形態の同調増幅器の構成を示す回路図である。同図に示す同調増幅器１Ｂは、それぞれが入力される交流信号の位相を所定量シフトさせることにより所定の周波数において合計で１８０°の位相シフトを行う２つの移相回路１０Ｃおよび１０Ｃ′と、後段の移相回路１０Ｃ′の出力信号の位相をさらに反転する位相反転回路８０と、位相反転回路８０の後段に設けられた抵抗１６２および１６４からなる分圧回路１６０と、帰還抵抗７０および入力抵抗７４（入力抵抗７４は帰還抵抗７０の抵抗値のｎ倍の抵抗値を有しているものとする）のそれぞれを介することにより分圧回路１６０の分圧出力（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。
【００９４】
前段の移相回路１０Ｃは、その詳細構成および入出力信号の位相関係は図２および図３を用いて説明した通りであり、例えばキャパシタ１４と抵抗１６からなるＣＲ回路の時定数をＴ_１ とすると、ω＝１／Ｔ_１ の周波数において位相シフト量φ１ が遅れ位相方向に９０°となる。
【００９５】
また、後段の移相回路１０Ｃ′は、上述した前段の移相回路１０Ｃと基本的な構成は同じであり、移相回路１０Ｃ内の抵抗１６を可変抵抗１５に置き換えた構成を有している。したがって、例えばキャパシタ１４と可変抵抗１５からなるＣＲ回路の時定数をＴ_３ とすると、ω＝１／Ｔ_３ の周波数において位相シフトφ１ ′が遅れ位相方向に９０°となる。
【００９６】
このように、２つの移相回路１０Ｃおよび１０Ｃ′の全体による遅れ位相方向の位相シフト量の合計が所定の周波数において、φ１ ＋φ１ ′＝９０°＋９０°＝１８０°となる。
【００９７】
また、位相反転回路８０は、ドレインと正電源との間に抵抗８４が、ソースとアースとの間に抵抗８６がそれぞれ接続されたＦＥＴ８２と、ＦＥＴ８２のゲートに所定のバイアス電圧を印加する抵抗８８とを含んで構成されている。ＦＥＴ８２のゲートに交流信号が入力されると、ＦＥＴ８２のドレインからは位相を反転した逆相の信号が出力される。また、この位相反転回路８０は、２つの抵抗８４、８６の抵抗比によって定まる所定の増幅度を有する。
【００９８】
このように、所定の周波数において、２つの移相回路１０Ｃおよび１０Ｃ′によって位相が１８０°シフトされ、さらに後段に接続された位相反転回路８０によって位相が反転され、これら３つの回路の全体による位相シフト量の合計が３６０°となる。
【００９９】
また、位相反転回路８０の出力は出力端子９２から同調増幅器１Ｂの出力として取り出されるとともに、位相反転回路８０の出力を分圧回路１６０を通した信号が帰還抵抗７０を介して前段の移相回路１０Ｃの入力側に帰還されている。そして、この帰還される信号と入力抵抗７４を介して入力される信号とが加算され、この加算された信号の電圧が前段の移相回路１０Ｃの入力端に印加されている。
【０１００】
このように、分圧回路１６０の出力を帰還抵抗７０を介して前段の移相回路１０Ｃの入力側に帰還させ、この帰還信号に入力抵抗７４を介して入力した信号を加算するとともに、位相反転回路８０の利得と分圧回路１６０の分圧比を調整して帰還ループのオープンループゲインを１以下に設定することにより、図１に示した同調増幅器１と同様の同調動作および増幅動作を行うことができる。
【０１０１】
図１６は、第３の実施形態の同調増幅器の他の構成を示す回路図である。同図に示す同調増幅器１Ｃは、それぞれが入力される交流信号の位相を所定量シフトさせることにより所定の周波数において合計で１８０°の位相シフトを行う２つの移相回路３０Ｃ′および３０Ｃと、後段の移相回路３０Ｃの出力信号の位相をさらに反転する位相反転回路８０と、位相反転回路８０の後段に設けられた抵抗１６２および１６４からなる分圧回路１６０と、帰還抵抗７０および入力抵抗７４のそれぞれを介することにより分圧回路１６０の分圧出力（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。
【０１０２】
前段の移相回路３０Ｃ′は、図４に構成を示した移相回路３０Ｃと基本的な構成は同じであり、移相回路３０Ｃ内の可変抵抗３６を抵抗値が固定の抵抗３５に置き換えた構成を有している。したがって、例えば、抵抗３５とキャパシタ３４からなるＣＲ回路の時定数をＴ_４ とし、ω＝１／Ｔ_４ の周波数における移相量φ２ ′を考えると、信号が反転してさらに位相遅れ方向に９０°となる。
【０１０３】
また、後段の移相回路３０Ｃは、その詳細構成および入出力信号の位相関係は図４および図５を用いて説明した通りであり、例えば可変抵抗３６とキャパシタ３４からなるＣＲ回路の時定数をＴ_２ とし、ω＝１／Ｔ_２ の周波数における移相量φ２ を考えると、信号が反転してさらに位相遅れ方向に９０°となる。
【０１０４】
このように、２つの移相回路３０Ｃ′および３０Ｃの全体による遅れ位相方向の位相シフト量の合計が所定の周波数において、φ２ ′＋φ２ ＝９０°＋９０°＝１８０°となる。
【０１０５】
このように、上述した２つの移相回路３０Ｃ′、３０Ｃを用いた場合であっても、所定の周波数において２つの移相回路３０Ｃ′および３０Ｃによって位相が１８０°シフトされ、さらに後段に接続された位相反転回路８０によって位相が反転され、これら３つの回路の全体による位相シフト量の合計が３６０°となる。
【０１０６】
したがって、上述した同調増幅器１Ｃは、分圧回路１６０の出力を帰還抵抗７０を介して前段の移相回路３０Ｃ′の入力側に帰還させ、この帰還信号に入力抵抗７４を介して入力した信号を加算するとともに、位相反転回路８０の利得と分圧回路１６０の分圧比を調整して帰還ループのオープンループゲインを１以下に設定することにより、図１５に示した同調増幅器１Ｂと同様の同調動作および増幅動作を行うことができる。
【０１０７】
なお、図１５、図１６に示した同調増幅器１Ｂ、１Ｃは、いずれも２つの移相回路をＣＲ回路を含んで構成したが、少なくとも一方をＬＲ回路を含んで構成するようにしてもよい。
【０１０８】
具体的には、図１５に示した同調増幅器１Ｂにおいて、前段の移相回路１０Ｃを図１１に示した移相回路１０Ｌに、あるいは後段の移相回路１０Ｃ′を図１１に示した移相回路１０Ｌの抵抗１６を可変抵抗１５に変更した移相回路１０Ｌ′に置き換える。または、２つの移相回路１０Ｃ、１０Ｃ′の両方を上述した移相回路１０Ｌ、１０Ｌ′に置き換える。
【０１０９】
また、図１６に示した同調増幅器１Ｃにおいて、前段の移相回路３０Ｃ′を図１３に示した移相回路３０Ｌの可変抵抗３６を抵抗値が固定の抵抗３５に変更した移相回路３０Ｌ′に、あるいは後段の移相回路３０Ｃを図１３に示した移相回路３０Ｌに置き換える。または、２つの移相回路３０Ｃ′、３０Ｃの両方を上述した移相回路３０Ｌ′、３０Ｌに置き換える。
【０１１０】
特に、両方の移相回路をＬＲ回路を有する移相回路に置き換えた場合には、同調増幅器全体を集積化することにより同調周波数の高周波化が容易となり、一方の移相回路をＬＲ回路を有する移相回路に置き換えた場合には、温度変化による同調周波数の変動を防止する、いわゆる温度補償が可能となる。
【０１１１】
〔その他の実施形態〕
ところで、上述した各種の同調増幅器１等は、位相シフトに着目すると２つの移相回路と非反転回路あるいは２つの移相回路と位相反転回路によって構成されており、接続された３つの回路の全体によって所定の周波数において合計の位相シフト量を３６０°にすることにより所定の同調動作を行うようになっている。したがって、位相シフト量だけに着目すると、２つの移相回路のどちらを前段に用いるか、あるいは３つの回路をどのような順番で接続するかはある程度の自由度があり、必要に応じて接続順番を決めることができる。
【０１１２】
図１７は、２つの移相回路と非反転回路５０を組み合わせて同調増幅器を構成した場合において、その接続状態を示す図である。なお、これらの図において、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａは、各同調増幅器の出力信号と入力信号とを所定の割合で加算するためのものであり、最も一般的には図１等に示すように、帰還側インピーダンス素子７０ａとして帰還抵抗７０を、入力側インピーダンス素子７４ａとして入力抵抗７４を使用する。
【０１１３】
但し、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａは、それぞれの素子に入力された信号の位相関係を変えることなく加算できればよいことから、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａをともにキャパシタにより形成したり、抵抗やキャパシタ等を組み合わせてインピーダンスの実数分と虚数分の比を同時に調整しうるようにしてもよい。
【０１１４】
また、図１７および後述する図１８に示した同調増幅器の構成には分圧回路１６０を除いた構成を示したが、実際には最終段の回路のさらに後段にこの分圧回路１６０を接続し、分圧後の信号を帰還信号として用いるとともに分圧前の信号を出力として取り出せばよい。
【０１１５】
図１７（Ａ）には２つの移相回路の後段に非反転回路５０を配置した構成が示されており、図１に示した同調増幅器１や図１０に示した同調増幅器１Ａに対応している。このように、後段に非反転回路５０を配置した場合には、この非反転回路５０に出力バッファの機能を持たせることにより、大きな出力電流を取り出すこともできる。
【０１１６】
図１７（Ｂ）には２つの移相回路の間に非反転回路５０を配置した構成が示されている。このように、中間に非反転回路５０を配置した場合には、前段の移相回路と後段の移相回路の相互干渉を完全に防止することができる。
【０１１７】
図１７（Ｃ）には２つの移相回路のさらに前段に非反転回路５０を配置した構成が示されている。このように、初段に非反転回路５０を配置した場合には、前段の移相回路に対する帰還側インピーダンス素子７０ａ等の影響を最小限に抑えることができる。
【０１１８】
同様に、図１８は、２つの移相回路と位相反転回路を組み合わせて同調増幅器を構成した場合において、その接続状態を示す図である。
【０１１９】
図１８（Ａ）には２つの移相回路の後段に位相反転回路８０を配置した構成が示されており、図１５に示した同調増幅器１Ｂあるいは図１６に示した同調増幅器１Ｃに対応している。このように、後段に位相反転回路８０を配置した場合には、この位相反転回路８０に出力バッファの機能を持たせることにより、大きな出力電流を取り出すこともできる。
【０１２０】
図１８（Ｂ）には２つの移相回路の間に位相反転回路８０を配置した構成が示されており、この場合には２つの移相回路間の相互干渉を完全に防止することができる。図１８（Ｃ）には２つの移相回路のさらに前段に位相反転回路８０を配置した構成が示されており、この場合には前段の移相回路に対する帰還側インピーダンス素子７０ａ等の影響を最小限に抑えることができる。
【０１２１】
本発明は上述した各種の実施形態に限定されるものではなく、この発明の要旨の範囲内で種々の変形実施が可能である。
【０１２２】
例えば、上述した各種の同調増幅器に含まれる可変抵抗３６等は、半導体基板上に集積化するには接合型あるいはＭＯＳ型のＦＥＴのチャネルを抵抗体として用いて実現することができる。このようにＦＥＴによって可変抵抗を形成した場合には、ゲート電圧を可変することによりソース・ドレイン間の抵抗を変化させることができる。
【０１２３】
また、上述した可変抵抗７４、３６等をｐチャネルのＦＥＴとｎチャネルのＦＥＴとを並列接続して構成してもよい。このように、２つのＦＥＴを組み合わせて可変抵抗を構成することにより、ＦＥＴの非線形領域の改善を行うことができるため、同調出力の歪みを少なくすることができる。
【０１２４】
また、上述した各種の同調増幅器においては、一方の移相回路に可変抵抗を含ませておいたが、２つの移相回路の両方に可変抵抗を含ませておいて（例えば図１に示した同調増幅器１において移相回路１０Ｃ内の抵抗１６を可変抵抗１５に置き換えて）、２つの移相回路の各位相シフト量を同時に変化させるようにしてもよい。この場合には、同調増幅器全体の同調周波数の変化量、すなわち同調周波数の可変範囲を大きく設定できる利点がある。
【０１２５】
また、上述した可変抵抗をＰＩＮダイオードによって構成し、このＰＩＮダイオードに流す電流値を変化させて、両端に現れる抵抗を変化させるようにしてもよい。
【０１２６】
また、ＣＲ回路を有する移相回路においては、各移相回路内のＣＲ回路を構成する抵抗の抵抗値を変化させるのではなく、キャパシタの静電容量を変えることによりＣＲ回路の時定数を変化させ、これにより移相回路の位相シフト量、すなわち同調増幅器の同調周波数を変化させるようにしてもよい。
【０１２７】
具体的には、ＣＲ回路を構成するキャパシタ（例えば図２に示したキャパシタ１４）を可変容量ダイオードと直流電流阻止用のキャパシタに置き換える。可変容量ダイオードは、印加する逆バイアス電圧を変えることによりアノード・カソード間の静電容量が変化するものである。このような可変容量ダイオードと抵抗とを直列接続してＣＲ回路を構成することにより、印加する逆バイアス電圧を変えてこのＣＲ回路の時定数を変えることができ、移相回路による位相シフト量を変化させることができる。
【０１２８】
また、この可変容量ダイオードの代わりに、ゲートに印加する制御電圧に応じてそのゲート容量がある範囲で変更可能なＦＥＴを可変容量素子として用いるようにしてもよい。
【０１２９】
また、上述したように可変抵抗や可変容量素子を用いる場合の他、素子定数が異なる複数の抵抗、キャパシタあるいはインダクタを用意しておいて、スイッチを切り換えることにより、これら複数の素子の中から１つあるいは複数を選ぶようにしてもよい。この場合にはスイッチ切り換えにより接続する素子の個数および接続方法（直列接続、並列接続あるいはこれらの組み合わせ）によって、素子定数を不連続に切り換えることができる。
【０１３０】
例えば、可変抵抗の代わりに抵抗値がＲ、２Ｒ、４Ｒ、…といった２のｎ乗の系列の複数の抵抗を用意しておいて、１つあるいは任意の複数を選択して直列接続することにより、等間隔の抵抗値の切り換えをより少ない素子で容易に実現することができる。同様に、キャパシタの代わりに静電容量がＣ、２Ｃ、４Ｃ、…といった２のｎ乗の系列の複数のキャパシタを用意しておいて、１つあるいは任意の複数を選択して並列接続することにより、等間隔の静電容量の切り換えをより少ない素子で容易に実現することができる。このため、同調周波数が複数ある回路、例えばＡＭラジオにこの実施形態の同調増幅器を適用して、複数の放送局から１局を選局して受信するような用途に適している。
【０１３１】
また、上述した各種の同調増幅器に含まれる２つの移相回路は、接合型のＦＥＴ１２あるいはＦＥＴ３２を用いて構成した場合を図示したが、ＭＯＳ型のＦＥＴにより、あるいはバイポーラトランジスタによって移相回路を構成するようにしてもよい。
【０１３２】
ＦＥＴをバイポーラトランジスタに置き換えた移相回路においては、入力信号がベースに入力されたときにベース・エミッタ間で電流が流れるため、エミッタに現れる電圧（交流電圧）とコレクタに現れる電圧（交流電圧）とは正確には同じにはならない。但し、電流増幅度が数十倍から百倍程度である場合には、その差は１％から数％であり、事実上無視することができる。あるいは、エミッタ抵抗よりコレクタ抵抗を若干大きく設定することにより、この差を補正するようにしてもよい。
【０１３３】
特に、バイポーラトランジスタを用いて移相回路を構成した場合には、動作周波数の上限を高くすることができ、また、ベース・エミッタ間の電位差がＦＥＴのゲート・ソース間の電位差よりも小さいため移相回路に入出力される信号振幅の減衰を少なくすることができる。したがって、少なくとも１段目の移相回路をバイポーラトランジスタを用いて構成することが好ましい。但し、２段目の移相回路は高入力インピーダンスにする必要があるため、ＦＥＴを用いて構成することが好ましい。
【０１３４】
【発明の効果】
以上の各実施形態に基づく説明から明らかなように、この発明の同調増幅器は、最大減衰量が入力側インピーダンス素子と帰還側インピーダンス素子の抵抗比ｎによって決まるとともに、同調周波数が各移相回路におけるＣＲ回路やＬＲ回路の時定数によって決まるため、最大減衰量や同調周波数および同調周波数における利得を互いに干渉しあうことなく設定することができる。
【０１３５】
また、同調増幅器内の２つの移相回路をＣＲ回路を含んで構成した場合には、同調増幅器全体を容易に集積化することができる。同様に、２つの移相回路をＬＲ回路を含んで構成した場合には、集積化によって小さなインダクタを形成することにより容易に同調周波数の高周波化が可能となる。一方の移相回路をＣＲ回路を含んで、他方の移相回路をＬＲ回路を含んで構成した場合には、温度等による特性の変動を防止して特性の安定化が可能となる。
【０１３６】
また、同調増幅器の出力として分圧回路を通す前の信号を取り出すことにより、同調増幅器に増幅作用を持たせることができる。
【図面の簡単な説明】
【図１】本発明を適用した第１の実施形態の同調増幅器の構成を示す回路図である。
【図２】図１に示した前段の移相回路の構成を抜き出して示した回路図である。
【図３】前段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図４】図１に示した後段の移相回路の構成を抜き出して示した回路図である。
【図５】後段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図６】２つの移相回路の全体を所定の伝達関数を有する回路に置き換えた回路図である。
【図７】図６に示す構成をミラーの定理によって変換した回路図である。
【図８】図１に示した同調増幅器の同調特性を示す図である。
【図９】同調増幅器に含まれる２つの移相回路に入出力される信号間の位相関係を示す図である。
【図１０】本発明を適用した第２の実施形態の同調増幅器の構成を示す回路図である。
【図１１】図１０に示した前段の移相回路の構成を抜き出して示した回路図である。
【図１２】前段の移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１３】図１０に示した後段の移相回路の構成を抜き出して示した回路図である。
【図１４】後段の移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１５】本発明を適用した第３の実施形態の同調増幅器の構成を示す回路図である。
【図１６】第３の実施形態の同調増幅器の他の構成を示す回路図である。
【図１７】移相回路と非反転回路の接続形態を示す図である。
【図１８】移相回路と位相反転回路の接続形態を示す図である。
【図１９】従来の同調増幅器における同調周波数、同調周波数における利得、最大減衰量の関係の一例を示す特性曲線図である。
【符号の説明】
１ 同調増幅器
１０Ｃ、３０Ｃ 移相回路
１２、３２、５２ ＦＥＴ
１４、３４ キャパシタ
１６、１８、２０、４０、３８ 抵抗
３６ 可変抵抗
５０ 非反転回路
７０ 帰還抵抗
７４ 入力抵抗
９０ 入力端子
９２ 出力端子
１６０ 分圧回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tuning amplifier that can be easily integrated, and more particularly to a tuning amplifier that can arbitrarily adjust a tuning frequency and a maximum attenuation amount without interfering with each other.
[0002]
[Background Art and Problems to be Solved by the Invention]
Conventionally, various amplifier circuits using active elements and reactance elements as tuning amplifiers have been proposed and put into practical use.
[0003]
For example, in a conventional tuning amplifier using LC resonance, the Q and gain depending on the LC circuit change when the tuning frequency is adjusted, and the tuning frequency changes when the maximum attenuation is adjusted. Alternatively, as shown in characteristic curves A and B in FIG. 19, when the maximum attenuation is adjusted, the gain at the tuning frequency changes.
[0004]
As described above, in the conventional tuning amplifier, it is extremely difficult to adjust the tuning frequency, the gain at the tuning frequency, and the maximum attenuation amounts C1 and C2 without interfering with each other. In addition, it has been difficult to form a tuning amplifier that can adjust the tuning frequency and the maximum attenuation amount by an integrated circuit.
[0005]
The present invention was created in view of the above points, and its purpose is suitable for integration, and it is possible to adjust the tuning frequency, the gain at the tuning frequency, and the maximum attenuation without interfering with each other. In particular, it is an object to provide a tuning amplifier that suppresses a change in output amplitude when the tuning frequency is varied.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problem, a tuning amplifier according to claim 1 includes two cascaded all-pass type phase shift circuits, a non-inverting circuit, and a voltage dividing circuit, and a final circuit of the plurality of cascaded circuits. An output circuit that feeds back the output of the stage to the input side of the first stage, adds the feedback signal and the input signal, and inputs them to the circuit of the first stage. Only a signal in the vicinity of a frequency of 360 ° is allowed to pass, and a signal before being input to the voltage dividing circuit is extracted as a tuning output. Here, the all-pass type means that the output signal has a constant amplitude regardless of the frequency of the input signal, and only the phase is shifted.
[0007]
The tuning amplifier according to claim 2 is the tuning amplifier according to claim 1, wherein each of the two phase shift circuits converts the input AC signal into an in-phase AC signal and an anti-phase AC signal, and outputs the converted AC signal. Synthesizing means for synthesizing one of the converted AC signals via a capacitor or inductor and the other AC signal via a resistor, and the amplitude is constant according to the frequency of the input AC signal and only the phase is included. Outputs a signal shifted by a predetermined amount, and the total phase shift amount is 360 ° at a certain frequency by the whole of the two phase shift circuits.
[0008]
A tuned amplifier according to claim 3 is characterized in that in claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
The method of connecting the capacitor and the resistor constituting the CR circuit is reversed in the two phase shift circuits.
[0009]
Here, each of the feedback-side impedance element and the input-side impedance element is most commonly a resistor. However, by combining elements such as a resistor and a capacitor, the ratios of the real component and the imaginary component of the impedance are the same. You may form so that it may become.
[0010]
A tuned amplifier according to claim 4 is characterized in that in claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base. An LR circuit composed of the inductor and the resistor constituting the synthesis means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
The connection method of the inductor and the resistor constituting the LR circuit is reversed in the two phase shift circuits.
[0011]
A tuned amplifier according to claim 5 is characterized in that in claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In one of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
In the other of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. An LR circuit comprising the inductor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
The reactance element formed of the capacitor or the inductor and the resistor are connected in the opposite manner in the two phase shift circuits.
[0012]
The tuned amplifier according to claim 6 includes two cascaded all-pass type phase shift circuits, phase inverting circuits, and voltage dividing circuits, and outputs of the final stages of the plurality of cascaded circuits on the input side of the first stage. An adder circuit that feeds back and adds the feedback signal and the input signal to the first stage circuit, and only the signals in the vicinity of the frequency at which the total phase shift amount is 180 ° by the whole of the two phase shift circuits. And a signal before being input to the voltage dividing circuit is taken out as a tuning output.
[0013]
A tuning amplifier according to a seventh aspect is the tuning amplifier according to the sixth aspect, wherein each of the two phase-shift circuits converts the input AC signal into an in-phase AC signal and an anti-phase AC signal and outputs the converted AC signal. Synthesizing means for synthesizing one of the converted AC signals via a capacitor or inductor and the other AC signal via a resistor, and the amplitude is constant according to the frequency of the input AC signal and only the phase is included. Outputs a signal shifted by a predetermined amount, and the total phase shift amount is 180 ° at a certain frequency by the whole of the two phase shift circuits.
[0014]
A tuned amplifier according to claim 8 is characterized in that in claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
The capacitor and the resistor constituting the CR circuit are connected in the same manner in the two phase shift circuits.
[0015]
A tuned amplifier according to claim 9 is characterized in that in claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base. An LR circuit composed of the inductor and the resistor constituting the synthesis means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
The inductors and the resistors constituting the LR circuit are connected in the same manner in the two phase shift circuits.
[0016]
A tuned amplifier according to claim 10 according to claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In one of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
In the other of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. An LR circuit comprising the inductor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
It is characterized in that the reactance element composed of the capacitor or the inductor and the resistor are connected in the same manner in the two phase shift circuits.
[0017]
A tuning amplifier according to an eleventh aspect is characterized in that in any one of the first to tenth aspects, a tuning frequency is varied by changing a phase shift amount of at least one of the two phase shift circuits.
[0018]
A tuning amplifier according to a twelfth aspect of the present invention is the tuning amplifier according to any one of the third to fifth and eighth to tenth aspects, wherein a tuning frequency is changed by changing a time constant of the CR circuit or the LR circuit included in at least one of the two phase shift circuits. Is variable.
[0019]
A tuned amplifier according to a thirteenth aspect is characterized in that, in the twelfth aspect, a resistor included in the CR circuit or the LR circuit is formed by a variable resistor, and a resistance value of the variable resistor is changed.
[0020]
The tuned amplifier of claim 14 is characterized in that, in claim 13, the variable resistor is formed of an FET, and the channel resistance between the source and the drain is changed by changing the gate voltage.
[0021]
The tuned amplifier according to claim 15 is the tuned amplifier according to claim 13, wherein the variable resistor is formed by connecting a p-channel FET and an n-channel FET in parallel, and each FET connected in parallel by changing a gate voltage is provided. The channel resistance is changed.
[0022]
According to a sixteenth aspect of the present invention, in the twelfth aspect, the capacitor included in the CR circuit is formed by a variable capacitance element, and the capacitance of the variable capacitance element is changed.
[0023]
A tuned amplifier according to claim 17 is the tuned amplifier according to any one of claims 3 to 5 and 8 to 10, wherein the feedback side impedance element and the input side impedance element are resistors, and at least one of the resistance values is varied to maximize attenuation. It is characterized by changing the amount.
[0024]
A tuned amplifier according to an eighteenth aspect is characterized in that in any one of the first to seventeenth aspects, the components are integrally formed on a semiconductor substrate.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a tuning amplifier according to an embodiment to which the present invention is applied will be described in detail with reference to the drawings.
[0026]
[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a tuning amplifier according to a first embodiment to which the present invention is applied. The tuning amplifier 1 shown in the figure includes two phase shift circuits 10C and 30C that perform a total phase shift of 360 ° at a predetermined frequency by shifting the phase of an AC signal to be input by a predetermined amount, and a phase shift A non-inverting circuit 50 that amplifies and outputs with a predetermined amplification without changing the phase of the output signal of the circuit 30C, a voltage dividing circuit 160 including resistors 162 and 164 provided at the subsequent stage of the non-inverting circuit 50, and feedback A voltage dividing output (feedback signal) of the voltage dividing circuit 160 and an input terminal through each of the resistor 70 and the input resistor 74 (the input resistor 74 has a resistance value n times that of the feedback resistor 70). And an addition circuit for adding a signal (input signal) inputted to 90 at a predetermined ratio.
[0027]
The capacitor 72 connected in series with the feedback resistor 70 and the capacitor 76 inserted between the input resistor 74 and the input terminal 90 are both for blocking DC current, and the impedance thereof is extremely small at the operating frequency. That is, it has a large capacitance.
[0028]
FIG. 2 shows an extracted configuration of the preceding phase shift circuit 10C shown in FIG. The phase-shift circuit 10C in the preceding stage shown in the figure includes an FET 12 whose gate is connected to the input terminal 22, a resistor 16 and a capacitor 14 connected in series between the source and drain of the FET 12, the drain of the FET 12, and a positive power source. And a resistor 18 connected between the source of the FET 12 and the ground.
[0029]
Here, the resistance values of the two resistors 20 and 18 connected to the source and drain of the FET 12 described above are set to be substantially equal, and the phase is matched when focusing on the AC component of the input voltage applied to the input terminal 22. The output signal is output from the source of the FET 12 and the signal whose phase is inverted (the phase is shifted by 180 °) is output from the drain of the FET 12.
[0030]
The resistor 26 in the phase shift circuit 10C shown in FIG. 1 is for applying an appropriate bias voltage to the FET 12.
[0031]
In the phase shift circuit 10C having such a configuration, when a predetermined AC signal is input to the input terminal 22, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 12, the source of the FET 12 is An AC voltage having the same phase as the input voltage appears, and on the other hand, an AC voltage having the same amplitude as that of the voltage appearing at the source and opposite in phase to the input voltage appears at the drain of the FET 12. The amplitude of the AC voltage appearing at the source and the drain is assumed to be Ei.
[0032]
A series circuit (CR circuit) composed of a resistor 16 and a capacitor 14 is connected between the source and drain of the FET 12. Therefore, a signal obtained by synthesizing each of the voltages appearing at the source and drain of the FET 12 via the resistor 16 or the capacitor 14 is output from the output terminal 24.
[0033]
FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit 10C and the voltage appearing in the capacitor or the like.
[0034]
Since an AC voltage having the same phase and opposite phase as the input voltage and having a voltage amplitude of Ei appears at the source and drain of the FET 12, the potential difference (AC component) between the source and drain becomes 2Ei. Further, the voltage VC1 appearing at both ends of the capacitor 14 and the voltage VR1 appearing at both ends of the resistor 16 are out of phase with each other by 90 °, and the vector combination of these voltages is the voltage 2Ei between the source and drain of the FET 12. Will be equal.
[0035]
Therefore, as shown in FIG. 3, a right triangle that forms two sides in which the voltage VC1 across the capacitor 14 and the voltage VR1 across the resistor 16 are orthogonal to each other is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VC1 of the capacitor 14 and the both-ends voltage VR1 of the resistor 16 change along the circumference of the semicircle shown in FIG.
[0036]
If the potential difference between the connection point of the capacitor 14 and the resistor 16 and the ground level is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be expressed by a vector whose end point is one point on the circumference where the voltage VR1 intersects, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0037]
Further, as apparent from FIG. 3, since the voltage VC1 and the voltage VR1 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 12 and the voltage VC1 is theoretically the frequency ω. As 0 changes from 0 to ∞, it changes from 0 ° to 90 °. The phase shift amount φ1 of the entire phase shift circuit 10C is twice that, and varies from 0 ° to 180 ° depending on the frequency.
[0038]
Similarly, FIG. 4 shows an extracted configuration of the subsequent phase shift circuit 30C shown in FIG. The latter-stage phase shift circuit 30C shown in the figure includes an FET 32 whose gate is connected to the input terminal 42, a capacitor 34 and a variable resistor 36 connected in series between the source and drain of the FET 32, and a drain and a positive electrode of the FET 32. The resistor 38 is connected between the power source and the resistor 40 is connected between the source of the FET 32 and the ground.
[0039]
Similar to the phase shift circuit 10C, the resistance values of the two resistors 40 and 38 connected to the source and drain of the FET 32 shown in FIG. 4 are set to be substantially equal, and the AC of the input voltage applied to the input terminal 42 is set. Focusing on the components, a signal having the same phase is output from the source of the FET 32, and a signal having an inverted phase is output from the drain of the FET 32.
[0040]
The resistor 46 in the phase shift circuit 30C shown in FIG. 1 is for applying an appropriate bias voltage to the FET 32, and the capacitor 48 provided between the phase shift circuits 30C and 10C This is for blocking direct current from the output of the circuit 10C, and only the alternating current component is input to the phase shift circuit 30C.
[0041]
In the phase shift circuit 30C having such a configuration, when a predetermined AC signal is input to the input terminal 42, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 32, the source of the FET 32 is An AC voltage having the same phase as the input voltage appears. On the other hand, an AC voltage having the same amplitude as that of the voltage appearing at the source and opposite in phase to the input voltage appears at the drain of the FET 32. The amplitude of the AC voltage appearing at the source and the drain is assumed to be Ei.
[0042]
A series circuit including a capacitor 34 and a variable resistor 36 is connected between the source and drain of the FET 32. Therefore, a signal obtained by synthesizing the voltages appearing at the source and drain of the FET 32 via the capacitor 34 or the variable resistor 36 is output from the output terminal 44.
[0043]
FIG. 5 is a vector diagram showing the relationship with the voltage appearing in the capacitor and the like of the subsequent phase shift circuit 30C.
[0044]
Since an AC voltage having the same phase and opposite phase as the input voltage and voltage amplitude Ei appears at the source and drain of the FET 32, the potential difference between the source and drain becomes 2Ei. Further, the voltage VR2 appearing at both ends of the variable resistor 36 and the voltage VC2 appearing at both ends of the capacitor 34 are out of phase with each other by 90 °, and the vector addition of these is the potential difference 2Ei between the source and drain of the FET 32. Is equal to
[0045]
Therefore, as shown in FIG. 5, a right-angled triangle that forms two sides where the voltage VR2 across the variable resistor 36 and the voltage VC2 across the capacitor 34 are orthogonal to each other is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR2 across the variable resistor 36 and the voltage VC2 across the capacitor 34 change along the circumference of the semicircle shown in FIG.
[0046]
If the potential difference between the connection point of the variable resistor 36 and the capacitor 34 and the ground level is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where VC2 intersects, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0047]
Further, as apparent from FIG. 5, since the voltage VR2 and the voltage VC2 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VR2 is theoretically the frequency ω. Changes from 90 ° to 0 ° as 0 changes from 0 to ∞. The phase shift amount φ2 of the entire phase shift circuit 30C is twice that and changes from 180 ° to 0 ° depending on the frequency.
[0048]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10C and 30C. Moreover, as shown in FIGS. 3 and 5, the relative phase relationship of the input / output voltages in each of the phase shift circuits 10C and 30C is in the opposite direction, and the two phase shift circuits 10C and 30C at a predetermined frequency. As a result, a signal having a total phase shift amount of 360 ° is output.
[0049]
Further, the non-inverting circuit 50 shown in FIG. 1 has an FET 52 in which a resistor 54 is connected between the drain and the positive power supply, a resistor 56 is connected between the source and the ground, and a base is connected to the drain of the FET 52. And a transistor 58 whose collector is connected to the source via a resistor 60, and a resistor 62 for applying an appropriate bias voltage to the FET 52. Note that the capacitor 64 provided in the front stage of the non-inverting circuit 50 shown in FIG. 1 is for DC current blocking that removes a DC component from the output of the subsequent phase shift circuit 30C, and only the AC component is supplied to the non-inverting circuit 50. Entered.
[0050]
When an AC signal is input to the gate of the FET 52, a reverse phase signal is output from the drain. In addition, when the signal of the opposite phase is input to the base, the transistor 58 outputs a signal of the same phase from the collector when the signal is further inverted, that is, based on the phase of the signal input to the gate of the FET 52. The in-phase signal is output from the non-inverting circuit 50.
[0051]
The output of the non-inverting circuit 50 is taken out from the output terminal 92 as the output of the tuning amplifier 1, and a signal obtained by passing the output of the non-inverting circuit 50 through the voltage dividing circuit 160 through the feedback resistor 70 is shifted to the previous phase. It is fed back to the input side of the circuit 10C. Then, the fed back signal and the signal input via the input resistor 74 are added, and the voltage of the added signal is input to the input terminal (the input terminal 22 shown in FIG. 2) of the preceding phase shift circuit 10C. Is applied.
[0052]
The amplification degree of the non-inverting circuit 50 described above is determined by the resistance values of the resistors 54, 56, and 60 described above, and the two phase shift circuits shown in FIG. 1 are adjusted by adjusting the resistance values of these resistors. The open loop gain of the feedback loop formed including 10C, 30C, the voltage dividing circuit 160, and the feedback resistor 70 is set to be 1 or less. That is, the signal amplitude is attenuated by passing through the two phase shift circuits 10C and 30C and the voltage dividing circuit 160. By compensating for this attenuation by amplification by the non-inverting circuit 50, the feedback loop of the entire tuning amplifier is opened. The loop gain is set to be 1 or less.
[0053]
Further, since the output signal of the non-inverting circuit 50 before being input to the voltage dividing circuit 160 is taken out from the output terminal 92 of the tuning amplifier 1, the gain of the tuning amplifier 1 itself can be given. The signal amplitude can be amplified simultaneously with the tuning operation.
[0054]
FIG. 6 is a system diagram in which the entire two phase shift circuits 10C, 30C, non-inverting circuit 50, and voltage dividing circuit 160 having the above-described configuration are replaced with a circuit having a transfer function K1, and a circuit having a transfer function K1. A feedback resistor 70 having a resistance R0 is connected in parallel with an input resistor 74 having a resistance value (nR0) n times that of the feedback resistor 70 in series. FIG. 7 is a system diagram in which the system shown in FIG. 6 is converted by Miller's theorem, and the transfer function A of the entire system after conversion is
A = Vo / Vi = K1 / {n (1-K1) +1} (1)
Can be expressed as
[0055]
By the way, the transfer function K2 of the preceding phase shift circuit 10C is the time constant of the CR circuit composed of the resistor 16 and the capacitor 14 as T₁(If the resistance value of the resistor 16 is R and the capacitance of the capacitor 14 is C, T₁= CR)
K2 = a₁(1-T₁s) / (1 + T₁s) (2)
It becomes. Where s = jω, a₁Is the gain of the phase shift circuit 10C and is a value less than one.
[0056]
Further, the transfer function K3 of the phase shift circuit 30C at the subsequent stage is obtained by setting the time constant of the CR circuit composed of the capacitor 34 and the variable resistor 36 to T₂(When the resistance value of the variable resistor 36 is R and the capacitance of the capacitor 34 is C, T₂= CR)
K3 = -a₂(1-T₂s) / (1 + T₂s) (3)
It becomes. Where a₂Is the gain of the phase shift circuit 30C and is a value less than one.
[0057]
Further, the gain of the voltage dividing circuit 160 is set to a₃(≦ 1), and in order to compensate for the attenuation of the signal amplitude by the phase shift circuits 10C and 30C and the voltage dividing circuit 160, the gain of the non-inverting circuit 50 is set to 1 / a₁a₂a₃Then, the overall transfer function K1 when the phase shift circuits 10C and 30C, the non-inverting circuit 50, and the voltage dividing circuit 160 are connected in cascade is
K1 =-{1+ (Ts)²-2Ts} / {1+ (Ts)²+ 2Ts} (4)
It becomes. In order to simplify the calculation, the time constant T of each phase shift circuit₁, T₂  Both are T. Substituting this equation (4) into the above equation (1),

It becomes.
[0058]
According to the equation (5), it can be seen that when ω = 0 (DC region), A = −1 / (2n + 1), and the maximum attenuation is given. Further, it can be seen that even when ω = ∞, A = −1 / (2n + 1), which gives the maximum attenuation. Further, the tuning point of ω = 1 / T (when the time constants of the phase shift circuits are different, ω = 1 / √ (T₁・ T₂  It can be seen that A = 1 at the tuning point)) and is independent of the resistance ratio n of the feedback resistor 70 and the input resistor 74. In other words, as shown in FIG. 8, even if the value of n is changed, the tuning point is not shifted and the attenuation at the tuning point is not changed.
[0059]
In addition, by changing the resistance value of the variable resistor 36 in the subsequent phase shift circuit 30C, the time constant T of the CR circuit composed of the variable resistor 36 and the capacitor 34 is obtained.₂The tuning frequency ω can be arbitrarily changed within a certain range.
[0060]
When φ1 and φ2 shown in FIGS. 3 and 5 are obtained from the equation (2) or (3),
φ1 = tan {2ωT₁/ (1-ω²T₁ ²)} (6)
φ2 = -tan {2ωT₂/ (1-ω²T₂ ²)} (7)
It becomes. Here, with reference to φ1 shown in FIG. 3, the symbol of φ2 shown in FIG. 5 is represented as “−”.
[0061]
For example, T₁= T₂In the case of (= T), when ω = 1 / T, the total phase shift amount by the two phase shift circuits 10C and 30C is 360 °, and the above-described tuning operation is performed. At this time, φ1 = 90 °, φ2 = -90 °.
[0062]
Incidentally, in FIG. 5, the output voltage Eo is shown as being advanced in phase than the voltage Ei having the same phase as the input voltage of the preceding phase shift circuit 30C. Is always in a delayed phase.
[0063]
FIG. 9 is a diagram illustrating a phase relationship between signals input to and output from the two phase shift circuits 10C and 30C, in which a signal having a frequency equal to the tuning frequency is input to the previous phase shift circuit 10C. As an example, the time constant T of each phase shift circuit 10C, 30C₁, T₂The case where is equal is shown.
[0064]
As shown in FIG. 9A, the preceding phase shift circuit 10C performs a phase shift of φ1 (= 90 °) on the input signal S1 and outputs an output signal S2.
[0065]
Further, as shown in FIG. 9B, the rear-stage phase shift circuit 30C shifts the phase of φ2 with respect to the input signal S2 (common with the output signal of the previous-stage phase shift circuit 10C), and outputs the output signal S3. Is output. Here, the output signal S3 seems to be 90 ° out of phase with respect to the input signal S2, but in reality, the output signal S3 is further 90 ° out of phase with the inverted signal. = 270 ° phase shift is performed.
[0066]
Therefore, when the two phase shift circuits 10C and 30C are connected in cascade, as shown in FIG. 9C, the above-described φ1 = 90 ° and φ2 ′ = 270 ° are added, and 360 ° as a whole. A phase shift is performed.
[0067]
From another viewpoint, in the signal input to the tuning amplifier 1, frequency components whose total phase shift amount by the two phase shift circuits 10C and 30C is other than 360 ° are attenuated when circulating through the closed loop, Only frequency components with a total shift amount of 360 ° are selected and output, and a predetermined tuning operation is performed.
[0068]
Thus, according to the tuning amplifier 1 described above, even if the resistance value of the input resistor 74 is varied to change the resistance ratio n between the feedback resistor 70 and the input resistor 74, the tuning frequency and the gain during tuning are constant. Only the maximum attenuation can be changed. The input resistor 74 is not a variable resistor but a resistor having a fixed resistance value. Conversely, the feedback resistor 70 is formed of a variable resistor, and the resistance ratio n is changed by changing the resistance value of the feedback resistor 70. May be.
[0069]
Further, by changing the resistance value of the variable resistor 36 in the subsequent phase shift circuit 30C, the time constant T of the CR circuit including the capacitor 34 and the variable resistor 36 is obtained.₂1 / √ (T₁T₂) Can also be varied within a certain range.
[0070]
Further, since the maximum attenuation is determined by the resistance ratio n of the feedback resistor 70 and the input resistor 74, even if the tuning frequency is changed by changing the resistance value of the variable resistor 36 in the phase shift circuit 30C, The maximum attenuation is not affected, and the tuning frequency and the maximum attenuation can be adjusted without interfering with each other.
[0071]
Further, the voltage dividing circuit 160 is connected to the subsequent stage of the non-inverting circuit 50, and the divided output from the voltage dividing circuit 160 is used as a feedback signal, and the signal before voltage division is taken out as the output of the tuning amplifier 1, thereby tuning. Signal amplification can be performed simultaneously with operation.
[0072]
The above-described tuning amplifier 1 is configured by combining a transistor, a capacitor, and a resistor, and any component can be formed on a semiconductor substrate. Therefore, the tuning amplifier 1 can adjust the tuning frequency and the maximum attenuation. It is easy to form an integrated circuit on the semiconductor substrate to form an integrated circuit.
[0073]
Although the non-inverting circuit 50 included in the tuning amplifier 1 described above includes the bipolar transistor 58, it may be configured by a two-stage source grounded circuit instead of the FET. In this case, since all the transistors used in the tuning amplifier 1 are unified by the FET, the manufacturing process can be simplified.
[0074]
[Second Embodiment]
In the tuning amplifier 1 of the first embodiment described above, each of the phase shift circuits 10C and 30C includes a CR circuit, but is tuned by using a phase shift circuit in which the CR circuit is replaced with an LR circuit composed of a resistor and an inductor. An amplifier can also be constructed.
[0075]
FIG. 10 is a circuit diagram showing a configuration of a tuning amplifier according to the second embodiment to which the present invention is applied. The tuning amplifier 1A shown in the figure includes two phase shift circuits 10L and 30L that perform a total phase shift of 360 ° at a predetermined frequency by shifting the phase of the AC signal to be input by a predetermined amount, and a phase shift A non-inverting circuit 50 that amplifies and outputs with a predetermined amplification without changing the phase of the output signal of the circuit 30L, a voltage dividing circuit 160 including resistors 162 and 164 provided at the subsequent stage of the non-inverting circuit 50, and feedback And an adder circuit that adds the divided output (feedback signal) of the voltage dividing circuit 160 and the signal (input signal) input to the input terminal 90 at a predetermined ratio through each of the resistor 70 and the input resistor 74. It consists of The tuning amplifier 1A shown in the figure has a configuration in which the preceding phase shift circuit 10C is replaced with a phase shift circuit 10L and the subsequent phase shift circuit 30C is replaced with a phase shift circuit 30L with respect to the tuning amplifier 1 shown in FIG. Have.
[0076]
FIG. 11 shows an extracted configuration of the previous phase shift circuit 10L shown in FIG. The phase shift circuit 10L shown in the figure has a configuration in which the CR circuit composed of the capacitor 14 and the resistor 16 in the phase shift circuit 10C shown in FIG. 2 is replaced with an LR circuit composed of the resistor 16 and the inductor 17. . The capacitor 19 inserted between the resistor 16 and the drain of the FET 12 is for DC current blocking, and its impedance is set to be extremely small at the operating frequency, that is, has a large capacitance.
[0077]
FIG. 12 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10L and the voltage appearing in the inductor or the like.
[0078]
The voltage VR3 appearing at both ends of the resistor 16 and the voltage VL1 appearing at both ends of the inductor 17 are out of phase with each other by 90 °, and the vector combination of these is equal to the voltage 2Ei between the source and drain of the FET 12. Accordingly, as shown in FIG. 12, a right triangle that forms two sides where the voltage VR3 of the resistor 16 and the voltage VL1 of the inductor 17 are orthogonal to each other is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VR3 of the resistor 16 and the both-ends voltage VL1 of the inductor 17 change along the circumference of the semicircle shown in FIG.
[0079]
If the potential difference between the connection point of the resistor 16 and the inductor 17 and the ground level is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. 12, and the voltage VR3 and the voltage VL1. Can be represented by a vector whose end point is a point on the circumference where and intersects with the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0080]
As apparent from FIG. 12, since the voltage VR3 and the voltage VL1 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 12 and the voltage VR3 is theoretically the frequency ω. As 0 changes from 0 to ∞, it changes from 0 ° to 90 °. The phase shift amount φ3 of the entire phase shift circuit 10L is twice that, and changes from 0 ° to 180 ° depending on the frequency.
[0081]
Further, this phase shift amount φ3 is obtained by setting the time constant of the LR circuit constituted by the resistor 16 and the inductor 17 to T₁(If the resistance value of the resistor 16 is R and the inductance of the inductor 17 is L, T₁= L / R), it is the same as φ1 shown in the above-described equation (6).
[0082]
Similarly, FIG. 13 shows an extracted configuration of the latter-stage phase shift circuit 30L shown in FIG. The phase shift circuit 30L shown in the figure has a configuration in which the CR circuit composed of the variable resistor 36 and the capacitor 34 in the phase shift circuit 30C shown in FIG. 4 is replaced with an LR circuit composed of the inductor 37 and the variable resistor 36. ing. The capacitor 39 inserted between the inductor 37 and the drain of the FET 32 is for DC current blocking, and its impedance is set to be extremely small at the operating frequency, that is, has a large capacitance.
[0083]
FIG. 14 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30L and the voltage appearing in the inductor or the like.
[0084]
The voltage VL2 appearing at both ends of the inductor 37 and the voltage VR4 appearing at both ends of the variable resistor 36 are out of phase with each other by 90 °. . Accordingly, as shown in FIG. 14, a right triangle that forms two sides where the voltage VL2 across the inductor 37 and the voltage VR4 across the variable resistor 36 are orthogonal is formed with twice the voltage Ei as the hypotenuse. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VL2 of the inductor 37 and the both-ends voltage VR4 of the variable resistor 36 change along the circumference of the semicircle shown in FIG.
[0085]
Assuming that the potential difference between the connection point of the inductor 37 and the variable resistor 36 and the ground level is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where VR4 intersects, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0086]
Further, as apparent from FIG. 14, since the voltage VL2 and the voltage VR4 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VL2 is theoretically the frequency ω. Changes from 90 ° to 0 ° as 0 changes from 0 to ∞. The phase shift amount φ4 of the entire phase shift circuit 30L is twice that and changes from 180 ° to 0 ° depending on the frequency.
[0087]
Further, the phase shift amount φ4 is obtained by setting the time constant of the LR circuit constituted by the inductor 37 and the variable resistor 36 to T₂(If the inductance of the inductor 37 is L and the resistance value of the variable resistor 36 is R, T₂= L / R), it is the same as φ2 shown in the above equation (7).
[0088]
As described above, each of the two phase shift circuits 10L and 30L included in the tuning amplifier 1A illustrated in FIG. 10 has two phase shift circuits included in the tuning amplifier 1 illustrated in FIG. It is equivalent to 10C and 30C, and the tuning amplifier 1A can perform a tuning operation and an amplification operation similar to those of the tuning amplifier 1.
[0089]
The tuning frequency of each of the two phase shift circuits 10L and 30L constituting the tuning amplifier 1A is determined by the time constant of the LR circuit included in each of the phase shift circuits 10L and 30L. For example, L / R, and the tuning frequency ω is proportional to 1 / T = R / L. Here, the inductor constituting the LR circuit can be realized by forming a spiral conductor on a semiconductor substrate by a photolithography method or the like, but by using the inductor thus formed, the entire tuning amplifier can be realized. Can be integrated on a semiconductor substrate.
[0090]
However, in this case, since the inductance of the inductor becomes extremely small, the tuning frequency becomes high. From another viewpoint, the tuning frequency of the tuning amplifier is proportional to, for example, the reciprocal R / L of the time constant of the LR circuit in each of the phase shift circuits 10L and 30L, in which the inductance L is reduced by integration or the like. Therefore, it is easy to increase the tuning frequency by integrating the entire tuning amplifier 1A.
[0091]
The tuning amplifier 1A shown in FIG. 10 is configured by replacing both of the phase shift circuits 10C and 30C included in the tuning amplifier 1 shown in FIG. 1 with equivalent phase shift circuits 10L and 30L. The tuning amplifier may be configured by replacing only one of the phase shift circuits 10C and 30C included in the phase shift circuit 10L or 30L. In particular, when such a tuning amplifier as a whole is integrated, so-called temperature compensation that prevents fluctuations in the tuning frequency due to temperature changes becomes possible. In other words, the time constant T of the CR circuit is CR, and the time constant T of the LR circuit is L / R, and the resistance value R is divided into a numerator and a denominator in each, so that the CR circuit and the LR circuit are configured by integration. In the case where the resistor to be formed is formed of a semiconductor material, there is an effect of suppressing the fluctuation of the tuning frequency with respect to the temperature change of each of these resistors.
[0092]
[Third Embodiment]
The tuned amplifiers 1 and 1A of the first and second embodiments described above are configured to include two phase shift circuits having different phase shift directions, but two phase shift circuits having basically the same configuration are combined. Thus, a tuned amplifier can be configured.
[0093]
FIG. 15 is a circuit diagram showing a configuration of a tuning amplifier according to the third embodiment of the present invention. The tuning amplifier 1B shown in FIG. 1 includes two phase shift circuits 10C and 10C ′ that perform a total phase shift of 180 ° at a predetermined frequency by shifting the phase of an AC signal to be input by a predetermined amount, and a subsequent stage. A phase inverting circuit 80 for further inverting the phase of the output signal of the phase shifting circuit 10C ′, a voltage dividing circuit 160 comprising resistors 162 and 164 provided at the subsequent stage of the phase inverting circuit 80, a feedback resistor 70 and an input resistor 74 (The input resistor 74 is assumed to have a resistance value that is n times the resistance value of the feedback resistor 70), and is input to the divided output (feedback signal) of the voltage dividing circuit 160 and the input terminal 90. And an adding circuit for adding the signal (input signal) to be added at a predetermined ratio.
[0094]
The phase shift circuit 10C in the previous stage has the detailed configuration and the phase relationship of the input / output signals as described with reference to FIGS. 2 and 3. For example, the time constant of the CR circuit including the capacitor 14 and the resistor 16 is set to₁Then, ω = 1 / T₁At this frequency, the phase shift amount φ1 becomes 90 ° in the delayed phase direction.
[0095]
The subsequent phase shift circuit 10C ′ has the same basic configuration as the above-described previous phase shift circuit 10C, and has a configuration in which the resistor 16 in the phase shift circuit 10C is replaced with a variable resistor 15. . Therefore, for example, the time constant of the CR circuit composed of the capacitor 14 and the variable resistor 15 is represented by T₃Then, ω = 1 / T₃The phase shift φ1 'becomes 90 ° in the delayed phase direction at the frequency of.
[0096]
In this way, the sum of the phase shift amounts in the delayed phase direction by the entire two phase shift circuits 10C and 10C ′ is φ1 + φ1 ′ = 90 ° + 90 ° = 180 ° at a predetermined frequency.
[0097]
Further, the phase inversion circuit 80 includes an FET 82 in which a resistor 84 is connected between the drain and the positive power source, and a resistor 86 is connected between the source and the ground, and a resistor 88 that applies a predetermined bias voltage to the gate of the FET 82. It is comprised including. When an AC signal is input to the gate of the FET 82, a reverse phase signal having an inverted phase is output from the drain of the FET 82. The phase inversion circuit 80 has a predetermined amplification degree determined by the resistance ratio of the two resistors 84 and 86.
[0098]
Thus, at a predetermined frequency, the phase is shifted by 180 ° by the two phase shift circuits 10C and 10C ′, and the phase is inverted by the phase inverting circuit 80 connected to the subsequent stage. The total shift amount is 360 °.
[0099]
Further, the output of the phase inverting circuit 80 is taken out from the output terminal 92 as the output of the tuning amplifier 1B, and the signal obtained by passing the output of the phase inverting circuit 80 through the voltage dividing circuit 160 is passed through the feedback resistor 70 to the preceding phase shift circuit. Returned to the input side of 10C. Then, the signal fed back and the signal inputted via the input resistor 74 are added, and the voltage of the added signal is applied to the input terminal of the preceding phase shift circuit 10C.
[0100]
In this way, the output of the voltage dividing circuit 160 is fed back to the input side of the preceding phase shift circuit 10C through the feedback resistor 70, and the signal input through the input resistor 74 is added to this feedback signal, and the phase is inverted. A tuning operation and an amplification operation similar to those of the tuning amplifier 1 shown in FIG. 1 are performed by adjusting the gain of the circuit 80 and the voltage dividing ratio of the voltage dividing circuit 160 to set the open loop gain of the feedback loop to 1 or less. Can do.
[0101]
FIG. 16 is a circuit diagram illustrating another configuration of the tuning amplifier according to the third embodiment. The tuning amplifier 1C shown in the figure includes two phase shift circuits 30C ′ and 30C that perform a total phase shift of 180 ° at a predetermined frequency by shifting the phase of the AC signal to be input by a predetermined amount, and a subsequent stage. A phase inverting circuit 80 for further inverting the phase of the output signal of the phase shifting circuit 30C, a voltage dividing circuit 160 comprising resistors 162 and 164 provided at the subsequent stage of the phase inverting circuit 80, a feedback resistor 70 and an input resistor 74 Each of them is configured to include a voltage dividing output (feedback signal) of the voltage dividing circuit 160 and an adding circuit that adds a signal (input signal) input to the input terminal 90 at a predetermined ratio.
[0102]
The phase shift circuit 30C ′ in the previous stage has the same basic configuration as the phase shift circuit 30C shown in FIG. 4, and the variable resistor 36 in the phase shift circuit 30C is replaced with a resistor 35 having a fixed resistance value. It has a configuration. Therefore, for example, the time constant of the CR circuit composed of the resistor 35 and the capacitor 34 is expressed as T₄Ω = 1 / T₄When the phase shift amount φ2 ′ at the frequency of is considered, the signal is inverted to 90 ° further in the phase delay direction.
[0103]
Further, the latter-stage phase shift circuit 30C has the detailed configuration and the phase relationship of the input / output signals as described with reference to FIGS. 4 and 5. For example, the time constant of the CR circuit including the variable resistor 36 and the capacitor 34 T₂Ω = 1 / T₂When the phase shift amount φ2 at the frequency of is considered, the signal is inverted to 90 ° further in the phase delay direction.
[0104]
In this way, the sum of the phase shift amounts in the delayed phase direction by the entire two phase shift circuits 30C ′ and 30C is φ2 ′ + φ2 = 90 ° + 90 ° = 180 ° at a predetermined frequency.
[0105]
As described above, even when the above-described two phase shift circuits 30C ′ and 30C are used, the phase is shifted by 180 ° by the two phase shift circuits 30C ′ and 30C at a predetermined frequency and further connected to the subsequent stage. The phase is inverted by the phase inverting circuit 80, and the total amount of phase shift by these three circuits is 360 °.
[0106]
Therefore, the above-described tuning amplifier 1C feeds back the output of the voltage dividing circuit 160 to the input side of the preceding phase shift circuit 30C ′ via the feedback resistor 70, and the signal input via the input resistor 74 to this feedback signal. In addition to adjusting the gain of the phase inverting circuit 80 and the voltage dividing ratio of the voltage dividing circuit 160 and setting the open loop gain of the feedback loop to 1 or less, the tuning operation similar to that of the tuning amplifier 1B shown in FIG. And an amplification operation can be performed.
[0107]
15 and 16 each include two phase shift circuits including a CR circuit, but at least one of them may include an LR circuit.
[0108]
Specifically, in the tuning amplifier 1B shown in FIG. 15, the preceding phase shift circuit 10C is changed to the phase shift circuit 10L shown in FIG. 11, or the subsequent phase shift circuit 10C ′ is changed to the phase shift circuit shown in FIG. The 10L resistor 16 is replaced with a phase shift circuit 10L ′ in which the variable resistor 15 is changed. Alternatively, both of the two phase shift circuits 10C and 10C ′ are replaced with the above-described phase shift circuits 10L and 10L ′.
[0109]
Further, in the tuning amplifier 1C shown in FIG. 16, the phase shift circuit 30C ′ in the previous stage is changed to the phase shift circuit 30L ′ in which the variable resistor 36 of the phase shift circuit 30L shown in FIG. Alternatively, the subsequent phase shift circuit 30C is replaced with the phase shift circuit 30L shown in FIG. Alternatively, both of the two phase shift circuits 30C ′ and 30C are replaced with the above-described phase shift circuits 30L ′ and 30L.
[0110]
In particular, when both of the phase shift circuits are replaced with phase shift circuits having LR circuits, it is easy to increase the tuning frequency by integrating the entire tuning amplifier, and one of the phase shift circuits has an LR circuit. When the phase shift circuit is used, so-called temperature compensation that prevents fluctuations in the tuning frequency due to temperature changes is possible.
[0111]
[Other Embodiments]
By the way, the above-described various tuning amplifiers 1 and the like are composed of two phase shift circuits and a non-inversion circuit or two phase shift circuits and a phase inversion circuit when focusing on the phase shift, and the whole of the three connected circuits. Thus, a predetermined tuning operation is performed by setting the total phase shift amount to 360 ° at a predetermined frequency. Therefore, when focusing only on the phase shift amount, there is a certain degree of freedom in which of the two phase shift circuits is used in the preceding stage, or in what order the three circuits are connected, and the connection order as necessary. Can be decided.
[0112]
FIG. 17 is a diagram illustrating a connection state in the case where a tuning amplifier is configured by combining two phase shift circuits and the non-inverting circuit 50. In these figures, the feedback-side impedance element 70a and the input-side impedance element 74a are for adding the output signals and input signals of the respective tuning amplifiers at a predetermined ratio, and are most commonly shown in FIG. As shown, the feedback resistor 70 is used as the feedback impedance element 70a, and the input resistor 74 is used as the input impedance element 74a.
[0113]
However, since the feedback side impedance element 70a and the input side impedance element 74a need only be added without changing the phase relationship of the signals input to the respective elements, both the feedback side impedance element 70a and the input side impedance element 74a are capacitors. Or the ratio of the real number and the imaginary number of the impedance may be adjusted simultaneously by combining resistors, capacitors, and the like.
[0114]
Further, the configuration of the tuning amplifier shown in FIG. 17 and FIG. 18 to be described later shows a configuration in which the voltage dividing circuit 160 is omitted, but actually, the voltage dividing circuit 160 is connected to the subsequent stage of the final stage circuit. The signal after the voltage division may be used as a feedback signal and the signal before the voltage division may be taken out as an output.
[0115]
FIG. 17A shows a configuration in which a non-inverting circuit 50 is arranged after the two phase shift circuits, and corresponds to the tuning amplifier 1 shown in FIG. 1 and the tuning amplifier 1A shown in FIG. Yes. As described above, when the non-inverting circuit 50 is disposed in the subsequent stage, a large output current can be taken out by providing the non-inverting circuit 50 with the function of an output buffer.
[0116]
FIG. 17B shows a configuration in which a non-inverting circuit 50 is disposed between two phase shift circuits. In this way, when the non-inverting circuit 50 is arranged in the middle, mutual interference between the front-stage phase shift circuit and the rear-stage phase shift circuit can be completely prevented.
[0117]
FIG. 17C shows a configuration in which the non-inverting circuit 50 is arranged further upstream of the two phase shift circuits. As described above, when the non-inverting circuit 50 is arranged in the first stage, the influence of the feedback side impedance element 70a and the like on the preceding phase shift circuit can be minimized.
[0118]
Similarly, FIG. 18 is a diagram illustrating a connection state when a tuning amplifier is configured by combining two phase shift circuits and a phase inversion circuit.
[0119]
FIG. 18A shows a configuration in which a phase inverting circuit 80 is disposed after the two phase shift circuits, corresponding to the tuning amplifier 1B shown in FIG. 15 or the tuning amplifier 1C shown in FIG. Yes. As described above, when the phase inverting circuit 80 is disposed in the subsequent stage, a large output current can be extracted by providing the phase inverting circuit 80 with the function of an output buffer.
[0120]
FIG. 18B shows a configuration in which a phase inversion circuit 80 is disposed between two phase shift circuits. In this case, mutual interference between the two phase shift circuits can be completely prevented. . FIG. 18C shows a configuration in which a phase inverting circuit 80 is arranged further upstream of the two phase shift circuits. In this case, the influence of the feedback side impedance element 70a etc. on the previous phase shift circuit is minimized. To the limit.
[0121]
The present invention is not limited to the various embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
[0122]
For example, the variable resistor 36 and the like included in the various tuning amplifiers described above can be realized by using a junction-type or MOS-type FET channel as a resistor for integration on a semiconductor substrate. When the variable resistance is formed by the FET as described above, the resistance between the source and the drain can be changed by changing the gate voltage.
[0123]
The variable resistors 74 and 36 described above may be configured by connecting a p-channel FET and an n-channel FET in parallel. In this way, by configuring the variable resistor by combining two FETs, it is possible to improve the nonlinear region of the FETs, so that the distortion of the tuning output can be reduced.
[0124]
In the above-described various tuned amplifiers, one phase shift circuit includes a variable resistor. However, both of the two phase shift circuits include a variable resistor (for example, as shown in FIG. 1). In the tuning amplifier 1, the phase shift amount of the two phase shift circuits may be changed simultaneously by replacing the resistor 16 in the phase shift circuit 10C with the variable resistor 15. In this case, there is an advantage that the variation amount of the tuning frequency of the entire tuning amplifier, that is, the variable range of the tuning frequency can be set large.
[0125]
Further, the above-described variable resistor may be constituted by a PIN diode, and the value of current flowing through the PIN diode may be changed to change the resistance appearing at both ends.
[0126]
In a phase shift circuit having a CR circuit, the time constant of the CR circuit is changed by changing the capacitance of the capacitor instead of changing the resistance value of the resistor constituting the CR circuit in each phase shift circuit. Thus, the phase shift amount of the phase shift circuit, that is, the tuning frequency of the tuning amplifier may be changed.
[0127]
Specifically, the capacitor constituting the CR circuit (for example, the capacitor 14 shown in FIG. 2) is replaced with a variable capacitance diode and a direct current blocking capacitor. In the variable capacitance diode, the capacitance between the anode and the cathode is changed by changing the applied reverse bias voltage. By constructing a CR circuit by connecting such variable capacitance diodes and resistors in series, the reverse bias voltage to be applied can be changed to change the time constant of the CR circuit, and the amount of phase shift by the phase shift circuit can be reduced. Can be changed.
[0128]
Further, instead of the variable capacitance diode, an FET that can be changed within a certain range according to the control voltage applied to the gate may be used as the variable capacitance element.
[0129]
In addition to the case of using a variable resistor or variable capacitance element as described above, a plurality of resistors, capacitors, or inductors having different element constants are prepared, and one of the plurality of elements is switched by switching the switch. One or more may be selected. In this case, the element constants can be switched discontinuously depending on the number of elements to be connected by switching and the connection method (series connection, parallel connection, or a combination thereof).
[0130]
For example, instead of a variable resistor, a plurality of resistors in the n-th power series such as R, 2R, 4R,... Are prepared, and one or any plurality of resistors are selected and connected in series. The switching of resistance values at equal intervals can be easily realized with fewer elements. Similarly, a plurality of 2 n series capacitors having capacitances C, 2C, 4C,... Are prepared instead of capacitors, and one or any plurality of capacitors are selected and connected in parallel. Thus, switching of the capacitance at equal intervals can be easily realized with fewer elements. For this reason, the tuning amplifier according to this embodiment is applied to a circuit having a plurality of tuning frequencies, for example, an AM radio, and is suitable for a purpose of selecting and receiving one station from a plurality of broadcasting stations.
[0131]
The two phase shift circuits included in the above-mentioned various tuning amplifiers are illustrated as being configured using the junction type FET 12 or FET 32. However, the phase shift circuit is configured using a MOS type FET or a bipolar transistor. You may make it do.
[0132]
In a phase shift circuit in which an FET is replaced with a bipolar transistor, a current flows between the base and emitter when an input signal is input to the base, so that the voltage appearing at the emitter (AC voltage) and the voltage appearing at the collector (AC voltage) Is not exactly the same. However, when the current amplification is about several tens to one hundred times, the difference is 1% to several%, and can be ignored in practice. Alternatively, this difference may be corrected by setting the collector resistance slightly larger than the emitter resistance.
[0133]
In particular, when a phase shift circuit is configured using bipolar transistors, the upper limit of the operating frequency can be increased and the potential difference between the base and emitter is smaller than the potential difference between the gate and source of the FET. Attenuation of the signal amplitude input / output to / from the phase circuit can be reduced. Therefore, it is preferable that at least the first-stage phase shift circuit is configured using bipolar transistors. However, since the second-stage phase shift circuit needs to have a high input impedance, it is preferable to use an FET.
[0134]
【The invention's effect】
As is clear from the description based on the above embodiments, the tuning amplifier of the present invention has a maximum attenuation determined by the resistance ratio n between the input side impedance element and the feedback side impedance element, and the tuning frequency in each phase shift circuit. Since it is determined by the time constant of the CR circuit or LR circuit, the maximum attenuation, the tuning frequency, and the gain at the tuning frequency can be set without interfering with each other.
[0135]
Further, when the two phase shift circuits in the tuning amplifier include the CR circuit, the entire tuning amplifier can be easily integrated. Similarly, when the two phase shift circuits are configured to include the LR circuit, the tuning frequency can be easily increased by forming a small inductor by integration. In the case where one phase shift circuit includes a CR circuit and the other phase shift circuit includes an LR circuit, it is possible to stabilize characteristics by preventing fluctuations in characteristics due to temperature or the like.
[0136]
Further, by extracting the signal before passing through the voltage dividing circuit as the output of the tuning amplifier, it is possible to give the tuning amplifier an amplification action.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a tuning amplifier according to a first embodiment to which the present invention is applied.
2 is a circuit diagram showing an extracted configuration of the previous phase shift circuit shown in FIG. 1; FIG.
FIG. 3 is a vector diagram showing a relationship between an input / output voltage of a preceding phase shift circuit and a voltage appearing in a capacitor or the like.
4 is a circuit diagram showing an extracted configuration of a subsequent phase shift circuit shown in FIG. 1. FIG.
FIG. 5 is a vector diagram showing a relationship between an input / output voltage of a subsequent phase shift circuit and a voltage appearing in a capacitor or the like.
FIG. 6 is a circuit diagram in which two phase shift circuits are entirely replaced with a circuit having a predetermined transfer function.
7 is a circuit diagram obtained by converting the configuration shown in FIG. 6 by the mirror theorem.
FIG. 8 is a diagram showing tuning characteristics of the tuning amplifier shown in FIG. 1;
FIG. 9 is a diagram illustrating a phase relationship between signals input to and output from two phase shift circuits included in the tuning amplifier.
FIG. 10 is a circuit diagram showing a configuration of a tuning amplifier according to a second embodiment to which the present invention is applied.
11 is a circuit diagram showing an extracted configuration of the preceding phase shift circuit shown in FIG. 10; FIG.
FIG. 12 is a vector diagram showing the relationship between the input / output voltage of the previous phase shift circuit and the voltage appearing in the inductor or the like.
13 is a circuit diagram showing an extracted configuration of the latter-stage phase shift circuit shown in FIG.
FIG. 14 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit and the voltage appearing in the inductor or the like.
FIG. 15 is a circuit diagram showing a configuration of a tuning amplifier according to a third embodiment to which the present invention is applied;
FIG. 16 is a circuit diagram showing another configuration of the tuning amplifier according to the third embodiment.
FIG. 17 is a diagram illustrating a connection form of a phase shift circuit and a non-inverting circuit.
FIG. 18 is a diagram illustrating a connection form of a phase shift circuit and a phase inversion circuit.
FIG. 19 is a characteristic curve diagram showing an example of a relationship between a tuning frequency, a gain at a tuning frequency, and a maximum attenuation in a conventional tuning amplifier.
[Explanation of symbols]
1 Tuning amplifier
10C, 30C phase shift circuit
12, 32, 52 FET
14, 34 capacitors
16, 18, 20, 40, 38 resistance
36 Variable resistance
50 Non-inverting circuit
70 Feedback resistance
74 Input resistance
90 input terminals
92 Output terminal
160 Voltage divider circuit

Claims (18)

Two cascaded all-pass type phase shift circuits, non-inverting circuits and voltage dividing circuits and the output of the final stage of these cascaded circuits are fed back to the input side of the first stage and this feedback signal and input And an addition circuit for adding the signals to the first stage circuit, and allowing only the signals in the vicinity of the frequency at which the total phase shift amount is 360 ° to pass through the two phase shift circuits as a whole, and the voltage division A tuning amplifier which extracts a signal before being input to a circuit as a tuning output. In claim 1,
Each of the two phase shift circuits converts an input AC signal into an in-phase AC signal and an anti-phase AC signal and outputs the converted AC signal via a capacitor or an inductor. Combining the other AC signal via a resistor, and outputs a signal having a constant amplitude and a phase shifted by a predetermined amount according to the frequency of the input AC signal, A tuning amplifier characterized in that the total amount of phase shift is 360 ° at a certain frequency due to the entire phase shift circuit. In claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
A tuning amplifier, wherein the capacitor and the resistor constituting the CR circuit are connected in the opposite manner in the two phase shift circuits. In claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base An LR circuit composed of the inductor and the resistor constituting the synthesis means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
A tuning amplifier characterized in that the inductor and the resistor constituting the LR circuit are connected in the opposite manner in the two phase shift circuits. In claim 1 or 2,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In one of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
In the other of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. An LR circuit comprising the inductor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
A tuning amplifier characterized in that the reactance element composed of the capacitor or the inductor and the resistor are connected in the opposite manner in the two phase shift circuits. Two cascaded all-pass type phase shift circuits, phase inverting circuits and voltage dividing circuits, and the output of the final stage of these cascaded circuits are fed back to the input side of the first stage and this feedback signal and input And an addition circuit for adding the signals to the first stage circuit, and allowing only the signals in the vicinity of the frequency where the total phase shift amount is 180 ° to pass through the two phase shift circuits as a whole, and the voltage division A tuning amplifier which extracts a signal before being input to a circuit as a tuning output. In claim 6,
Each of the two phase shift circuits converts an input AC signal into an in-phase AC signal and an anti-phase AC signal and outputs the converted AC signal via a capacitor or an inductor. Combining the other AC signal via a resistor, and outputs a signal having a constant amplitude and a phase shifted by a predetermined amount according to the frequency of the input AC signal, A tuning amplifier characterized in that the total amount of phase shift becomes 180 ° at a certain frequency by the whole phase shift circuit. In claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
A tuning amplifier characterized in that the capacitor and the resistor constituting the CR circuit are connected in the same manner in the two phase shift circuits. In claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In the conversion means included in each of the two phase shift circuits, resistors having substantially equal resistance values are connected to the source and drain or to the emitter and collector, respectively, and an AC signal is input to the gate or base An LR circuit composed of the inductor and the resistor constituting the synthesis means is connected between the source and drain of the transistor or between the emitter and collector of the transistor,
A tuning amplifier characterized in that the inductor and the resistor constituting the LR circuit are connected in the same manner in the two phase shift circuits. In claim 6 or 7,
The adder circuit has a feedback side impedance element and an input side impedance element, and adds the feedback signal and the input signal through each of the feedback side impedance element and the input side impedance element. And
In one of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. A CR circuit comprising the capacitor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
In the other of the two phase shift circuits, the conversion means is connected to a source and a drain or to an emitter and a collector, respectively, and a resistor having an approximately equal resistance value, and an AC signal is input to the gate or base. An LR circuit comprising the inductor and the resistor constituting the combining means is connected between the source and drain or between the emitter and collector of the transistor,
A tuning amplifier characterized in that the reactance element composed of the capacitor or the inductor and the resistor are connected in the same manner in the two phase shift circuits. In any one of Claims 1-10,
A tuning amplifier, wherein a tuning frequency is varied by changing a phase shift amount of at least one of the two phase shift circuits. In any one of Claims 3-5 and 8-10,
A tuning amplifier, wherein a tuning frequency is varied by changing a time constant of the CR circuit or the LR circuit included in at least one of the two phase shift circuits. In claim 12,
A tuning amplifier, wherein a resistor included in the CR circuit or the LR circuit is formed by a variable resistor, and a resistance value of the variable resistor is changed. In claim 13,
The variable amplifier is formed of an FET, and a channel resistance between a source and a drain is changed by changing a gate voltage. In claim 13,
A tuning amplifier, wherein the variable resistor is formed by connecting a p-channel FET and an n-channel FET in parallel, and a channel resistance of each FET connected in parallel is changed by changing a gate voltage. In claim 12,
A tuning amplifier, wherein a capacitor included in the CR circuit is formed by a variable capacitance element, and a capacitance of the variable capacitance element is changed. In any one of Claims 3-5 and 8-10,
The feedback-side impedance element and the input-side impedance element are resistors, and the maximum attenuation is changed by varying at least one of the resistance values. In any one of Claims 1-17,
A tuned amplifier, wherein the component parts are integrally formed on a semiconductor substrate.

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