JPH08111612A - Oscillator - Google Patents

Abstract

PURPOSE: To obtain the oscillator easily formed as an integrated circuit, and operated stably while its oscillating frequency is considerably adjusted. CONSTITUTION: The oscillator is made cup of two phase shifter circuits 10, 30 applying a prescribed phase shift by synthesizing signals of in-phase and an opposite phase produced at a source and a drain of an FET via a capacitor or a resistor, a noninverting circuit 50 amplifying an output signal of the phase shift circuit 30 of the post-stage without changing its phase, and a feedback resistor 70 used to feed back the signal outputted from the noninverting circuit 50 to an input of the phase shift circuit 10 of the pre-stage. The oscillated frequency is adjusted by changing a time constant of a series circuit comprising the capacitor and the resistor in the phase shifter circuits 10, 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator which can be easily formed as an integrated circuit and whose oscillation frequency can be adjusted significantly.

[0002]

2. Description of the Related Art Various oscillating circuits using an active element and a reactance element have been proposed and put into practical use as a sine wave oscillator.

[0003]

As a sine wave oscillator,
The Wien bridge oscillator shown in FIG. 21 and the bridge T oscillator shown in FIG. 22 are conventionally known.

As is apparent from FIG. 21, in the Wien bridge type oscillator, the variable resistance Rs of the series circuit of the capacitor C and the variable resistance Rs for changing the frequency.
The resistance value of the variable resistance Rp of the parallel circuit and the resistance value of the variable resistance Rp of the parallel circuit of the capacitor C and the variable resistance Rp must be changed in conjunction with each other. If an interlocking error occurs in the resistance value of, the voltage input to the amplifier A increases or decreases, and as a result, the oscillation output fluctuates. When the oscillation output becomes small, the oscillation stops, and when it becomes large, the oscillation output is significantly distorted.

Generally, it is difficult to stabilize the output of the sine wave oscillator so as to reduce the fluctuation, and the stabilizing means adds nonlinearity to the amplitude characteristic of the amplifier, that is, the amplification degree depends on the magnitude of the output. A characteristic that changes is added.

Since the addition of such characteristics deteriorates the linearity of the amplifier, it deteriorates the distortion factor of the output waveform, and the stability of the output voltage and the distortion coefficient are in the opposite ratio. Have a relationship.

Changing the ratio of the resistance Rs of the series circuit to the variable resistance Rp of the parallel circuit at a constant value is particularly effective when the circuit is integrated and the variable resistance is changed externally by a voltage control method. Have difficulty.

The same applies to not only the Wien-bridge oscillator but also the bridge-T oscillator and the phase-shift oscillator shown in FIG.

Further, it is also difficult to form a variable frequency oscillator whose oscillation frequency can be adjusted significantly by an integrated circuit.

Therefore, the present invention was devised to solve such a problem.

[0011]

In order to solve the above-mentioned problems, an oscillator according to the present invention includes a conversion means for converting an input AC signal into an AC signal of an in-phase and an AC signal of an opposite phase, and outputting the AC signal. Two phase shift circuits including a synthesizing means for synthesizing one of the alternating current signals that has been converted by the capacitor and the other alternating current signal through the resistor, and a predetermined amplification without changing the phase of the input alternating current signal. A non-inverting circuit that amplifies and outputs the first phase, and each of the two phase shift circuits and the non-inverting circuit is cascade-connected, and the output of the final stage of the plurality of cascade-connected circuits is the first stage. Is fed back to the input side of and the sine wave oscillation output is taken out from any one of these plural circuits.

Further, the oscillator of the present invention includes a converting means for converting an input AC signal into an AC signal having an in-phase and an AC signal having an opposite phase, and outputting the converted two AC signals to a first capacitor and a second capacitor. A first phase shift circuit comprising means for synthesizing and shifting the phase via a resistor of, a conversion means for converting an input AC signal into an AC signal of the same phase and an opposite phase, and outputting the AC signal, and A second phase shift circuit comprising means for synthesizing two alternating signals via a second resistor and a second capacitor and shifting the phase in the opposite direction to the first phase shift circuit; A circuit for returning the output of the second phase shift circuit to the input of the first phase shift circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An oscillator according to an embodiment of the present invention will be specifically described below with reference to the drawings.

The oscillator of this embodiment is characterized in that the AC signal is shifted so that the phase shift circuit at the preceding stage for shifting the phase of the AC signal and the phase relationship between the phase shift circuit at the preceding stage and the input / output voltage are opposite to each other. A closed circuit is formed by a post-stage phase shift circuit and a non-inverting circuit that amplifies and outputs the output of the post-stage phase shift circuit at a predetermined amplification degree without changing the phase, and the gain of the closed circuit is set to 1 or more. Set a large value and the total sum of the phase difference of the closed circuit is 0 °
To oscillate at a frequency that

FIG. 1 is a circuit diagram showing a configuration of an oscillator according to an embodiment of the present invention. Oscillator 1 shown in FIG.
Does not change the phase of the output signal of the phase shift circuit 30 and two phase shift circuits 10 and 30 that perform a total phase shift of 0 ° at a predetermined frequency by shifting the phase of the input signal by a predetermined amount. And a feedback resistor 70 that feeds back the output of the non-inverting circuit 50 to the input side of the phase shift circuit 10 at the previous stage. The feedback resistor 70 has a finite resistance value from 0Ω.

FIG. 2 shows the extracted structure of the phase shift circuit 10 at the preceding stage shown in FIG. The phase shift circuit 10 in the previous stage shown in the figure has a FET 12 whose gate is connected to an input end 22.
A variable resistor 14 and a capacitor 16 connected in series between the source and drain of the FET 12, a resistor 18 connected between the drain of the FET 12 and the positive power supply, and between the source of the FET 12 and the negative power supply. It is configured to include the connected resistor 20.

Here, the resistance values of the two resistors 20 and 18 connected to the source and drain of the FET 12 described above are set to be substantially equal, and focusing on the AC component of the input voltage applied to the input end 22, The signal with the same phase is FET
Signals with inverted phases are output from the 12 sources respectively from the drain of the FET 12.

The capacitor 72 provided in the preceding stage of the phase shift circuit 10 shown in FIG. 1 is for blocking a direct current, and its impedance is extremely small at the operating frequency, that is, it has a large capacitance. Have The two resistors 25 and 26 connected in series are for dividing the power supply voltage and applying an appropriate bias voltage to the FET 12.

Further, in the present embodiment, the power supply voltage is applied by the positive power supply and the negative power supply, but the negative power supply side may be replaced with the ground and the single power supply may be operated. In addition, FET
12 can be self-biased, so
25 may be omitted and the bias voltage of the FET 12 may be applied only by the resistor 26.

In the phase shift circuit 10 having such a structure, when a predetermined AC signal is input to the input end 22, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 12, the FET 12 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having a reverse phase to the input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 12. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit composed of a variable resistor 14 and a capacitor 16 is connected between the source and drain of the FET 12. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 12 via the capacitor 16 or the variable resistor 14 is output from the output end 24.

FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10 and the voltage appearing at the capacitor or the like.

Since an AC voltage having the same amplitude and opposite phase as the input voltage and a voltage amplitude of Ei appears at the source and drain of the FET 12, the potential difference (AC component) between the source and the drain becomes 2Ei. Further, the voltage VR1 appearing across the variable resistor 14 and the voltage VC1 appearing across the capacitor 16 are 90 ° out of phase with each other, and a vector combination (addition) of these results between the source and drain of the FET12. Potential difference of 2Ei.

Therefore, as shown in FIG. 3, the voltage Ei
Of the variable resistor 14 and the voltage VC1 across the capacitor 16 are orthogonal to each other to form a right triangle. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR1 across the variable resistor 14 and the voltage VC1 across the capacitor 16 change along the circumference of the semicircle shown in FIG.

By the way, if the potential difference between the connection point of the variable resistor 14 and the capacitor 16 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. , Voltage VR1 and voltage V
It can be represented by a vector whose end point is one point on the circumference where C1 intersects, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

As is clear from FIG. 3, the voltage VR1
And the voltage VC1 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET12 and the voltage VR1 is 9 as the frequency ω changes from 0 to ∞.
It varies from 0 ° to 0 °. The phase shift amount φ1 of the entire phase shift circuit 10 is twice that, and is 1 depending on the frequency.
It varies from 80 ° to 0 °.

Next, the relationship between the input and output voltages described above will be verified quantitatively. FIG. 4 is an equivalent view of the phase shift circuit 10 described above.

The source and drain of the FET 12 are F
Since a voltage in phase with or opposite to the input voltage applied to the gate of ET12 is generated, it can be considered by replacing with two voltage sources 27 and 28 that generate these two voltages. At this time, the current I flowing in the closed loop of the equivalent circuit shown in FIG.
Let C be the capacitance of

[Equation 1] Becomes If the potential difference between the output terminal 24 and the negative power source shown in FIG. 4 is taken out as the output voltage Eo, the voltage Ei
Since the voltage obtained by adding the output voltage Eo and the output voltage Eo is equal to the voltage across the variable resistor 14,

[Equation 2] The relationship is established. By substituting equation (1) into equation (2) above,

(Equation 3) Becomes Here, the time constant of the CR circuit is T (= CR).

Substituting s = jω in the equation (3) and transforming it,

[Equation 4] Becomes When the absolute value of the output voltage Eo is calculated from the equation (4),

(Equation 5) Becomes That is, the expression (5) represents that the phase shift circuit 10 of the present embodiment has a constant amplitude of its output signal, regardless of how the phase between the input and the output rotates.

When the phase shift amount φ1 of the output voltage Eo with respect to the input voltage is calculated from the equation (4),

(Equation 6) Becomes From this equation (6), for example, ω is approximately 1 / T (=
The phase shift amount φ1 at a frequency such that 1 / (CR)) is approximately 90 °. Moreover, by varying the resistance value R of the variable resistor 14, the phase shift amount φ1 is approximately 9
The frequency ω that becomes 0 ° can be changed.

FIG. 5 shows an extracted structure of the phase shift circuit 30 at the latter stage shown in FIG. The phase shift circuit 30 in the latter stage shown in the figure has a FET 32 whose gate is connected to the input end 42.
A capacitor 36 and a variable resistor 34 connected in series between the source and drain of the FET 32, a resistor 38 connected between the drain of the FET 32 and a positive power supply, and a source and a negative power supply of the FET 32. It is configured to include the connected resistor 40.

Similar to the phase shift circuit 10, the FET shown in FIG.
Two resistors 40 connected to 32 sources and drains,
The resistance values of 38 are set to be substantially equal. Focusing on the AC component of the input voltage applied to the input end 42, a signal in phase with the source of the FET 32 and a signal with inverted phase from the drain of the FET 32, respectively. It is supposed to be output.

The resistor 46 provided before the phase shift circuit 30 shown in FIG. 1 is for applying an appropriate bias voltage to the FET 32. Further, the capacitor 48 provided between the phase shift circuits 30 and 10 is for blocking a DC current that removes a DC component from the output of the phase shift circuit 10, and only the AC component is input to the phase shift circuit 30.

In the phase shift circuit 30 having such a structure, when a predetermined AC signal is input to the input terminal 42, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 32, the FET 32 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having the opposite phase to this input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 32. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit composed of a capacitor 36 and a variable resistor 34 is connected between the source and drain of the FET 32. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 32 via the variable resistor 34 or the capacitor 36 is output from the output end 44.

Since an AC voltage having the same phase and the opposite phase to the input voltage and the voltage amplitude of Ei appears at the source and drain of the FET 32, the potential difference between the source and the drain becomes 2Ei. Further, the voltage VC2 appearing across the capacitor 36 and the voltage VR2 appearing across the variable resistor 34 are 9 times each other.
The phase difference is 0 °, and the vector addition of these results in a potential difference 2Ei between the source and drain of the FET 32.
Is equal to

Therefore, as shown in FIG. 6, the voltage Ei
Is set to be a hypotenuse, and a right-angled triangle forming two sides in which the voltage VC2 across the capacitor 36 and the voltage VR2 across the variable resistor 34 are orthogonal to each other is formed. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC2 across the capacitor 36 and the voltage VR2 across the variable resistor 34 change along the circumference of the semicircle shown in FIG.

Assuming that the potential difference between the connection point of the variable resistor 34 and the capacitor 36 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where VC2 and voltage VR2 intersect, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

As is clear from FIG. 6, the voltage VC2
And the voltage VR2 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VC2 becomes 0 as the frequency ω changes from 0 to ∞.
Change from ° to 90 °. The phase shift amount φ2 of the entire phase shift circuit 30 is twice that, and 0 depending on the frequency.
It varies from ° to 180 °.

Next, the relationship between the input and output voltages described above will be verified quantitatively. FIG. 7 is a diagram equivalently showing the phase shift circuit 30 described above.

At the source and the drain of the FET 32, voltages in phase or in opposite phase to the input voltage applied to the gate are generated, so that these two voltages are generated as in the case of the phase shift circuit 10 described above. Two voltage sources 27, 28
Can be replaced with. At this time, the current I flowing in the closed loop of the equivalent circuit shown in FIG.
Let C be the electrostatic capacitance and R be the resistance value of the variable resistor 34, then the above equation (1) can be used. Therefore, if the potential difference between the output terminal 44 and the negative power supply shown in FIG. 7 is taken out as the output voltage Eo, the voltage obtained by adding the voltage Ei and the output voltage Eo is equal to the voltage across the capacitor 36.

(Equation 7) The relationship is established. By substituting equation (1) into equation (7) above,

(Equation 8) Becomes Here, as in the case of the phase shift circuit 10, the time constant of the CR circuit is T.

Substituting s = jω in this equation (8) and transforming it,

[Equation 9] Becomes

The equations (8) and (9) described above are used in the phase shift circuit 10
Only the sign is different from the equations (3) and (4) calculated for. Therefore, as for the absolute value of the output voltage Eo, the equation (5) can be applied as it is, and the amplitude of the output signal of the phase shift circuit 30 is constant no matter how the phase between the input and the output rotates. It means that.

When the phase shift amount φ2 of the output voltage Eo with respect to the input voltage is calculated from the equation (9),

[Equation 10] Becomes From this equation (10), for example, ω is approximately 1 / T (=
The phase shift amount φ2 at a frequency that becomes 1 / (CR)) is approximately 90 °. In addition, by changing the resistance value R of the variable resistor 34, the phase shift amount φ2 is approximately 9
The frequency ω that becomes 0 ° can be changed.

In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10 and 30. Moreover,
As shown in FIG. 3 and FIG. 6, the relative phase relationships of the input and output voltages in the phase shift circuits 10 and 30 are in opposite directions,
At a certain frequency, the two phase shift circuits 10 and 30 together output a signal having a phase shift amount of 0 °.

In the non-inverting circuit 50 shown in FIG. 1, a resistor 54 is connected between the drain and the positive power source, and a resistor 56 is connected between the source and the negative power source.
The transistor 58 is connected to the drain of the ET52 and has a collector connected to the source via a resistor 60. A resistor 62 provided in the preceding stage of the non-inverting circuit 50 is for applying an appropriate bias voltage to the FET 52, and a capacitor 64 is for blocking a DC current that removes a DC component from the output of the phase shift circuit 30. Only the AC component is input to the non-inverting circuit 50.

When an alternating current signal is input to the gate of the FET 52, the FET 52 outputs a reverse phase signal from the drain. Further, the transistor 58 outputs a signal of the same phase from the collector when the signal of the opposite phase is input to the base, considering the signal of which the phase is further inverted, that is, the phase of the signal input to the gate of the FET 52 as a reference. , This in-phase signal is a non-inverting circuit
Output from 50. The output of the non-inverting circuit 50 is taken out from the output terminal 92 as the output of the oscillator 1, and
It is fed back to the input side of the preceding phase shift circuit 10 via the feedback resistor 70.

The amplification factor of the non-inverting circuit 50 described above is
The loop gain of the oscillator 1 shown in FIG. 1 is set to 1 or more by adjusting the resistance value of each of the resistors 54, 56, 60 described above and adjusting the resistance value of each of these resistors. That is, since the signal amplitude is actually attenuated and the loop gain becomes considerably smaller than 1, it is possible to set the loop gain to 1 or more by supplementing this attenuation by amplification by the non-inverting circuit 50. . By setting the loop gain to 1 or more in this way, sine wave oscillation is performed at a frequency such that the phase shift amount becomes 0 ° when the closed loop makes one round.

FIG. 8 is a system diagram in which the entire two phase shift circuits 10 and 30 and the non-inverting circuit 50 having the above-described configuration are replaced with a circuit having a transfer function K1. A closed loop is formed by the feedback resistor 70 having the value R0. FIG. 9 is a system diagram in which the system shown in FIG. 8 is converted by the Miller's theorem. When the feedback resistor 70 having a resistance value R0 is converted into an input shunt resistance as shown in FIG.

[Equation 11] Can be represented by

In this equation, considering that K1 is larger than 1, it can be seen that the input shunt resistance Rs becomes a negative resistance.

Assuming that the ideal phase shift circuit (all-pass network) having the transfer function K1 satisfies the condition that the phase shift amount is 0 ° at an arbitrary finite frequency, it is selective at this frequency. A negative resistance will be realized and oscillation will be possible. Actually, the input shunt resistance is in the form of being connected in parallel with the input impedance of the phase shift circuit, and it is necessary that a composite of these is a negative resistance, but the resistance value R0 of the feedback resistance 70 is set low, Since it is extremely easy to set the input impedance of the phase shift circuit to be high, it is theoretically possible to ignore the influence of the input impedance of the phase shift circuit.

By the way, as is apparent from the equation (3), the transfer function K2 of the phase shift circuit 10 in the preceding stage is

(Equation 12) As is clear from the equation (8), the phase shift circuit 30
The transfer function K3 of

(Equation 13) Is. However, assuming that the time constants of the CR circuits in the phase shift circuits 10 and 30 are different, they are set to T ₁ and T ₂ , respectively.

Therefore, the overall transfer function K1 when the phase shift circuits 10 and 30 are cascaded in two stages is

[Equation 14] Becomes It should be noted that, as described above, two phase shift circuits are actually used.
The loop gain is set to 1 or more by connecting the non-inverting circuit 50 at the stage subsequent to 10 and 30, but the transfer functions K2 and K3 represented by the equations (12) and (13) are different in each phase shift circuit. It was obtained assuming that there is no signal amplitude attenuation, and (14)
The transfer function K1 obtained from the equation is actually two phase shift circuits 1
It becomes the same as the overall transfer function in which the non-inverting circuit 50 is connected to 0 and 30.

Here, in order to simplify the calculation, s = j
ω, s ² = −ω ² , A = 1 + T ₁ · T ₂ · s ² = 1−T ₁ · T
₂ · ω ² and B = T ₁ + T ₂

(Equation 15) Becomes In this equation (15), if the phase difference between the input and output of the entire phase shift circuits 10 and 30 connected in two stages is 0 °, (15)
Since the imaginary term on the right side of the equation must be 0, the following equation holds.

[Equation 16] Therefore, 1-T ₁ · T ₂ · ω ² = 0 or ω = 0. Here, when ω = 0, the input signal is DC and the phase difference is 180 °, so that the other condition (1
Ω = 1 / √ (T ₁ · T ₂ ) satisfying −T ₁ · T ₂ · ω ² = 0)
At this time, the phase difference becomes 0 °. At this frequency, the input shunt resistance Rs becomes a negative resistance and simultaneously satisfies the oscillation voltage condition and the frequency condition.

As described above, by combining the two phase shift circuits 10 and 30, the phase shift amount of the signal that goes through the closed loop can be made 0 ° at a certain frequency, and the loop gain at this time is larger than 1. By doing so, the sine wave oscillation is sustained. Further, the frequency at which the amount of phase shift becomes 0 ° is the variable resistor 14 or
Since it can be changed by changing the resistance value of 34, a variable frequency oscillator can be easily realized.

The oscillator 1 of this embodiment is constructed by combining FETs, capacitors or resistors,
Since all the constituent elements can be formed on the semiconductor substrate, it is easy to form the entire voltage-controlled oscillator 1 on the semiconductor substrate to form an integrated circuit.

In the oscillator 1 of this embodiment described above, the phase shift circuit 10 is arranged at the front stage and the phase shift circuit 30 is arranged at the rear stage. Therefore, as shown in FIG. 10, the front and rear of these are interchanged, and the phase shift circuit 30 is provided in the front stage.
The oscillator 1a may be configured by arranging the phase shift circuits 10 in the subsequent stages.

Further, although the non-inverting circuit 50 included in the oscillator 1 of the present embodiment described above is configured to include the bipolar transistor 58, it may be replaced with an FET and configured by a two-stage source grounded circuit. May be. In this case, all the transistors used in the oscillator 1 are F
Since it is unified by ET, the manufacturing process can be simplified.

By the way, the oscillator of this embodiment described above is composed of two phase shift circuits and a non-inverting circuit, and the total amount of phase shift is 0 ° at a predetermined frequency by the entire three connected circuits. By doing so, predetermined oscillation is performed. Therefore, focusing only on the amount of phase shift, there is some degree of freedom in the order in which the three circuits are connected, and the connection order can be determined as necessary.

11 and 12 show two phase shift circuits 1
FIG. 6 is a diagram showing a connection state between 0 and 30 and a non-inverting circuit 50. In these figures, the feedback impedance element 70
Most commonly, a uses a feedback resistor 70 as shown in FIG. However, the feedback impedance element 70a may be formed by a capacitor or an inductor, or may be formed by combining a resistor, a capacitor or an inductor.

FIG. 11A shows a configuration in which a non-inverting circuit 50 is arranged at the subsequent stage of the two phase shift circuits 10 and 30.
It corresponds to the oscillator 1 shown in FIG. FIG. 11B shows a configuration in which the non-inverting circuit 50 is arranged at the subsequent stage of the two phase shift circuits 30 and 10, and corresponds to the oscillator 1a shown in FIG. As described above, when the non-inverting circuit 50 is arranged in the subsequent stage, a large output current can be taken out by giving the non-inverting circuit 50 a function of an output buffer.

The configuration in which the non-inverting circuit 50 is arranged between the two phase shift circuits 10 and 30 in FIG. 11C is shown in FIG. 11D.
A configuration in which a non-inverting circuit 50 is arranged between the two phase shift circuits 30 and 10 is shown. In this way, when the non-inverting circuit 50 is arranged in the middle, the phase shift circuit 10 or
Mutual interference between 30 and the phase shift circuit 30 or 10 in the subsequent stage can be completely prevented.

FIG. 12A shows a configuration in which the non-inverting circuit 50 is arranged in front of the two phase shift circuits 10 and 30, but FIG.
A configuration in which a non-inverting circuit 50 is arranged in front of the two phase shift circuits 30 and 10 is shown. In this way, when the non-inverting circuit 50 is arranged in the previous stage, the phase shift circuit 10 or
The influence of the feedback side impedance element 70a on 30 can be minimized.

Further, the phase shift circuits 10 and 30 shown in the above-mentioned embodiments include the variable resistors 14 and 34.
These variable resistors 14 and 34 can be specifically realized by using a junction type or MOS type FET.

FIG. 13 is a diagram showing the configuration of the phase shift circuit in the case where the variable resistor 14 or 34 in the two types of phase shift circuits shown in this embodiment is replaced with an FET.

FIG. 6A shows a configuration in which the variable resistor 14 is replaced with an FET in the one phase shift circuit 10 shown in FIG. 1 and the like. FIG. 2B shows a configuration in which the variable resistor 34 in the other phase shift circuit 30 shown in FIG.

As described above, the channel formed between the source and drain of the FET is used as a resistor to change the variable resistance.
When used in place of 14 or 34, the gate voltage can be variably controlled to arbitrarily change the channel resistance within a certain range to change the amount of phase shift in each phase shift circuit. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that makes a round in each oscillator becomes 0 °, so that the oscillation frequency can be arbitrarily changed.

In each phase shift circuit shown in FIG. 13, the variable resistance is composed of one FET, that is, a p-channel or n-channel FET.
Alternatively, T and n-channel FETs may be connected in parallel to form one variable resistor, and gate voltages of equal magnitude but different polarities may be applied between the gate and substrate of each FET. When changing the resistance value, the magnitude of the gate voltage may be changed. As described above, by combining the two FETs to form the variable resistance, it is possible to improve the non-linear region of the FETs, so that the distortion of the oscillation output can be reduced.

Further, the phase shift circuit 10 or 30 shown in each of the above-described embodiments changes the resistance value of the variable resistor 14 or 34 connected in series with the capacitors 16 and 36 to change the phase shift amount. Although the overall oscillation frequency is changed by means of, the capacitors 16, 36 may be formed of variable capacitance elements, and the overall oscillation frequency may be changed by changing the capacitance thereof.

FIG. 14 is a diagram showing the structure of the phase shift circuit in the case where the capacitors 16 or 36 in the two types of phase shift circuits shown in this embodiment are replaced by variable capacitance diodes.

FIG. 1A shows a structure in which the variable resistor 14 is replaced with a fixed resistor and the capacitor 16 is replaced with a variable capacitance diode in the one phase shift circuit 10 shown in FIG. 1 and the like. FIG. 2B shows a configuration in which the variable resistor 34 is replaced with a fixed resistor and the capacitor 36 is replaced with a variable capacitance diode in the other phase shift circuit 30 shown in FIG. 1 and the like.

In FIGS. 14A and 14B, the capacitor connected in series to the variable capacitance diode blocks its direct current when a reverse bias voltage is applied between the anode and cathode of the variable capacitance diode. The impedance is extremely small at the operating frequency, that is, it has a large capacitance. In addition, since the potentials at both ends of the capacitor shown in FIGS. 14A and 14B are constant when the DC component is seen, by applying a reverse bias voltage larger than the amplitude of the AC component between the anode and the cathode, Each variable capacitance diode can function as a variable capacitance capacitor.

In this way, the capacitor 16 or 36 is composed of a variable capacitance diode, and the magnitude of the reverse bias voltage applied between its anode and cathode is variably controlled to control the capacitance of this variable capacitance diode within a certain range. The amount of phase shift in each phase shift circuit can be changed by changing the value arbitrarily. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency.

By the way, although the variable capacitance diode is used as the variable capacitance element in FIGS. 14A and 14B described above, the FET in which the source and the drain are connected to a fixed potential in a direct current and the variable voltage is applied to the gate is used. May be used. As described above, the potentials at both ends of the variable capacitance diodes shown in FIGS. 14A and 14B are fixed in terms of direct current.
It is only necessary to replace it with T, and the gate capacitance, that is, the electrostatic capacitance of the FET can be changed by changing the voltage applied to the gate.

Further, although only the capacitance of the variable capacitance diode is changed in FIGS. 14A and 14B described above, the resistance value of the variable resistor 14 or 34 may be changed at the same time. FIG. 14C shows one phase shift circuit 10 shown in FIG.
2 shows a configuration in which the variable resistor 14 is used and the capacitor 16 is replaced with a variable capacitance diode.
FIG. 2D shows a configuration in which the variable resistor 34 is used and the capacitor 36 is replaced with a variable capacitance diode in the other phase shift circuit 30 shown in FIG. 1 and the like. In these, a variable capacitance diode is used as a gate capacitance variable FET
Of course, it may be replaced with.

Needless to say, the variable resistance shown in FIGS. 14C and 14D can be formed by utilizing the channel resistance of the FET as shown in FIG. In particular,
When a p-channel FET and an n-channel FET are connected in parallel to form one variable resistor and gate voltages of equal magnitude and different polarities are applied between the base and substrate of each FET, Since the nonlinear region can be improved, the distortion of the oscillation output can be reduced.

As described above, even when a variable resistance and a variable capacitance element are combined to form a phase shift circuit, the resistance value of the variable resistance and the capacitance of the variable capacitance element can be arbitrarily changed within a certain range. The amount of phase shift in each phase shift circuit can be changed. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency.

In addition to the case where the variable resistance or the variable capacitance element is used as described above, a plurality of resistors or capacitors having different element constants are prepared and the switch is switched to select from among the plurality of elements. One or more may be selected. In this case, the element constants can be discontinuously switched by the number of elements to be connected and the connection method (serial connection, parallel connection, or a combination thereof) by switching the switches. For example, instead of a variable resistor, a plurality of 2 n-th series resistors whose resistance values are R, 2R, 4R, ...
By selecting one or an arbitrary plurality and connecting them in series, it is possible to easily realize switching of resistance values at equal intervals with a smaller number of elements. Similarly, instead of the capacitors, prepare a plurality of 2 n-th series capacitors having capacitances of C, 2C, 4C, ... And select one or an arbitrary plurality of capacitors for parallel connection. Thus, it is possible to easily realize the switching of the electrostatic capacitances at equal intervals with a smaller number of elements.

When the oscillator 1 of each of the above-described embodiments is formed on a semiconductor substrate, a large capacitance cannot be set as the capacitor 16 or 36 in practice. Therefore, if the capacitance can be increased apparently by devising a circuit of small capacitance of the capacitor actually formed on the semiconductor substrate, the time constant T can be set to a large value to reduce the oscillation frequency. It is convenient for.

FIG. 15 shows the phase shift circuits 10 and 30 shown in FIG.
FIG. 11 is a diagram showing a modified example in which the capacitor 16 or 36 used for is composed of a circuit instead of a single element, and functions as a capacitance conversion circuit that makes the capacitance of a capacitor actually formed on a semiconductor substrate look large. To do. In addition,
The entire circuit shown in FIG. 15 corresponds to the capacitor 16 or 36 included in the phase shift circuit 10 or 30.

The capacitance conversion circuit 16a shown in FIG. 15 comprises a capacitor 210 having a predetermined capacitance C0, two operational amplifiers 212 and 214, and four resistors 216, 218, 220 and 222. Has been done.

In the first-stage operational amplifier 212, a resistor 218 (whose resistance value is R18) is connected between the output terminal and the inverting input terminal, and the inverting input terminal is a resistor.
It is grounded through 216 (this resistance is R16).

Between the voltage E1 applied to the non-inverting input terminal of the first stage operational amplifier 212 and the voltage E2 appearing at the output terminal,

[Equation 17] There is a relationship. The first-stage operational amplifier 212 mainly functions as a buffer that performs impedance conversion, and the gain may be 1. R18 when the gain is 1
When / R16 = 0, that is, R16 is set to infinity (removing the resistor 216), or R18 is set to 0Ω (direct connection).

Further, the operational amplifier 214 of the second stage has a resistor 222 (this resistance value is set to R22 between the output terminal and the inverting input terminal).
And a resistor 220 (whose resistance value is R20) is connected between the inverting input terminal and the output terminal of the operational amplifier 212 described above, and the non-inverting input terminal is grounded. There is.

When the voltage appearing at the output terminal of the second stage operational amplifier 214 is E3, the voltage E3 between this voltage E3 and the voltage E2 appearing at the output terminal of the first stage operational amplifier 212 is:

(Equation 18) There is a relationship. In this way, the second-stage operational amplifier 214 functions as an inverting amplifier, and the first-stage operational amplifier 212 is set in order to set its input side to high impedance.
Is used.

Further, the non-inverting input terminal of the first-stage operational amplifier 212 and the second-stage operational amplifier 2 having such a connection are connected.
As described above, the capacitor 210 having a predetermined electrostatic capacity is connected between the 14 output terminals.

In the capacitance conversion circuit 16a shown in FIG. 15, when the transfer function of the entire circuit except the capacitor 210 is K4, the capacitance conversion circuit 16a can be represented by the system diagram shown in FIG. FIG. 17 is a system diagram in which this is converted by the Miller's theorem.

If the impedance Z0 shown in FIG. 16 is used to represent the impedance Z1 shown in FIG.

[Formula 19] Becomes Here, the capacitance conversion circuit 16a shown in FIG.
In the case of, the impedance Z0 = 1 / (jωC0), and by substituting this into the equation (19),

(Equation 20)

[Equation 21] Becomes In the equation (21), the capacitance C0 of the capacitor 210 in the capacitance conversion circuit 16a is apparently (1-
K4) shows that it has doubled.

Therefore, when the gain K4 is negative, (1-K4) is always larger than 1, so that the electrostatic capacitance C0 can be changed to the larger one.

By the way, the gain of the amplifier in the capacitance conversion circuit 16a shown in FIG.
The gain K4 of the amplifier formed by the whole of
From equation and (18),

[Equation 22] Becomes Substituting equation (22) into equation (21),

(Equation 23) Becomes Therefore, by setting the resistance value of the four resistors 216, 218, 220, 222 to a predetermined value, the two terminals 22
The apparent capacitance C between 4 and 226 can be increased.

When the gain of the amplifier by the first stage operational amplifier 212 is 1, that is, when R16 is set to infinity (resistor 216 is removed) or R18 is set to 0Ω as described above, R18 / R16 If = 0, then (2
Equation 3 is simplified to

[Equation 24] Becomes

FIG. 18 is a diagram showing the configuration of the capacitance conversion circuit 16b in which the resistor 216 connected to the inverting input terminal of the first operational amplifier 212 shown in FIG. 15 is removed. In this case, since the electrostatic capacitance C appearing between the terminals 224 and 226 is expressed by the equation (24), C0 can be changed to a larger value by changing the ratio of R22 and R20.

As described above, the capacitance conversion circuit 16 described above
a or 16b is a resistance ratio of the resistance 220 and the resistance 222 R22 /
By changing R20 or the resistance ratio R18 / R16 of the resistor 216 and the resistor 218, the electrostatic capacitance C0 of the capacitor 210 actually formed on the semiconductor substrate can be converted to an apparently larger one. Therefore, when the whole of the oscillator 1 and the like shown in FIG. 1 and the like is formed on the semiconductor substrate, the capacitor 210 having a small capacitance C0 is formed on the semiconductor substrate, and the capacitor 210 shown in FIG. The circuit shown in FIG. 18 allows conversion into a large capacitance C, which is convenient for integration. In particular, if a large capacitance can be secured in this way, the oscillator 1 shown in FIG.
It is also possible to reduce the total mounting area of the above, and to reduce the material cost.

At least one of the resistors 216, 218, 220, 222 (at least one of the resistors 220, 222 in the case of the capacitance conversion circuit 16b shown in FIG. 18) is formed by a variable resistor. Therefore, specifically, the junction type or MOS type F
By connecting the ET or p-channel FET and the n-channel FET in parallel to form a variable resistance, it is possible to easily form a capacitor having a variable capacitance.
Therefore, by using this capacitor instead of the variable capacitance diode shown in FIG. 14, the phase shift amount can be arbitrarily changed within a certain range. Therefore, the phase shift amount of the signal that makes one round in the oscillator is 0 °.
Can be changed, and the oscillation frequency of the oscillator described above can be changed arbitrarily.

Since the first stage operational amplifier 212 is used as a buffer for increasing the input impedance as described above, the operational amplifier 212 may be replaced with an emitter follower circuit or a source follower circuit.

FIG. 19 is a diagram showing the configuration of the electrostatic capacitance conversion circuit 16c using the emitter follower circuit in the first stage. The capacitance conversion circuit 16c shown in the figure includes an emitter follower circuit 22 including a first-stage operational amplifier 212 and two resistors 216 and 218 shown in FIG.
It has a configuration replaced with 8.

FIG. 20 is a diagram showing the configuration of the capacitance conversion circuit 16d using the source follower circuit in the first stage. The capacitance conversion circuit 16d shown in the figure has a configuration in which the first-stage operational amplifier 212 and the two resistors 216 and 218 shown in FIG. 15 are replaced with a source follower circuit 230 including an FET and a resistor.

The capacitance conversion circuits 16c and 16 described above are also provided.
Each of d is a resistor 2 connected to the operational amplifier 214.
The point that the apparent capacitance C between the terminals 224 and 226 can be arbitrarily changed by changing the resistance ratio of the resistors 20 and 222 is the same as the capacitance conversion circuit 16a shown in FIG. 15 and the like. . Therefore, at least one of the resistors 220 and 222 is
By replacing the junction type or MOS type FET or the variable resistor in which the p-channel FET and the n-channel FET are connected in parallel, a variable capacitance capacitor can be constructed. By using it instead of the capacitance diode, the phase shift amount can be arbitrarily changed within a certain range. Therefore, in each oscillator, the phase shift amount of the signal that makes one round is 0
It is possible to change the frequency at which the angle becomes °, and the oscillation frequency can be changed arbitrarily.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

For example, although the oscillator 1 and the like of the above-described embodiments include two phase shift circuits, when the oscillation frequency is variable, the resistors forming the CR circuits included in both phase shift circuits are included. In addition to changing the element constant of at least one of the capacitor and the capacitor, there may be a case of changing the element constant of at least one of the resistor and the capacitor forming the CR circuit included in the one phase shift circuit. Alternatively, the variable resistors 14 and 34 in each phase shift circuit may be replaced with resistors having a fixed resistance value to form an oscillator having a fixed oscillation frequency.

When the oscillator of the above-mentioned embodiment is integrated on a semiconductor substrate, electrodes are formed by sandwiching an insulating film such as a silicon oxide film, or the FET is used as described above.
It is possible to form a capacitor in the phase shift circuit by utilizing the gate capacitance of.

Further, in FIG. 1 and the like described above, the case where the phase shift circuit 10 or the like is configured by using the junction type FET 12 or FET 32 is illustrated, but the phase shift circuit is formed by the MOS type FET or the bipolar transistor. It may be configured.

In a phase shift circuit in which the FET is replaced with a bipolar transistor, a current flows between the base and the emitter when an input signal is input to the base, so that the voltage appearing at the emitter (AC voltage) and the voltage appearing at the collector ( AC voltage) is not exactly the same. However, when the current amplification factor is several tens to one hundred times, the difference is 1% to several%, which can be practically ignored.
Alternatively, this difference may be corrected by setting the collector resistance slightly larger than the emitter resistance.

In particular, when the phase shift circuit is constructed by using the bipolar transistor, the upper limit of the operating frequency can be increased, and the potential difference between the base and the emitter is F.
Since it is smaller than the potential difference between the gate and source of ET, it is possible to reduce the attenuation of the signal amplitude input to and output from the phase shift circuit. Therefore, it is preferable that at least the first-stage phase shift circuit 10 or 30 is configured by using bipolar transistors. However, since the second-stage phase shift circuit needs to have a high input impedance, it is preferable to use FETs.

Further, in the oscillator of the above-mentioned embodiment, the sine wave signal is taken out from one of the two phase shift circuits 10 and 30 and the non-inverting circuit 50 constituting the oscillator.
You may make it take out a sine wave signal from two or all in one circuit. In particular, when the time constants of the two phase shift circuits 10 and 30 forming the oscillator are set to be the same, the phase shift amount in each phase shift circuit becomes 90 °, so that the phases are deviated from each other by 90 °. The phase output can be taken out.

[0106]

As is clear from the description based on each of the above embodiments, each element constituting the oscillator of the present invention can be formed by the manufacturing method of an integrated circuit, so that the oscillator is integrated on a semiconductor wafer. It can be made small as a circuit,
It can be manufactured inexpensively by mass production.

In particular, the channel between the source and drain of the FET is used as the variable resistance of the CR circuit in each phase shift circuit, and the resistance of the channel is changed by changing the control voltage applied to the gate of this FET. Then, it is possible to avoid the influence of the inductance and the capacitance of the wiring to which the control voltage is applied, and it is possible to obtain an oscillator having ideal characteristics almost as designed.

Further, in the conventional oscillator utilizing LC resonance, the oscillation frequency ω is 1 / √LC, so if the capacitance C or the inductance L is changed in order to adjust the oscillation frequency, the oscillation frequency becomes Although it changes in proportion to the square root of the amount of change, in the oscillator of the present invention, the oscillation frequency ω is, for example, 1 / (CR), and the oscillation frequency should be changed in proportion to the resistance value R or the capacitance C. Therefore, the oscillation frequency can be greatly changed and adjusted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an oscillator of an embodiment to which the invention is applied,

FIG. 2 is a diagram showing an extracted configuration of a phase shift circuit in the preceding stage shown in FIG.

FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit and the voltage appearing at a capacitor or the like;

FIG. 4 is an equivalent view of the phase shift circuit shown in FIG.

FIG. 5 is a diagram showing an extracted configuration of a phase shift circuit at a subsequent stage shown in FIG.

FIG. 6 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit and the voltage appearing at a capacitor or the like;

7 is an equivalent view of the phase shift circuit shown in FIG.

FIG. 8 is a system diagram in which the entire two phase shift circuits are replaced with a circuit having a transfer function K1.

FIG. 9 is a system diagram obtained by converting the system shown in FIG. 8 according to Miller's theorem,

FIG. 10 is a diagram showing a modification of the oscillator of this embodiment,

FIG. 11 is a diagram showing a connection form of a phase shift circuit and a non-inverting circuit;

FIG. 12 is a diagram showing a connection form of a phase shift circuit and a non-inverting circuit;

FIG. 13 is a diagram showing a configuration of a phase shift circuit in which a variable resistance of the phase shift circuit is replaced with an FET,

FIG. 14 is a diagram showing a configuration of a phase shift circuit in which a capacitor of the phase shift circuit is replaced with a variable capacitance diode;

FIG. 15 is a diagram showing a configuration of a capacitance conversion circuit that apparently increases the capacitance that a capacitor actually has;

16 is a diagram showing the circuit shown in FIG. 15 using a transfer function,

FIG. 17 is a diagram in which the configuration shown in FIG. 16 is converted by the Miller's theorem,

FIG. 18 is a diagram showing a configuration of a capacitance conversion circuit which is a simplified version of the circuit of FIG. 15;

FIG. 19 is a diagram showing a configuration of a capacitance conversion circuit using an emitter follower circuit in the first stage,

FIG. 20 is a diagram showing a configuration of a capacitance conversion circuit using a source follower circuit in the first stage,

FIG. 21 is a circuit diagram showing an example of a conventional sine wave oscillator,

FIG. 22 is a circuit diagram showing an example of a conventional sine wave oscillator.

[Explanation of symbols]

 1 Oscillator 10, 30 Phase shift circuit 12, 32 Field effect transistor (FET) 14, 34 Variable resistor 16, 36 Capacitor 18, 20, 38, 40 Resistor 50 Non-inverting circuit 70 Feedback resistor 92 Output terminal

Claims (16)

[Claims] 1. A conversion means for converting an input AC signal into an in-phase and an opposite-phase AC signal and outputting the AC signal, and one AC signal converted by the conversion means and a resistance of the other AC signal via a capacitor. And a non-inverting circuit that amplifies and outputs the input AC signal at a predetermined amplification level without changing the phase of the input AC signal. Each of the phase circuit and the non-inverting circuit is connected in cascade, and the output of the final stage of the plurality of circuits connected in cascade is fed back to the input side of the first stage, and a sine wave oscillation is generated from any of these circuits. An oscillator characterized by taking out the output. 2. The conversion means included in the phase shift circuit according to claim 1, wherein the source and the drain, or the emitter and the collector are respectively connected to resistors having substantially equal resistance values, and a gate or The base is composed of a transistor to which an input signal is input, and a series circuit composed of the capacitor and the resistor forming the combining means is connected between the source and drain of the transistor or between the emitter and collector of the transistor, An oscillator characterized in that a connection method of a capacitor and the resistor is reversed in the two phase shift circuits. 3. The oscillator according to claim 1, wherein a two-phase output is taken out from the two phase shift circuits and the non-inverting circuit. 4. The oscillation frequency according to claim 1, wherein the resistance of the synthesizing means included in at least one of the two phase shift circuits is formed by a variable resistance, and the resistance value is changed. Oscillator characterized by changing. 5. The oscillator according to claim 4, wherein the variable resistance is formed by a channel of an FET, and a channel voltage is changed by changing a gate voltage. 6. The channel according to claim 4, wherein the variable resistor is formed by connecting a p-channel type FET and an n-channel type FET in parallel, and changing the magnitude of the gate voltage of each FET having a different polarity. An oscillator characterized by changing resistance. 7. The oscillator according to claim 1, wherein the capacitor of the synthesizing means included in at least one of the two phase shift circuits is formed of a variable capacitance element, and the capacitance is changed. An oscillator characterized by changing the frequency. 8. The oscillator according to claim 7, wherein the variable capacitance element is formed of a variable capacitance diode whose reverse bias voltage can be changed or an FET whose gate capacitance can be changed by changing the gate voltage. 9. The resistor according to claim 1, wherein a resistance value of the synthesizing means included in at least one of the two phase shift circuits is a plurality of resistors having a fixed resistance value. An oscillator characterized in that the oscillation frequency is changed by selectively connecting. 10. The switch according to claim 1, wherein a plurality of capacitors having a fixed electrostatic capacitance are provided as the capacitors of the synthesizing means included in at least one of the two phase shift circuits, and the switches are switched. An oscillator characterized in that the oscillation frequency is changed by selectively connecting with. 11. The capacitor according to claim 1, wherein the capacitor of the combining means included in at least one of the two phase shift circuits is provided between an amplifier having a negative gain and an input / output of the amplifier. An oscillator characterized in that the capacitance seen from the input side of the amplifier is made larger than the capacitance actually possessed by the capacitor element by replacing it with a capacitor element connected in parallel with. 12. The oscillator according to claim 11, wherein the oscillation frequency is changed by changing the gain of the amplifier to change the electrostatic capacitance viewed from the input side of the amplifier. 13. A conversion means for converting an input AC signal into an in-phase and an opposite-phase AC signal and outputting the AC signal, and combining the two converted AC signals via a first capacitor and a first resistor. And a phase shifting circuit for converting the input AC signal into in-phase and anti-phase AC signals and outputting the converted AC signals. A second phase-shifting circuit comprising means for synthesizing via a second resistor and a second capacitor and shifting the phase in the opposite direction to the first phase-shifting circuit; A circuit for returning an output to the input of the first phase shift circuit, and an oscillator. 14. The oscillator according to claim 13, wherein the oscillation frequency is changed by changing the first resistance of the first phase shift circuit and / or the second resistance of the second phase shift circuit. Oscillator. 15. The oscillator according to claim 13, wherein each resistance of the first and second phase shift circuits is formed by a channel of an FET. 16. The oscillator according to claim 1, which is formed as a semiconductor integrated circuit.