JPH0865045A - Oscillator - Google Patents

Abstract

PURPOSE: To provide a stably operating oscillator for which remarkably the oscillation frequency can be adjusted over a wide range. CONSTITUTION: This oscillator is provided with two phase shift circuits 10C and 30L for performing prescribed phase shift by synthesizing the signals of the same phase and an opposite phase generated in the source and drain of an FET through a capacitor and a resistor or an inductor and the resistor, a non-inversion circuit 50 for performing amplification without changing the phase of the output signals of the phase shift circuit 30L of a poststage and a feedback resistor 70 for feeding back the signals outputted from the non- inversion circuit 50 to the input side of the phase shift circuit 10C of a prestage. By changing the time constant of a serial circuit composed of the capacitor and the resistor or the serial circuit composed of the inductor and the resistor inside the phase shift circuits 10C and 30L, the oscillation frequency is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator whose oscillation frequency can be adjusted significantly.

[0002]

2. Description of the Related Art Various oscillating circuits using an active element and a reactance element have been proposed and put into practical use as a sine wave oscillator.

[0003]

As a sine wave oscillator,
The Wien bridge type oscillator shown in FIG. 48 and the bridge T type oscillator shown in FIG. 49 are conventionally known.

As is apparent from FIG. 48, in the Wien bridge type oscillator, the variable resistance Rs of the series circuit of the capacitor C and the variable resistance Rs is changed in order to change the frequency.
The resistance value of the variable resistance Rp of the parallel circuit and the resistance value of the variable resistance Rp of the parallel circuit of the capacitor C and the variable resistance Rp must be changed in conjunction with each other. If an interlocking error occurs in the resistance value of, the voltage input to the amplifier A increases or decreases, and as a result, the oscillation output fluctuates. When the oscillation output becomes small, the oscillation stops, and when it becomes large, the oscillation output is significantly distorted.

Generally, it is difficult to stabilize the output of the sine wave oscillator so as to reduce the fluctuation, and the stabilizing means adds nonlinearity to the amplitude characteristic of the amplifier, that is, the amplification degree depends on the magnitude of the output. A characteristic that changes is added.

Since the addition of such characteristics deteriorates the linearity of the amplifier, it deteriorates the distortion factor of the output waveform, and the stability of the output voltage and the distortion coefficient are in the opposite ratio. Have a relationship.

Changing the ratio of the resistance Rs of the series circuit to the variable resistance Rp of the parallel circuit at a constant value is particularly effective when the circuit is integrated and the variable resistance is changed by a voltage control method from the outside. Have difficulty.

The same applies to not only the Wien bridge oscillator but also the bridge T oscillator and the phase shift oscillator shown in FIG.

Further, it is also difficult to form a variable frequency oscillator whose oscillation frequency can be adjusted significantly by an integrated circuit.

Therefore, the present invention was devised to solve such a problem.

[0011]

In order to solve the above-mentioned problems, an oscillator according to the present invention includes a conversion means for converting an input AC signal into an AC signal of an in-phase and an AC signal of an opposite phase, and outputting the AC signal. A first phase shift circuit including a synthesizing means for synthesizing one of the alternating current signals converted via the capacitor and the other alternating current signal via the resistor; and an in-phase and anti-phase alternating current signal of the input alternating current signal. A second phase-shifting circuit including: a converting unit that converts to and outputs the AC signal converted by the converting unit and a combining unit that combines the one AC signal through the inductor and the other AC signal through the resistor; A non-inverting circuit for amplifying and outputting the input AC signal at a predetermined amplification level without changing the phase of the AC signal;
Cascade connection of each of the phase shift circuit and the non-inverting circuit,
The output of the final stage of the plurality of circuits connected in cascade is fed back to the input side of the first stage, and the sine wave oscillation output is taken out from any of the plurality of circuits.

Further, the oscillator of the present invention has a conversion means for converting an input AC signal into in-phase and anti-phase AC signals and outputting the AC signal, and one AC signal converted by the conversion means via a capacitor. A first phase shift circuit including a synthesizing unit that synthesizes the other AC signal via a resistor, a converting unit that converts the input AC signal into in-phase and anti-phase AC signals, and outputs the AC signals, and the converting unit. A second phase shift circuit including a synthesizing means for synthesizing one of the alternating current signals converted by means of the inductor and the other alternating current signal via the resistor; And a phase inversion circuit that amplifies and outputs with an amplification degree,
Each of the first and second phase shift circuits and the phase inversion circuit is connected in cascade, and the output of the final stage of the plurality of circuits connected in cascade is fed back to the input side of the first stage, It is characterized in that the sine wave oscillation output is taken out from any of the circuits.

Further, the oscillator of the present invention includes a converting means for converting an input AC signal into an in-phase and anti-phase AC signal and outputting the AC signal, and one of the two AC signals thus converted, which is either a capacitor or an inductor. A first-stage phase-shift circuit including a first reactance element composed of and a means for synthesizing a phase via a first resistor and a phase shifter, and converting an input AC signal into an in-phase and an in-phase AC signal And outputs the converted two AC signals through a second reactance element composed of the other one of a capacitor and an inductor via a second resistor to generate the first AC signal.
A second-stage phase-shift circuit including means for shifting the phase in the opposite direction to the second-stage phase-shift circuit; a non-inverting circuit that outputs the output of the second-stage phase-shift circuit in the same phase; A circuit for returning the output of the non-inverting circuit to the input of the first-stage phase shift circuit.

In the oscillator of the present invention, a converting means for converting an input AC signal into an AC signal of an in-phase and an AC signal of an opposite phase and outputting the AC signal, and one of the two AC signals thus converted is a capacitor or an inductor. A first-stage phase-shift circuit including a first reactance element composed of and a means for synthesizing a phase via a first resistor and a phase shifter, and converting an input AC signal into an in-phase and an in-phase AC signal And outputs the converted two AC signals through a second reactance element composed of the other one of a capacitor and an inductor via a second resistor to generate the first AC signal.
A second-stage phase-shift circuit that shifts the phase in the same direction as the second-stage phase-shift circuit, a phase-inverting circuit that inverts the phase of the output of the second-stage phase-shift circuit, and an output of the phase-inverting circuit Is fed back to the input of the phase shift circuit of the first stage.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An oscillator according to an embodiment of the present invention will be specifically described below with reference to the drawings.

The oscillators of the following embodiments are characterized in that the AC signal is shifted so that the phase shift circuit at the preceding stage for shifting the phase of the AC signal and the phase relationship between the phase shift circuit at the preceding stage and the input / output voltage are opposite to each other. A closed circuit is formed by a post-stage phase shift circuit and a non-inverting circuit that amplifies and outputs the output of the post-stage phase shift circuit at a predetermined amplification degree without changing the phase, and the gain of the closed circuit is set to 1 Set it to a larger value and the total sum of the phase differences of the closed circuit is 0.
It is to oscillate at a frequency of °.

Alternatively, the oscillator of the following embodiments is characterized in that a phase shift circuit in the preceding stage for shifting the phase of an AC signal,
Inverts the phase of the output of the phase shift circuit of the latter stage and the phase shift circuit of the latter stage that shifts the AC signal so that the phase relationship between the phase shift circuit of the former stage and the input / output voltage is the same and amplifies it with a predetermined amplification Then, a closed circuit is formed by the output phase inversion circuit, and the gain of the closed circuit is set to be larger than 1, and the oscillation operation is performed at a frequency at which the total phase difference of the closed circuit becomes 0 °.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of an oscillator according to a first embodiment of the present invention. Each of the oscillators 1 shown in the figure shifts the phase of the input signal by a predetermined amount, so that a total of 0 is obtained at a predetermined frequency.
Two phase shift circuits 10C and 30L for phase shift of °
And a non-inverting circuit 50 that amplifies and outputs the signal at a predetermined amplification level without changing the phase of the output signal of the subsequent phase-shifting circuit 30L, and outputs the output of the non-inverting circuit 50 to the input side of the preceding phase-shifting circuit 10C. The feedback resistor 70 is included for feedback. This feedback resistor
70 has a finite resistance value from 0Ω.

FIG. 2 shows a phase shift circuit 10C in the preceding stage shown in FIG.
The configuration of is extracted and shown. The phase shift circuit 10C at the previous stage shown in the figure is an FE in which the gate is connected to the input end 22.
T12, a variable resistor 14 and a capacitor 16 connected in series between the source and drain of the FET 12, a resistor 18 connected between the drain of the FET 12 and a positive power supply, and a FET
It is configured to include a resistor 20 connected between 12 sources and a negative power source.

Here, the resistance values of the two resistors 20 and 18 connected to the source and drain of the FET 12 described above are set to be substantially equal, and focusing on the AC component of the input voltage applied to the input end 22, The signal with the same phase is FET
Signals with inverted phases are output from the 12 sources respectively from the drain of the FET 12.

The capacitor 72 provided before the phase shift circuit 10C shown in FIG. 1 is for blocking a direct current, and its impedance is extremely small at the operating frequency, that is, it has a large electrostatic capacitance. Have
The two resistors 25 and 26 connected in series are for dividing the power supply voltage and applying an appropriate bias voltage to the FET 12.

Further, in this embodiment, the power source voltage is applied by the positive power source and the negative power source, but the negative power source side may be replaced with ground and the single power source may be used for operation. Furthermore, FE
Since T12 can be self-biased, the resistor 25 may be omitted and the bias voltage of the FET 12 may be applied only by the resistor 26.

In the phase shift circuit 10C having such a configuration, when a predetermined AC signal is input to the input terminal 22, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 12, the FET 12 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having a reverse phase to the input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 12. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit composed of a variable resistor 14 and a capacitor 16 is connected between the source and drain of the FET 12. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 12 via the capacitor 16 or the variable resistor 14 is output from the output end 24.

FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10C and the voltage appearing at the capacitor or the like.

Since an AC voltage having the same phase and opposite phase as the input voltage and a voltage amplitude of Ei appears at the source and drain of the FET 12, the potential difference (AC component) between the source and the drain becomes 2Ei. Further, the voltage VR1 appearing across the variable resistor 14 and the voltage VC1 appearing across the capacitor 16 are 90 ° out of phase with each other, and a vector combination (addition) of these results between the source and drain of the FET12. Potential difference of 2Ei.

Therefore, as shown in FIG. 3, the voltage Ei
Of the variable resistor 14 and the voltage VC1 across the capacitor 16 are orthogonal to each other to form a right triangle. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR1 across the variable resistor 14 and the voltage VC1 across the capacitor 16 change along the circumference of the semicircle shown in FIG.

By the way, if the potential difference between the connection point of the variable resistor 14 and the capacitor 16 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. , Can be represented by a vector whose end point is one point on the circumference where the voltage VR1 and the voltage VC1 intersect, and the size thereof is equal to the radius Ei of the semicircle.
Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

As is clear from FIG. 3, the voltage VR1
And the voltage VC1 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET12 and the voltage VR1 is 9 as the frequency ω changes from 0 to ∞.
It varies from 0 ° to 0 °. The phase shift amount φ1 of the entire phase shift circuit 10C is twice that and changes from 180 ° to 0 ° depending on the frequency.

Next, the relationship between the input and output voltages described above will be verified quantitatively. FIG. 4 is an equivalent view of the phase shift circuit 10C described above.

The source and drain of the FET 12 are F
Since a voltage in phase with or opposite to the input voltage applied to the gate of ET12 is generated, it can be considered by replacing with two voltage sources 27 and 28 that generate these two voltages. At this time, the current I flowing in the closed loop of the equivalent circuit shown in FIG.
Let C be the capacitance of

[Equation 1] Becomes If the potential difference between the output terminal 24 and the negative power supply shown in FIG. 4 is taken out as the output voltage Eo, the sum of the voltage Ei and the output voltage Eo is equal to the voltage across the variable resistor 14,

[Equation 2] The relationship is established. By substituting equation (1) into equation (2) above,

(Equation 3) Becomes Here, the time constant of the CR circuit is T (= CR).

Substituting s = jω in the equation (3) and transforming it,

[Equation 4] Becomes When the absolute value of the output voltage Eo is calculated from the equation (4),

(Equation 5) Becomes That is, the equation (5) is the phase shift circuit 10 of this embodiment.
C represents that the amplitude of the output signal is constant no matter how the phase between the input and output rotates.

Further, when the phase shift amount φ1 with respect to the input voltage of the output voltage Eo is obtained from the equation (4),

(Equation 6) Becomes From this equation (6), for example, ω is approximately 1 / T (=
The phase shift amount φ1 at a frequency such that 1 / (CR)) is approximately 90 °. Moreover, by varying the resistance value R of the variable resistor 14, the phase shift amount φ1 is approximately 9
The frequency ω that becomes 0 ° can be changed.

FIG. 5 shows a phase shift circuit 30L at the latter stage shown in FIG.
The configuration of is extracted and shown. The phase shift circuit 30L at the latter stage shown in the figure is an FE in which the gate is connected to the input end 42.
T32, an inductor 37 and a variable resistor 34 connected in series between the source and drain of the FET 32, a resistor 38 connected between the drain of the FET 32 and the positive power supply, and a FET
The resistor 40 is connected between the source of 32 and the negative power source.

Similar to the phase shift circuit 10C, the FE shown in FIG.
Two resistors 4 connected to the source and drain of T32.
The resistance values of 0 and 38 are set to be almost equal, and the input end 42
Focusing on the alternating-current component of the input voltage applied to, the phase-matched signal is output from the source of the FET 32, and the phase-inverted signal is output from the FET 32 drain.

Further, the capacitor 39 inserted between the inductor 37 and the source of the FET 32 is for blocking direct current, and its impedance is extremely small at the operating frequency, that is, it has a large capacitance. The capacitor 48 provided in the preceding stage of the phase shift circuit 30L shown in FIG. 1 is also for blocking the DC current, and only the AC component is input to the phase shift circuit 30L. Further, the resistor 46 is for applying an appropriate bias voltage to the FET 32.

In the phase shift circuit 30L having such a structure, when a predetermined AC signal is input to the input terminal 42, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 32, the FET 32 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having the opposite phase to this input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 32. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit composed of an inductor 37 and a variable resistor 34 is connected between the source and drain of the FET 32. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 32 via the inductor 37 or the variable resistor 34 is output from the output end 44.

Since an AC voltage having the same phase and opposite phase as the input voltage and the voltage amplitude of Ei appears at the source and drain of the FET 32, the potential difference between the source and drain is 2
It becomes Ei. In addition, the voltage VR2 that appears across the variable resistor 34
And the voltage VL1 appearing across the inductor 37 are 90
The phases are out of phase, and the vector addition of these is equal to the potential difference 2Ei between the source and drain of the FET 32.

Therefore, as shown in FIG. 6, the voltage Ei
Of the variable resistor 34 and the voltage VL1 across the inductor 37 are orthogonal to each other to form a right triangle. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR2 across the variable resistor 34 and the voltage VL1 across the inductor 37 change along the circumference of the semicircle shown in FIG.

Assuming that the potential difference between the connection point between the inductor 37 and the variable resistor 34 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where VR2 and voltage VL1 intersect,
Its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

As is clear from FIG. 6, the voltage VR2
And the voltage VL1 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VR2 becomes 0 as the frequency ω changes from 0 to ∞.
Change from ° to 90 °. The phase shift amount φ2 of the entire phase shift circuit 30L is twice that, and changes from 0 ° to 180 ° depending on the frequency.

Next, the relationship between the input and output voltages described above will be verified quantitatively. FIG. 7 is a diagram equivalently showing the above-mentioned phase shift circuit 30L.

At the source and the drain of the FET 32, voltages in phase or in reverse phase with the input voltage applied to the gate are generated, respectively, so that these two voltages are generated as in the case of the phase shift circuit 10C described above. Two voltage sources 27,
It can be replaced by 28. At this time, the current I ′ flowing in the closed loop of the equivalent circuit shown in FIG.
If the resistance value of 34 is R and the inductance of inductor 37 is L,

(Equation 7) Becomes If the potential difference between the output terminal 44 and the negative power supply shown in FIG. 7 is taken out as the output voltage Eo, the sum of the voltage Ei and the output voltage Eo is equal to the voltage across the variable resistor 34.

[Equation 8] The relationship is established. By substituting equation (7) into equation (8) above,

[Equation 9] Becomes Here, in order to simplify the explanation, the time constant of the LR circuit is set to T, similarly to the time constant of the CR circuit in the phase shift circuit 10C.

Substituting s = jω in the equation (9) and transforming it,

[Equation 10] Becomes

The equations (9) and (10) described above are equivalent to the phase shift circuit 1
Only the signs are different from the expressions (3) and (4) calculated for 0C. Therefore, for the absolute value of the output voltage Eo, the equation (5) can be applied as it is, and the phase shift circuit 30L has a constant amplitude of its output signal regardless of how the phase between the input and the output rotates. It means that.

Further, when the phase shift amount φ2 of the output voltage Eo with respect to the input voltage is obtained from the equation (10),

[Equation 11] Becomes From this equation (11), for example, ω is approximately 1 / T (=
R / L) Phase shift amount φ2 at the frequency
Is approximately 90 °. Moreover, by changing the resistance value R of the variable resistor 34, the frequency ω at which the phase shift amount φ2 becomes approximately 90 ° can be changed.

In this way, the two phase shift circuits 10C and 30
The phase is shifted by a predetermined amount in each of L. Moreover, as shown in FIGS. 3 and 6, each of the phase shift circuits 10C and 30
The relative phase relationships of the input and output voltages at L are in opposite directions, and the two phase shift circuits 10C and 30L at a certain frequency
, The signal whose phase shift amount is 0 ° is output.

Further, in the non-inverting circuit 50 shown in FIG. 1, a resistor 54 is connected between the drain and the positive power source, a resistor 56 is connected between the source and the negative power source, and a base is F.
The transistor 58 is connected to the drain of the ET52 and has a collector connected to the source via a resistor 60. A resistor 62 provided in the preceding stage of the non-inverting circuit 50 is for applying an appropriate bias voltage to the FET 52, and a capacitor 64 is for blocking a DC current that removes a DC component from the output of the phase shift circuit 30L. Only the AC component is input to the non-inverting circuit 50.

When the AC signal is input to the gate of the FET 52, the FET 52 outputs a signal of opposite phase from the drain. Further, the transistor 58 outputs a signal of the same phase from the collector when the signal of the opposite phase is input to the base, considering the signal of which the phase is further inverted, that is, the phase of the signal input to the gate of the FET 52 as a reference. , This in-phase signal is a non-inverting circuit
Output from 50. The output of the non-inverting circuit 50 is taken out from the output terminal 92 as the output of the oscillator 1, and
It is fed back to the input side of the preceding phase shift circuit 10C via the feedback resistor 70.

The amplification factor of the non-inverting circuit 50 described above is
The loop gain of the oscillator 1 shown in FIG. 1 is set to 1 or more by adjusting the resistance value of each of the resistors 54, 56, 60 described above and adjusting the resistance value of each of these resistors. That is, since the signal amplitude is actually attenuated and the loop gain becomes considerably smaller than 1, it is possible to set the loop gain to 1 or more by supplementing this attenuation by amplification by the non-inverting circuit 50. . By setting the loop gain to 1 or more in this way, sine wave oscillation is performed at a frequency such that the phase shift amount becomes 0 ° when the closed loop makes one round.

FIG. 8 is a system diagram in which the entire two phase shift circuits 10C and 30L and the non-inverting circuit 50 having the above-mentioned configuration are replaced with a circuit having a transfer function K1.
A closed loop is formed by the circuit having 1 and the feedback resistor 70 having a resistance value R0. FIG. 9 is a system diagram in which the system shown in FIG. 8 is converted by the Miller's theorem. When the feedback resistor 70 having a resistance value R0 is converted into an input shunt resistance as shown in FIG.

[Equation 12] Can be represented by

Considering the case where K1 is larger than 1 in this equation, it can be seen that the input shunt resistance Rs becomes a negative resistance.

Assuming that the ideal phase shift circuit (all-pass network) having the transfer function K1 satisfies the condition that the phase shift amount is 0 ° at an arbitrary finite frequency, it is selective at this frequency. A negative resistance will be realized and oscillation will be possible. Actually, the input shunt resistance is in the form of being connected in parallel with the input impedance of the phase shift circuit, and it is necessary that a composite of these is a negative resistance, but the resistance value R0 of the feedback resistance 70 is set low, Since it is extremely easy to set the input impedance of the phase shift circuit to be high, it is theoretically possible to ignore the influence of the input impedance of the phase shift circuit.

By the way, as is apparent from the equation (3), the transfer function K2 of the phase shift circuit 10C in the preceding stage is

[Equation 13] As is clear from the equation (9), the phase shift circuit 30
The transfer function K3 of L is

[Equation 14] Is. However, assuming that the time constant of the CR circuit in the phase shift circuit 10C and the time constant of the LR circuit in the phase shift circuit 30L are different, they are set to T ₁ and T ₂ , respectively.

Therefore, when the phase shift circuits 10C and 30L are cascade-connected in two stages, the overall transfer function K1 is

(Equation 15) Becomes It should be noted that, as described above, two phase shift circuits are actually used.
The loop gain is set to 1 or more by connecting the non-inverting circuit 50 in the subsequent stage of 10C and 30L, but the transfer functions K2 and K3 represented by the equations (13) and (14) are different in each phase shift circuit. It was calculated as one in which there is no attenuation of the signal amplitude,
The transfer function K1 obtained by the equation (15) is actually the same as the overall transfer function in which the non-inverting circuit 50 is connected to the two phase shift circuits 10C and 30L.

Here, in order to simplify the calculation, s = j
ω, s ² = −ω ² , A = 1 + T ₁ · T ₂ · s ² = 1−T ₁ · T
₂ · ω ² and B = T ₁ + T ₂

[Equation 16] Becomes In this equation (16), the phase shift circuits 10C and 30L are
In order for the phase difference between the input and output of all the stages connected to become 0 °,
Since the imaginary term on the right side of equation (16) must be 0, the following equation holds.

[Equation 17] Therefore, 1-T ₁ · T ₂ · ω ² = 0 or ω = 0. Here, when ω = 0, the input signal is DC and the phase difference is 180 °, so that the other condition (1
Ω = 1 / √ (T ₁ · T ₂ ) satisfying −T ₁ · T ₂ · ω ² = 0)
At this time, the phase difference becomes 0 °. At this frequency, the input shunt resistance Rs becomes a negative resistance and simultaneously satisfies the oscillation voltage condition and the frequency condition.

As described above, by combining the two phase shift circuits 10C and 30L, the phase shift amount of the signal that goes through the closed loop can be set to 0 ° at a certain frequency, and the loop gain at this time becomes 1 or more. By setting, sine wave oscillation is maintained. Also, the phase shift amount is 0
The frequency that becomes ° is the variable resistance in each phase shift circuit 10C, 30L.
Since it can be changed by changing the resistance value of 14 or 34, a variable frequency oscillator can be easily realized.

In the oscillator 1 of this embodiment, the inductor 37 can be formed on the semiconductor substrate by forming a spiral conductor by photolithography or the like. By using, it is easy to form the entire oscillator 1 on the semiconductor substrate together with other components (FET, resistor or capacitor) to form an integrated circuit.

The time constant T of the CR circuit of the preceding phase shift circuit 10C is 1 / (CR), and L of the latter phase shift circuit 30L is L.
Since the time constant T of the R circuit is R / L, and the resistance value R is divided into the denominator and the numerator in each, the entire oscillator 1 is formed on the semiconductor substrate and each variable resistor 1
When the FETs 4 and 34 are formed, it is possible to perform so-called temperature compensation, which suppresses the variation of the tuning frequency with respect to the temperature variation of the resistance value. The point that this temperature compensation is possible is the same in the oscillators of the respective embodiments described below.

The oscillator 1 of the first embodiment shown in FIG.
Is provided with a DC current blocking capacitor between each of the phase shift circuits 10C and 30L and the non-inverting circuit 50, and F
Although a resistor for bias application is connected to the gate of ET so that each circuit operates at an optimum operating point, as shown in FIG. 10, an appropriate operating point is obtained in the state where a capacitor for blocking direct current is omitted. The element constant of each element may be adjusted so that

Further, in the oscillator 1 of the first embodiment, the phase shift circuit 10C is arranged in the front stage and the phase shift circuit 30L is arranged in the rear stage, but the phase shift amount between the input and output signals is 0 ° due to the whole of them. Therefore, the oscillator may be configured by replacing the front and the rear of these and arranging the phase shift circuit 30L in the front stage and the phase shift circuit 10C in the rear stage.

Further, although the non-inverting circuit 50 included in the oscillator 1 of this embodiment described above is configured to include the bipolar transistor 58, it may be replaced with an FET and configured by a two-stage source grounded circuit. May be. In this case, all the transistors used for the oscillator 1 and the like are unified by the FETs, so that the manufacturing process can be simplified.

(Second Embodiment) FIG. 11 is a circuit diagram showing a structure of an oscillator according to a second embodiment of the invention. Similar to the oscillator 1 of the first embodiment, the oscillator 1a shown in the figure includes two phase shift circuits each of which shifts the phase of an input signal by a predetermined amount to perform a total phase shift of 0 ° at a predetermined frequency. 10L, 30C, a non-inverting circuit 50 that amplifies and outputs a predetermined amplification degree without changing the phase of the output signal of the phase-shifting circuit 30C, and the output of the non-inverting circuit 50 is the input side of the phase-shifting circuit 10L in the preceding stage. It is configured to include a feedback resistor 70 for returning to.

FIG. 12 shows the phase shift circuit of the preceding stage shown in FIG.
The structure of 10 L is extracted and shown. The preceding stage phase shift circuit 10L shown in the figure includes a FET 12 having a gate connected to an input end 22, a variable resistor 14 and an inductor 17 connected in series between a source and a drain of the FET 12, and an FET.
A resistor 18 connected between the drain of 12 and the positive power supply, and
It is configured to include a resistor 20 connected between the source of ET12 and the negative power supply. As described in the first embodiment,
The resistance values of the two resistors 18 and 20 are set to be substantially equal. The capacitor 19 inserted between the inductor 17 and the drain of the FET 12 is for blocking DC current,
Its impedance is very small at the operating frequency, ie it has a large capacitance.

In the phase shift circuit 10L having such a configuration, when a predetermined AC signal is input to the input end 22, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 12, the FET 12 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having a reverse phase to the input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 12. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit including a variable resistor 14 and an inductor 17 is connected between the source and drain of the FET 12. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 12 via the variable resistor 14 or the inductor 17 is output from the output end 24.

FIG. 13 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10L and the voltage appearing in the inductor or the like.

Since an AC voltage having the same phase and opposite phase as the input voltage and a voltage amplitude of Ei appears at the source and drain of the FET 12, the potential difference (AC component) between the source and the drain becomes 2Ei. Further, VL2 appearing across the inductor 17 and the voltage VR3 appearing across the variable resistor 14 are 90 ° out of phase with each other, and a vector combination (addition) of these results between the source and drain of the FET 12. It becomes equal to the potential difference 2Ei.

Therefore, as shown in FIG.
The double side of i is a hypotenuse, and a right triangle forming two sides where the voltage VL2 across the inductor 17 and the voltage VR3 across the variable resistor 14 are orthogonal to each other is formed. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VL2 across the inductor 17 and the voltage VR3 across the variable resistor 14 change along the circumference of the semicircle shown in FIG.

By the way, assuming that the potential difference between the connection point of the inductor 17 and the variable resistor 14 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. , Voltage VL2 and voltage VR3
It can be represented by a vector whose end point is one point on the circumference where and intersect, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

As is clear from FIG. 13, the voltage V
Since L2 and voltage VR3 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET12 and the voltage VL2 is 90 ° as the frequency ω changes from 0 to ∞. It changes to 0 °. The phase shift amount φ3 of the entire phase shift circuit 10L is twice that, and changes from 180 ° to 0 ° depending on the frequency.

Next, the relationship between the input and output voltages described above will be quantitatively verified. FIG. 14 is an equivalent view of the phase shift circuit 10L described above.

The source and drain of the FET 12 are F
Since a voltage in phase with or opposite to the input voltage applied to the gate of ET12 is generated, it can be considered by replacing with two voltage sources 27 and 28 that generate these two voltages. At this time, the current I ′ flowing in the closed loop of the equivalent circuit shown in FIG. 14 is represented by the equation (7) shown in the first embodiment, where L is the inductance of the inductor 17 and R is the resistance value of the variable resistor 14. You can Therefore, if the potential difference between the output terminal 24 and the negative power source shown in FIG. 14 is taken out as the output voltage Eo, the sum of the voltage Ei and the output voltage Eo is equal to the voltage across the inductor 17,

(Equation 18) The relationship is established. By substituting equation (7) into equation (18) above,

[Formula 19] Becomes Here, the time constant of the LR circuit in the phase shift circuit 10L is the same as the time constant of the CR circuit or the LR circuit in the two phase shift circuits 10C and 30L shown in the first embodiment, T (= L /
R).

This equation (19) is the same as the equation (3) shown in the first embodiment, and the phase shift circuit 10L of this embodiment has the same input / output voltage as the phase shift circuit 10C of the first embodiment. It is understood that they have a relationship of. Therefore, the phase shift circuit 10L indicates that the amplitude of its output signal is constant no matter how the phase between the input and output rotates.

Further, as the phase shift amount φ3 of the output voltage Eo with respect to the input voltage, φ1 represented by the above equation (6) is applied as it is, and for example, ω becomes approximately 1 / T (= R / L). The amount of phase shift at the frequency is approximately 90 °. Moreover, by changing the resistance value R of the variable resistor 14, the frequency ω at which the phase shift amount becomes approximately 90 ° can be changed.

FIG. 15 shows a phase shift circuit of the latter stage shown in FIG.
The structure of 30C is extracted and shown. The subsequent phase shift circuit 30C shown in the figure includes a FET 32 having a gate connected to an input end 42, a capacitor 36 and a variable resistor 34 connected in series between the source and drain of the FET 32, and an FET.
A resistor 38 connected between the drain of 32 and the positive power supply, and
It comprises a resistor 40 connected between the source of the ET32 and the negative power supply. As described in the first embodiment,
The resistance values of the two resistors 38 and 40 are set to be substantially equal.

In the phase shift circuit 30C having such a structure, when a predetermined AC signal is input to the input terminal 42, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 32, the FET 32 is turned on. An AC voltage having the same phase as this input voltage appears at the source, and conversely, an AC voltage having the opposite phase to this input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 32. The amplitude of the AC voltage appearing at the source and drain is both Ei.

A series circuit composed of a capacitor 36 and a variable resistor 34 is connected between the source and drain of the FET 32. Therefore, a signal obtained by combining the voltages appearing at the source and the drain of the FET 32 via the variable resistor 34 or the capacitor 36 is output from the output end 44.

FIG. 16 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30C and the voltage appearing at the capacitor or the like.

Since an AC voltage having the same phase and opposite phase as the input voltage and the voltage amplitude of Ei appears at the source and drain of the FET 32, the potential difference between the source and drain is 2
It becomes Ei. In addition, the voltage VC appearing across the capacitor 36
2 and the voltage VR4 appearing across the variable resistor 34 are 90
The phases are out of phase, and the vector addition of these is equal to the potential difference 2Ei between the source and drain of the FET 32.

Therefore, as shown in FIG.
A double side of i is a hypotenuse, and a right-angled triangle forming two sides where the voltage VC2 across the capacitor 36 and the voltage VR4 across the variable resistor 34 are orthogonal to each other is formed. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC2 across the capacitor 36 and the voltage VR4 across the variable resistor 34 change along the circumference of the semicircle shown in FIG.

If the potential difference between the connection point of the variable resistor 34 and the capacitor 36 and the negative power source is taken out as the output voltage Eo, this output voltage Eo starts from the center point of the semicircle shown in FIG. , Voltage VC2 and voltage VR4
It can be represented by a vector whose end point is one point on the circumference where and intersect, and its size is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so a stable output in which the output amplitude does not change according to the frequency can be obtained.

Further, as is clear from FIG. 16, the voltage V
Since C2 and voltage VR4 intersect at a right angle on the circumference, theoretically, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VC2 is 0 ° as the frequency ω changes from 0 to ∞. Change up to 90 °. The phase shift amount φ4 of the entire phase shift circuit 30C is twice that, and changes from 0 ° to 180 ° depending on the frequency.

Next, the relationship between the input and output voltages described above will be verified quantitatively. FIG. 17 is an equivalent view of the phase shift circuit 30C described above.

At the source and the drain of the FET 32, a voltage having the same phase or an opposite phase as the input voltage applied to the gate is generated, respectively. Therefore, these two voltages are generated.
It can be considered by replacing the two voltage sources 27 and 28. At this time, the current I flowing in the closed loop of the equivalent circuit shown in FIG. 17 is expressed by the equation (1) shown in the first embodiment, where C is the capacitance of the capacitor 36 and R is the resistance value of the variable resistor 34. be able to. Therefore, if the potential difference between the output terminal 44 and the negative power supply shown in FIG. 17 is taken out as the output voltage Eo, the voltage obtained by adding the voltage Ei and the output voltage Eo is the capacitor.
Since it is equal to the voltage across 36,

[Equation 20] The relationship is established. By substituting equation (1) into equation (20),

[Equation 21] Becomes Here, the time constant of the CR circuit of the phase shift circuit 30C is set to T as in the case of the LR circuit of the phase shift circuit 10L.

This equation (21) is the same as the equation (9) shown in the first embodiment, and the phase shift circuit 30C of this embodiment has the same input / output voltage as the phase shift circuit 30L of the first embodiment. It is understood that they have a relationship of. Therefore, the phase shift circuit 30 represents that the amplitude of its output signal is constant no matter how the phase between the input and the output rotates.

Further, as the phase shift amount φ4 of the output voltage Eo with respect to the input voltage, φ2 expressed by the above equation (11) is applied as it is, and for example, ω is approximately 1 / T (= 1 / (CR)).
The amount of phase shift at the frequency
Becomes Moreover, by changing the resistance value R of the variable resistor 14, the frequency ω at which the phase shift amount becomes approximately 90 ° can be changed.

In this way, the two phase shift circuits 10L and 30
The phase is shifted by a predetermined amount in each of C. Moreover, as shown in FIGS. 13 and 16, each phase shift circuit 10
The relative phase relationships of the input and output voltages at L and 30C are in opposite directions, and two phase shift circuits 10
A signal whose phase shift amount is 0 ° is output by the entire L and 30C.

The non-inverting circuit 50 shown in FIG. 11 is the same as that shown in FIG. 1 in the first embodiment. When an AC signal is input to the gate of the FET 52, the input AC is input from the collector of the transistor 58. An AC signal in phase with the signal is output. The output of the non-inverting circuit 50 is fed back to the input side of the preceding phase shift circuit 10L via the feedback resistor 70.

The amplification factor of the non-inverting circuit 50 is
It is determined by the resistance values of 54, 56, and 60, and by adjusting the resistance values of these resistances, the loop gain of the oscillator 1a whose configuration is shown in FIG. 11 is set to 1 or more. Sine wave oscillation is performed at a frequency such that the amount of phase shift is 0 °.

By the way, the above-mentioned two phase shift circuits 10L,
Oscillator 1a of the second embodiment including 30C and non-inverting circuit 50
Can be represented by the system diagram shown in FIG. 8 as in the case of the first embodiment by replacing the whole with a circuit having a transfer function K1. Therefore, it can be expressed by the system diagram shown in FIG. 9 by converting by the Miller's theorem, and the input shunt resistance Rs of the converted system is (1
It can be expressed by equation (2).

As is clear from the equations (19) and (21), the transfer functions of the two phase shift circuits 10L and 30C of this embodiment are the same as those of the two phase shift circuits 10C and 10C of the first embodiment. It is the same as each transfer function of 30L, and the overall transfer function K1 when the non-inverting circuit 50 is connected to the latter stage of the two phase shift circuits 10L and 30C is
The one shown in the equation (16) can be applied as it is.
Therefore, the phase difference becomes 0 ° when ω = 1 / √ (T ₁ · T ₂ ), between the entire input / output in which the two phase shift circuits 10L and 30C are connected, and the oscillation voltage condition and the frequency condition are satisfied. Will be satisfied at the same time.

As described above, by combining the two phase shift circuits 10L and 30C, the phase shift amount of the signal that goes through the closed loop can be set to 0 ° at a certain frequency, and the loop gain at this time becomes 1 or more. By setting, sine wave oscillation is maintained. Also, the phase shift amount is 0
The frequency that becomes ° is the variable resistance in each phase shift circuit 10L, 30C.
Since it can be changed by changing the resistance value of 14 or 34, a variable frequency oscillator can be easily realized.

Further, as in the first embodiment, the inductor 17
Can be formed on a semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an inductor 17, other components (FET, resistor or capacitor) can be formed. It is also easy to form the entire oscillator 1a on a semiconductor substrate to form an integrated circuit.

In the oscillator 1a of the second embodiment shown in FIG. 11, a DC current blocking capacitor is provided between each of the phase shift circuits 10L and 30C and the non-inverting circuit 50, and a bias is applied to the gate of the FET. Each circuit operates at an optimum operating point by connecting a resistor for each element. However, as shown in FIG. 18, each element is operated at an appropriate operating point in the state where a capacitor for blocking direct current is omitted. The element constant of may be adjusted.

Further, in the oscillator 1a of this embodiment, the phase shift circuit 10L and the phase shift circuit 30C are arranged in the front and rear stages, respectively, but the phase shift amount between the input and output signals cannot be 0 ° due to the whole of them. Therefore, the oscillator may be configured by arranging the front and rear of these and arranging the phase shift circuit 30C in the front stage and the phase shift circuit 10L in the rear stage.

(Third Embodiment) The oscillator 1 of the first embodiment described above is constructed by combining two phase shift circuits in which the relative phase relationship between the input and the output is opposite. The oscillator may be configured by combining two phase shift circuits having the same relationship.

One phase shift circuit 10C included in the oscillator 1 shown in FIG. 1 and the phase shift circuit included in the oscillator 1a shown in FIG.
Equation (3) or (19) between each input and output voltage of 10L
The relationship expressed by the formula is established. In the following, the phase shift circuit 10C or 10L having the configuration shown in FIG.
For convenience, description will be given by using the fractional sign in the equation (3) as a “− type phase shift circuit”.

The phase shift circuit 30L included in the oscillator 1 shown in FIG. 1 and the phase shift circuit included in the oscillator 1a shown in FIG.
Equation (9) or (21) between each input and output voltage of 30C
The relationship expressed by the formula is established. In the following, the phase shift circuit 30C or 30L having the configuration shown in FIG.
For the sake of convenience, the sign of the fraction in the expression (9) will be referred to as a "+ type phase shift circuit" for explanation.

When the phase shift circuits are classified into two types for convenience, the oscillator 1 of the first embodiment and the oscillator 1a of the second embodiment are composed of two phase shift circuits of different types. Thus, the oscillation operation is performed at the frequency at which the phase shift amount as a whole becomes 0 °.

By the way, when attention is paid to the relationship between the entire input and output when a phase inverting circuit for inverting the phase of a signal is connected to the subsequent stage of one − type phase shift circuit 10C (or 10L), (3) In the equation, the sign "-" of the fraction may be inverted to "+", and the configuration in which the phase inversion circuit is connected to the subsequent stage of one-type phase shift circuit 10C is equivalent to one + type phase shift circuit. You can say that. Similarly, one + type phase shift circuit
Focusing on the relationship between the entire input and output when a phase inversion circuit that inverts the phase of the signal is connected in the subsequent stage of 30 L (or 30 C), the sign "+" of the fraction is inverted in Eq. It may be set to "-", and it can be said that the configuration in which the phase inversion circuit is connected to the subsequent stage of one + type phase shift circuit is equivalent to one-type phase shift circuit.

Therefore, instead of combining two phase shift circuits of different types in the first embodiment to form an oscillator, two phase shift circuits of the same type and a phase inversion circuit can be combined to form an oscillator. .

FIG. 19 is a diagram showing the structure of the oscillator of the third embodiment. The oscillator 1b shown in the figure includes two − type phase shift circuits 10C and 10L shown in FIG. 2 or FIG. 12, a phase inverting circuit 80 for further inverting the phase of the output signal of the subsequent phase shift circuit 10L, and a phase A feedback resistor 70 for feeding back the output of the inverting circuit 80 to the input side of the preceding phase shift circuit 10C is included.

The phase inversion circuit 80 includes a FET 82 in which a resistor 84 is connected between the drain and the positive power source and a resistor 86 is connected between the source and the negative power source. FET
When an AC signal is input to the gate of 82, the drain of the FET 82 outputs a reverse phase signal with the phase reversed. Further, the phase inverting circuit 80 has a predetermined amplification degree determined by the resistance ratio of the two resistors 84 and 86.

By using the phase inverting circuit 80 having such a configuration, it becomes easy to invert the phase of the input signal and adjust the amplification degree to set the loop gain of the oscillator 1b to 1 or more.

By the way, the above-mentioned first embodiment and second embodiment
As described in the embodiment, the two-type phase shift circuits 10C,
Each of the 10L has a phase shift amount of 180 ° to 0 ° as the frequency ω of the input signal changes from 0 to ∞.
Change. For example, assuming that the time constant of the CR circuit in the phase shift circuit 10C is the same as the time constant of the LR circuit in the phase shift circuit 10L, and letting this be T, there are two The amount of phase shift in each of the phase shift circuits 10C and 10L becomes 90 °. Therefore, the two phase shift circuits 10
The phase is shifted by 180 ° by the whole of C and 10L, and the phase is inverted by the phase inversion circuit 80 connected to the latter stage, and the phase is completely looped and the phase shift amount is 0.
A signal of 0 is output from the phase inversion circuit 80. By feeding back the output of the phase inversion circuit 80 to the input side of the phase shift circuit 10 at the previous stage via the feedback resistor 70, sine wave oscillation having the frequency ω is performed.

The transfer function K21 of each of the two phase shift circuits 10C and 10L is (13) when both the time constant of the CR circuit in the phase shift circuit 10C and the time constant of the LR circuit in the phase shift circuit 10L are set to (13). Replace T ₁ with T in the formula,

[Equation 22] Becomes Therefore, these two phase shift circuits 10C and 10L
Is connected in series and the phase inversion circuit 80 is connected in the subsequent stage, the overall transfer function K11 is

[Equation 23] Becomes The right side of the equation (23) is (15) in the first embodiment.
It is equal to the transfer function K1 shown in the equation with T ₁ and T ₂ replaced by T. That is, the equation (23) is equal to the entire transfer function when the two phase shift circuits 10C and 30L and the non-inverting circuit 50 shown in the first embodiment are connected, and in this embodiment, the same type of transfer function is used. Two phase shift circuits 10C and 10L
It can be seen that the configuration in which the phase inversion circuit 80 is connected to the phase inversion circuit 80 is equivalent to the configuration shown in FIG. 1 in the first embodiment.

Therefore, in the oscillator 1b of the third embodiment, by setting the amplification factor of the phase inverting circuit 80 to an appropriate value and setting the loop gain to 1 or more, the phase shift amount becomes 0 ° when the circuit makes one cycle. The sine wave oscillation is sustained at such a frequency.

In addition, the variable resistance in each phase shift circuit 10C, 10L
Since the phase shift amount in each phase shift circuit can be changed by changing the resistance value R of 14, the total phase shift amount of the two phase shift circuits 10C and 10L is 18
The frequency of 0 ° can be changed, and the variable frequency oscillator 1b can be easily realized.

In addition, as in the first embodiment, etc.,
17 can be formed on a semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an inductor 17, other components (FET, resistor, or Since it can be formed on a semiconductor substrate together with a capacitor),
It is easy to form the entire oscillator 1b on a semiconductor substrate to form an integrated circuit.

The oscillator 1b of the third embodiment shown in FIG. 19 has two phase shift circuits 10C and 10L and a phase inversion circuit.
A capacitor for blocking a direct current is provided between each of 80, and a resistor for bias application is connected to the gate of the FET so that each circuit operates at an optimum operating point.
As shown in FIG. 20, the element constants of the respective elements may be adjusted so as to obtain an appropriate operating point in the state where the DC current blocking capacitor and the like are omitted.

Further, in the oscillator 1b of this embodiment, the phase shift circuit 10C is arranged in the front stage and the phase shift circuit 10L is arranged in the rear stage. Therefore, the oscillator may be configured by arranging the front and the rear of these and arranging the phase shift circuit 10L in the front stage and the phase shift circuit 10C in the rear stage, respectively.

(Fourth Embodiment) In the oscillator 1b of the third embodiment described above, the case where two − type phase shift circuits are connected has been described. However, by connecting two + type phase shift circuits, May be configured.

FIG. 21 is a diagram showing the structure of the oscillator of the fourth embodiment. The oscillator 1c shown in the figure is composed of two + type phase shift circuits 30L and 30C shown in FIG. 5 or FIG. 15, a phase inversion circuit 80 which further inverts the phase of the output signal of the subsequent phase shift circuit 30C, and a phase The output of the inverting circuit 80 is applied to the phase shift circuit 30
A feedback resistor 70 for feeding back to the input side of L is included.

The phase inversion circuit 80 is the same as that shown in FIG. 19 in the third embodiment. When an AC signal is input to the gate of the FET 82, a reverse phase signal of which the phase is inverted is output from the drain of the FET 82. Is output.

As described in the first and second embodiments described above, each of the two + type phase shift circuits 30L and 30C has a phase as the frequency ω of the input signal changes from 0 to ∞. The shift amount changes from 0 ° to 180 °.
For example, the time constant of the LR circuit in the phase shift circuit 30L and the phase shift circuit
Assuming that the time constants of the CR circuits in 30C are the same, and letting that value be T, the phase shift amount in each of the two phase shift circuits 30L and 30C is 90 ° at the frequency of ω = 1 / T.
Becomes Therefore, the phase is shifted by 180 ° by the whole of the two phase shift circuits 30L and 30C, and the phase is inverted by the phase inverting circuit 80 connected in the subsequent stage. As a whole, the phase makes one round and the phase shift amount is 0 °. The signal that becomes is output from the phase inversion circuit 80. The output of the phase inversion circuit 80 is fed back to the input side of the phase shift circuit 30L at the previous stage via the feedback resistor 70, so that sine wave oscillation having the frequency ω is performed.

Transfer function K31 of the two phase shift circuits 30L and 30C
Is the time constant of the LR circuit in the phase shift circuit 30L and the phase shift circuit 30C.
Assuming that the time constant of the CR circuit inside is T, replace T ₂ with T in equation (14),

[Equation 24] Becomes This transfer function K31 is the phase shift circuit 10 shown in the equation (22).
The sign "-" of the transfer function K21 of C and 10L is replaced with "+", and the whole of the case where two phase shift circuits 30L and 30C are connected in cascade and further the phase inversion circuit 80 is connected to the subsequent stage. The transfer function K12 of

(Equation 25) Therefore, it becomes the same as the transfer function K11 shown in the equation (23) in the third embodiment.

That is, the configuration in which two phase shift circuits 30L and 30C of the same type and the phase inversion circuit 80 are connected in this embodiment is two phase shift circuits of different types in the first and second embodiments. And a non-inverting circuit 50 are connected to each other, or two negative-type phase shift circuits 10C in the third embodiment,
It can be said that it is equivalent to the configuration in which 10 L and the phase inversion circuit 80 are connected.

Therefore, in the oscillator 1c of the fourth embodiment, by setting the amplification factor of the phase inverting circuit 80 to an appropriate value and setting the loop gain to 1 or more, the phase shift amount becomes 0 ° when the circuit makes one cycle. The sine wave oscillation is sustained at such a frequency.

The variable resistor 34 in the phase shift circuits 30L and 30C is also used.
Since the phase shift amount in each phase shift circuit can be changed by changing the resistance value R of, the total phase shift amount is 180 by the total of the two phase shift circuits 30L and 30C.
It is possible to change the frequency at which the angle becomes 0, and it is possible to easily realize the variable frequency oscillator 1c.

Further, as in the first embodiment, etc.,
The 37 can be formed on the semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an inductor 37, other components (FET, resistor, or Since it can be formed on a semiconductor substrate together with a capacitor),
It is easy to form the entire oscillator 1c on a semiconductor substrate to form an integrated circuit.

The oscillator 1c of the fourth embodiment shown in FIG. 21 has two phase shift circuits 30L and 30C and a phase inversion circuit.
A capacitor for blocking a direct current is provided between each of 80, and a resistor for bias application is connected to the gate of the FET so that each circuit operates at an optimum operating point.
As shown in FIG. 22, the element constants of the respective elements may be adjusted so that an appropriate operating point is obtained in the state where the DC current blocking capacitors and the like are omitted.

Further, in the oscillator 1c of this embodiment, the phase shift circuit 30L is arranged in the front stage and the phase shift circuit 30C is arranged in the rear stage. Therefore, the oscillator may be configured by arranging the front and the rear of these and arranging the phase shift circuit 30C in the front stage and the phase shift circuit 30L in the rear stage.

(Other Embodiments) By the way, the oscillator of each of the above-mentioned embodiments is composed of two phase shift circuits and a non-inversion circuit or two phase shift circuits and a phase inversion circuit, and three connected circuits. A predetermined oscillation operation is performed by setting the total amount of phase shift to 0 ° at a predetermined frequency by the whole circuit. Therefore, focusing only on the amount of phase shift, there is some degree of freedom in the order in which the three circuits are connected, and the connection order can be determined as necessary.

FIG. 23 is a diagram showing a connection state when an oscillator is formed by combining two phase shift circuits and a non-inverting circuit. In these figures, the feedback impedance element 70a most commonly uses a feedback resistor 70 as shown in FIG. However, the feedback impedance element 70a may be formed by a capacitor or an inductor, or may be formed by combining a resistor, a capacitor or an inductor.

FIG. 23A shows a configuration in which a non-inverting circuit 50 is arranged in the latter stage of two phase shift circuits, and corresponds to the oscillator 1 shown in FIG. 1 or the oscillator 1a shown in FIG. ing. As described above, when the non-inverting circuit 50 is arranged in the subsequent stage, a large output current can be taken out by giving the non-inverting circuit 50 a function of an output buffer.

FIG. 23B shows two phase shift circuits 10C and 30L.
The configuration in which the non-inverting circuit 50 is arranged between the two phase shift circuits 10L and 30C is shown. In this way, when the non-inverting circuit 50 is arranged in the middle, mutual interference between the phase shift circuit at the front stage and the phase shift circuit at the rear stage can be completely prevented.

FIG. 23C shows two phase shift circuits 10C and 30L.
The configuration is shown in which the non-inverting circuit 50 is arranged in the preceding stage or in the preceding stage of the two phase shift circuits 10L and 30C. As described above, when the non-inverting circuit 50 is arranged in the preceding stage, the influence of the feedback impedance element 70a on the preceding phase shift circuit can be minimized.

Similarly, FIG. 24 is a diagram showing a connection state when an oscillator is formed by combining two phase shift circuits and a phase inversion circuit. As described with reference to FIG. 23, the feedback impedance element 70a is
Most commonly, a feedback resistor 70 is used. However, the feedback impedance element 70a may be formed by a capacitor or an inductor, or may be formed by combining a resistor, a capacitor or an inductor.

FIG. 24 (A) shows a configuration in which a phase inverting circuit 80 is arranged after two phase shift circuits, and corresponds to the oscillator 1b shown in FIG. 19 or the oscillator 1c shown in FIG. ing. As described above, when the phase inverting circuit 80 is arranged in the subsequent stage, a large output current can be taken out by giving the phase inverting circuit 80 a function as an output buffer.

FIG. 24B shows two phase shift circuits 10C and 10L.
A configuration in which the phase inversion circuit 80 is arranged between the two phase shift circuits 30L and 30C is shown. in this way,
When the phase inversion circuit 80 is arranged in the middle, mutual interference between the two phase shift circuits can be completely prevented.

FIG. 24C shows two phase shift circuits 10C and 10L.
The configuration is shown in which the phase inversion circuit 80 is arranged in the preceding stage or in the preceding stage of the two phase shift circuits 30L and 30C. As described above, when the phase inversion circuit 80 is arranged in the preceding stage, the influence of the feedback impedance element 70a on the preceding phase shift circuit can be minimized.

The phase shift circuit shown in each of the above-described embodiments includes the variable resistor 14 or 34. These variable resistors 14 and 34 are specifically junction type or MO type.
It can be realized by using an S-type FET.

In FIG. 25, the variable resistance 14 or 34 in the two types of phase shift circuits 10C or 30C having a CR circuit is FE.
It is a figure which shows the structure of the phase shift circuit when it replaces with T.
In the same figure (A), the variable resistor 14 is FE in the phase shift circuit 10C.
The configuration replaced with T is shown. FIG. 2B shows a configuration in which the variable resistor 34 is replaced with an FET in the phase shift circuit 30C.

Similarly, FIG. 26 shows a variable resistor 14 or 34 in two types of phase shift circuits 10L or 30L having an LR circuit.
It is a figure which shows the structure of the phase shift circuit when replacing with FET. In the same figure (A), in the phase shift circuit 10L, the variable resistor 14
A configuration in which is replaced with an FET is shown. FIG. 1B shows a configuration in which the variable resistor 34 is replaced with an FET in the phase shift circuit 30L.

As described above, the channel formed between the source and drain of the FET is used as a resistor to make the variable resistance variable.
When used in place of 14 or 34, the gate voltage can be variably controlled to arbitrarily change the channel resistance within a certain range to change the amount of phase shift in each phase shift circuit. Therefore, in each oscillator, the frequency at which the amount of phase shift of the signal that goes around once becomes 0 ° can be changed, so that the oscillation frequency of the oscillator can be arbitrarily changed.

In each of the phase shift circuits shown in FIG. 25 or 26, the variable resistor is composed of one FET, that is, a p-channel or n-channel FET.
The channel FET and the n-channel FET may be connected in parallel to form one variable resistor, and gate voltages of equal magnitude but different polarities may be applied between the gate of each FET and the substrate. When changing the resistance value, the magnitude of the gate voltage may be changed. in this way,
By constructing a variable resistance by combining two FETs, it is possible to improve the non-linear region of the FETs, so that the distortion of the oscillation output can be reduced.

In the phase shift circuit 10C or 30C shown in each of the above-mentioned embodiments, the resistance value of the variable resistor 14 or 34 connected in series with the capacitor 16 or 36 is changed to change the phase shift amount. Although the overall oscillation frequency is changed by means of, the capacitors 16, 36 may be formed of variable capacitance elements, and the overall oscillation frequency may be changed by changing the capacitance thereof.

FIG. 27 is a diagram showing the structure of the phase shift circuit in the case where the capacitor 16 or 36 in the phase shift circuit 10C or 30C shown in each embodiment is replaced with a variable capacitance diode. FIG. 1A shows the phase shift circuit 10 shown in FIG.
In C, a configuration is shown in which the variable resistor 14 is replaced with a fixed resistor and the capacitor 16 is replaced with a variable capacitance diode. FIG. 11B shows a configuration in which the variable resistor 34 is replaced with a fixed resistor and the capacitor 36 is replaced with a variable capacitance diode in the phase shift circuit 30C shown in FIG.

27 (A) and 27 (B), the capacitor connected in series to the variable capacitance diode blocks its direct current when a reverse bias voltage is applied between the anode and the cathode of the variable capacitance diode. The impedance is extremely small at the operating frequency, that is, it has a large capacitance. In addition, since the potentials at both ends of the capacitor shown in FIGS. 27A and 27B are constant when the DC component is seen, by applying a reverse bias voltage larger than the amplitude of the AC component between the anode and the cathode, Each variable capacitance diode can function as a variable capacitance capacitor.

As described above, the capacitor 16 or 36 is composed of a variable capacitance diode, and the magnitude of the reverse bias voltage applied between its anode and cathode is variably controlled to make the capacitance of this variable capacitance diode within a certain range. The amount of phase shift in each phase shift circuit can be changed by changing the value arbitrarily. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency of the oscillator.

By the way, although the variable capacitance diode is used as the variable capacitance element in FIGS. 27A and 27B described above, the FET in which the source and the drain are connected to a fixed potential in the direct current and the variable voltage is applied to the gate May be used. As described above, the potentials at both ends of the variable capacitance diodes shown in FIGS. 27A and 27B are fixed in terms of direct current.
It is only necessary to replace it with T, and the gate capacitance, that is, the electrostatic capacitance of the FET can be changed by changing the voltage applied to the gate.

Further, in FIGS. 27A and 27B described above, only the capacitance of the variable capacitance diode is changed, but the resistance value of the variable resistor 14 or 34 may be changed at the same time. 27C shows a configuration in which the variable resistor 14 is used and the capacitor 16 is replaced with a variable capacitance diode in the phase shift circuit 10C shown in FIG. 1 and the like. Same figure
11D shows a configuration in which the variable resistor 34 is used and the capacitor 36 is replaced with a variable capacitance diode in the phase shift circuit 30C shown in FIG. 11 and the like. It goes without saying that the variable capacitance diode may be replaced with an FET having a variable gate capacitance.

It goes without saying that the variable resistance shown in FIGS. 27C and 27D can be formed by utilizing the channel resistance of the FET as shown in FIG. In particular,
When a p-channel FET and an n-channel FET are connected in parallel to form one variable resistor and gate voltages of equal magnitude and different polarities are applied between the base and substrate of each FET, Since the nonlinear region can be improved, distortion of the oscillation signal can be reduced.

As described above, even when the variable resistance and the variable capacitance element are combined to form the phase shift circuit, the resistance value of the variable resistance and the capacitance of the variable capacitance element can be arbitrarily changed within a certain range. The amount of phase shift in each phase shift circuit can be changed. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency of the oscillator.

Similarly, the phase shift circuit 10L or 30L shown in each of the above-described embodiments is the inductor 17 or 37.
The overall oscillation frequency was changed by changing the resistance value of the variable resistors 14 or 34 connected in series with the variable resistor 14 and 34, but the inductors 17 and 37 were formed by variable inductors and their inductance It is also possible to change the whole oscillation frequency by changing.

FIG. 28 is a diagram showing the structure of the phase shift circuit when the inductor 17 or 37 in the phase shift circuit 10L or 30L shown in each embodiment is replaced with a variable inductor.

FIG. 11A shows the phase shift circuit shown in FIG.
In 10L, a configuration is shown in which the variable resistor 14 is replaced with a fixed resistor and the inductor 17 is replaced with a variable inductor 17a. FIG. 1B shows a configuration in which the variable resistor 34 is replaced with a fixed resistor and the inductor 37 is replaced with a variable inductor 37a in the phase shift circuit 30L shown in FIG.

As described above, the inductor 17 or 37 can be replaced by the variable inductor 17a or 37a, and the inductance of the variable inductor 17a or 37a can be arbitrarily changed within a certain range to change the amount of phase shift in each phase shift circuit.
Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency.

By the way, in FIGS. 28A and 28B described above, only the inductance of the variable inductor 17a or 37a is changed, but the resistance value of the variable resistor 14 or 34 may be changed at the same time. FIG. 28C shows a configuration in which the variable resistor 14 is used and the inductor 17 is replaced with a variable inductor 17a in the phase shift circuit 10L shown in FIG. 11 and the like. FIG. 2D shows a configuration in which the variable resistor 34 is used and the inductor 37 is replaced with a variable inductor 37a in the phase shift circuit 30L shown in FIG.

It goes without saying that the variable resistance shown in FIGS. 28C and 28D can be formed by utilizing the channel resistance of the FET as shown in FIG. In particular,
When a p-channel FET and an n-channel FET are connected in parallel to form one variable resistor and gate voltages of equal magnitude and different polarities are applied between the base and substrate of each FET, Since the nonlinear region can be improved, distortion of the oscillation signal can be reduced.

As described above, even when the variable resistance and the variable inductor are combined to form the phase shift circuit, the resistance value of the variable resistor and the inductance of the variable inductor are arbitrarily changed within a certain range. The amount of phase shift at can be changed. Therefore, it is possible to change the frequency at which the amount of phase shift of the signal that goes round in each oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency.

In addition to the case where the variable resistance, the variable capacitance element or the variable inductor is used as described above, a plurality of resistors, capacitors or inductors having different element constants are prepared and the switch is switched.
One or a plurality of these elements may be selected. In this case, the element constants can be discontinuously switched by the number of elements to be connected and the connection method (serial connection, parallel connection, or a combination thereof) by switching the switches.

For example, instead of the variable resistor, the resistance value is R,
By preparing a plurality of 2n-th power series resistors such as 2R, 4R, ... And selecting one or an arbitrary plurality of resistors and connecting them in series, it is possible to reduce the switching of resistance values at even intervals. Can be easily realized with. Similarly,
In place of the capacitors, a plurality of n-th power series capacitors having capacitances of C, 2C, 4C, ... Are prepared, and one or arbitrary plural capacitors are selected and connected in parallel. Switching of the electrostatic capacitance of the interval can be easily realized with a smaller number of elements.

FIG. 29 shows the variable inductor shown in FIG.
It is a figure which shows the specific example of 17a, and the outline of the planar structure formed on the semiconductor substrate is shown. The structure of the variable inductor 17a shown in FIG.
It can also be applied to a.

The variable inductor 17a shown in the figure is a spiral inductor conductor 112 formed on a semiconductor substrate 110.
And a control conductor 11 formed so as to circulate the outer periphery thereof.
4 and an insulating magnetic body 118 formed so as to cover both the inductor conductor 112 and the control conductor 114.

The control conductor 114 described above is the control conductor 114.
A variable voltage power supply 116 is connected to both ends of the variable voltage power supply 116 to change the bias current flowing through the control conductor 114 by variably controlling the DC bias voltage applied by the variable voltage power supply 116. be able to.

As the semiconductor substrate 110, for example, an n-type silicon substrate (n-Si substrate) or another semiconductor material (for example, an amorphous material such as germanium or amorphous silicon) is used. The inductor conductor 112 is formed by spirally forming a metal thin film such as aluminum or gold or a semiconductor material such as polysilicon.

The semiconductor substrate 110 shown in FIG. 29 is provided with other components of the oscillator shown in FIG. 11 and the like in addition to the variable inductor 17a.

FIG. 30 shows the variable inductor shown in FIG.
It is a figure which shows the shape of the inductor conductor 112 and the control conductor 114 of 17a in more detail.

As shown in the figure, the inductor conductor 112 located on the inner peripheral side has a predetermined number of turns (for example, about 4 turns).
Is formed in a spiral shape, and two terminal electrodes 122 and 124 are connected to both ends thereof. Similarly, the control conductor 114 located on the outer peripheral side is formed in a spiral shape with a predetermined number of turns (for example, about 2 turns), and the control conductor 114 has two ends at both ends.
Two control electrodes 126 and 128 are connected.

FIG. 31 is an enlarged sectional view taken along the line AA of FIG. 30, showing a cross section of the insulating magnetic body 118 including the inductor conductor 112 and the control conductor 114.

As shown in the figure, the inductor conductor 112 and the control conductor 114 are formed on the surface of the semiconductor substrate 110 via the insulating magnetic film 118a, and the insulating magnetic film 118b is further formed on the surface thereof. Is coated. The insulating magnetic material 118 shown in FIG. 29 is formed by these two magnetic material films 118a and 118b.

For example, as the magnetic films 118a and 118b,
Various magnetic films such as gamma-ferrite and barium-ferrite can be used. Various kinds of materials and forming methods of these magnetic films can be considered. For example, a method of forming a magnetic film by vacuum vapor deposition of FeO or the like, other molecular beam epitaxy method (MBE method), chemical vapor deposition, etc. There is a method of forming a magnetic film by using a phase growth method (CVD method), a sputtering method or the like.

The insulating film 130 is made of a non-magnetic material, and covers the winding portions of the inductor conductor 112 and the control conductor 114. By eliminating the magnetic films 118a and 118b between the winding portions in this way, the leakage magnetic flux generated between the winding portions can be minimized, so that the magnetic flux generated by the inductor conductor 112 can be effectively used. As a result, the variable inductor 17a having a large inductance can be realized.

As described above, in the variable inductor 17a shown in FIG. 29 and the like, the insulating magnetic material 118 (magnetic material films 118a and 118b) is formed so as to cover the inductor conductor 112 and the control conductor 114, By controlling the DC bias current flowing through the control conductor 114 variably, the above-mentioned insulating magnetic material is used.
The saturation magnetization characteristic of the inductor conductor 112 having the magnetic path 118 changes, and the inductance of the inductor conductor 112 changes.

Therefore, the inductance itself of the inductor conductor 112 can be directly changed, and the inductor conductor 112 can be formed on the semiconductor substrate 110 by using a thin film forming technique or a semiconductor manufacturing technique, which facilitates the production.
Further, since it is possible to form other components such as the oscillator 1 on the semiconductor substrate 110, it is suitable when the whole oscillator of each embodiment is integrally formed by integration.

The variable inductor 17 shown in FIG.
As shown in FIG. 32 or FIG. 33, a may be formed by alternately winding the inductor conductor 112 and the control conductor 114, or may be formed by stacking the inductor conductor 112 and the control conductor 114. In either case, the control conductor 11
The saturation magnetization characteristic of the insulating magnetic body 118 can be changed by changing the DC bias current flowing through the inductor 4, and the inductance of the inductor conductor 112 can be changed within a certain range.

Further, the variable inductor 17 shown in FIG.
Although a has been described by taking the case where the inductor conductor 112 and the like are formed on the semiconductor substrate 110 as an example, it may be formed on various insulating or conductive substrates such as ceramics.

Further, although the insulating material is used for the magnetic films 118a and 118b, a conductive material such as metal powder (MP) may be used. However, if such a conductive magnetic film is used by replacing it with the above-mentioned insulating magnetic film 118a or the like, each winding portion of the inductor conductor 112 or the like is short-circuited and does not function as an inductor conductor.
It is necessary to electrically insulate each inductor conductor from the conductive magnetic film. As this insulating method, a method of forming an insulating oxide film by oxidizing the inductor conductor 112 or the like,
There is a method of forming a silicon oxide film or a nitride film by a chemical vapor deposition method or the like.

In particular, a conductive material such as metal powder has a large magnetic permeability as compared with an insulating material such as gamma-ferrite, and therefore has an advantage that a large inductance can be secured.

Further, the variable inductor 17 shown in FIG.
In the case of a, the whole of both the inductor conductor 112 and the control conductor 114 is covered with the insulating magnetic material 118, but only part of them may be covered to form the magnetic path.

FIG. 34 is a diagram showing a variable inductor in which the insulating magnetic material 118 is partially formed. As shown in the figure, the insulating magnetic material 118 is used as the inductor conductor 112 and the control conductor.
It is formed so as to cover a part of 114, and a magnetic path is formed by this partially formed insulating magnetic body 118. In this way, when the insulating magnetic body (or the conductive magnetic body may be used) 118 that serves as a magnetic path is partially formed, the magnetic flux is generated by the inductor conductor 112 and the control conductor 114 due to the narrowed magnetic path. It becomes easy to saturate. Therefore, even when a small bias current is passed through the control conductor 114, the magnetic flux is saturated, and the inductance of the inductor conductor 112 can be changed by variably controlling the small bias current. Therefore, the structure of the control system can be simplified.

The variable inductor 17 shown in FIG.
The conductor a is formed by concentrically winding the inductor conductor 112 and the control conductor 114. These conductors are formed at adjacent positions on the surface of the semiconductor substrate 110, and an insulating or conductive magnetic material is formed between them. You may magnetically couple by the magnetic path formed of the body.

FIG. 35 shows a variable inductor in which an inductor conductor and a control conductor are formed adjacent to each other.
It is a top view which shows the outline of 17b.

The variable inductor 17b shown in the figure is a spiral inductor conductor 112 formed on a semiconductor substrate 110.
a, a spiral-shaped control conductor 114a formed at a position adjacent to the inductor conductor 112a, and an insulating magnetic body (or conductive material) formed so as to cover each spiral center of the inductor conductor 112a and the control conductor 114a. Magnetic material) 119
It is configured to include and.

Similar to the variable inductor 17a shown in FIG. 29, a variable voltage power supply 116 is connected to the control conductor 114a for applying a variable bias voltage across the control conductor 114a. By variably controlling the applied bias voltage, it is possible to change a predetermined bias current flowing through the control conductor 114a.

FIG. 36 shows the variable inductor shown in FIG.
It is the figure which showed in more detail the shape of the inductor conductor 112a and the control conductor 114a of 17b.

As shown in the figure, the inductor conductor 112a
Is formed in a spiral shape with a predetermined number of turns (for example, about 4 turns), and two terminal electrodes 122 and 124 are provided at both ends thereof.
Is connected. Similarly, the control conductor 114a arranged adjacent to the inductor conductor 112a is formed in a spiral shape with a predetermined number of turns (for example, about 2 turns),
Two control electrodes 126 and 128 are connected to both ends thereof.

FIG. 37 is an enlarged sectional view taken along line BB of FIG. 36, and shows a cross section of the insulating magnetic body 119 including the inductor conductor 112a and the control conductor 114a.

As shown in the figure, an insulating magnetic film 119a and an insulating non-magnetic film 132 are formed on the surface of the semiconductor substrate 110, and the inductor conductor 112a and the control conductor 114a are respectively formed on the surface. Has been formed. Then, an insulating magnetic film 119 is further formed on the surface of the inductor conductor 112a and the control conductor 114a so as to penetrate the central portions thereof.
b is formed by coating. These two magnetic films 119
inductor conductor 112a and control conductor 11 by a and 119b.
An annular magnetic body 119 is formed which serves as a common magnetic path for 4a.

The insulating nonmagnetic film shown in FIG.
Reference numeral 132 has a thickness substantially the same as that of the magnetic film 119a, and is for forming the inductor conductor 112a and the control conductor 114a at substantially the same height on their surfaces. Therefore, if a slight step may occur in the inductor conductor 112a and the control conductor 114a, one of the inductor conductor 112a and the control conductor 114a may be directly formed on the semiconductor substrate 110 without forming the nonmagnetic film 132. You may make it form a part.

In addition, between the inductor conductor 112a and the control conductor 114a on the surface of the magnetic film 119a,
Similar to the variable inductor 17a shown in FIG.
0 is formed. By partially filling the insulating film 130 and excluding the magnetic films 119a and 119b between the winding portions in this manner, the leakage flux generated between the winding portions can be minimized. Most of the magnetic flux generated by 112a is magnetic film 119a, 119a.
It comes to intersect with the control conductor 114a through b. Therefore, by reducing the leakage magnetic flux, a large inductance can be obtained by effectively utilizing the magnetic flux generated by the inductor conductor 112a.

As described above, the variable inductor 17b described above is used.
Is an annular insulating magnetic material 119 (magnetic material film 119) so as to pass through the spiral centers of the inductor conductor 112a and the control conductor 114a.
a, 119b) are formed. Therefore, by variably controlling the DC bias current flowing through the control conductor 114a, the saturation magnetization characteristic of the inductor conductor 112a having the magnetic body 119 as a magnetic path changes, and the inductor conductor 112a
The inductance of the element also changes.

Further, when the oscillator 1 of each of the above-described embodiments is formed on a semiconductor substrate, it is not possible to set a very large capacitance as the capacitor 16 or 36 in the phase shift circuit 10C, 30C. Therefore, if the capacitance can be increased apparently by devising a circuit of small capacitance of the capacitor actually formed on the semiconductor substrate, the time constant T can be set to a large value to reduce the oscillation frequency. It is convenient for.

FIG. 38 shows the phase shift circuit 10C shown in FIG.
It is a figure which shows the modification which comprised the capacitor 16 or 36 used for 30C not by a single element but by a circuit, and as an electrostatic capacity conversion circuit which makes the electrostatic capacity of the capacitor actually formed on a semiconductor substrate look large. Function. The entire circuit shown in FIG. 38 is the phase shift circuit 10C or 30.
It corresponds to the capacitor 16 or 36 included in C.

The capacitance conversion circuit 16a shown in FIG. 38 includes a capacitor 210 having a predetermined capacitance C0, two operational amplifiers 212 and 214, and four resistors 216, 218, 220 and 222. Has been done.

In the operational amplifier 212 in the first stage, a resistor 218 (whose resistance value is R18) is connected between the output terminal and the inverting input terminal, and the inverting input terminal is a resistor.
It is grounded through 216 (this resistance is R16).

Between the voltage E1 applied to the non-inverting input terminal of the first stage operational amplifier 212 and the voltage E2 appearing at the output terminal,

(Equation 26) There is a relationship. The first-stage operational amplifier 212 mainly functions as a buffer that performs impedance conversion, and the gain may be 1. R18 when the gain is 1
When / R16 = 0, that is, R16 is set to infinity (removing the resistor 216), or R18 is set to 0Ω (direct connection).

Further, the operational amplifier 214 of the second stage has a resistor 222 (this resistance value is set to R22 between the output terminal and the inverting input terminal).
And a resistor 220 (whose resistance value is R20) is connected between the inverting input terminal and the output terminal of the operational amplifier 212 described above, and the non-inverting input terminal is grounded. There is.

When the voltage appearing at the output terminal of the second stage operational amplifier 214 is E3, the voltage E3 between this voltage E3 and the voltage E2 appearing at the output terminal of the first stage operational amplifier 212 is:

[Equation 27] There is a relationship. In this way, the second-stage operational amplifier 214 functions as an inverting amplifier, and the first-stage operational amplifier 212 is set in order to set its input side to high impedance.
Is used.

Further, the non-inverting input terminal of the first-stage operational amplifier 212 and the second-stage operational amplifier 2 which are connected as described above.
As described above, the capacitor 210 having a predetermined electrostatic capacity is connected between the 14 output terminals.

In the capacitance conversion circuit 16a shown in FIG. 38, assuming that the transfer function of the entire circuit except the capacitor 210 is K4, the capacitance conversion circuit 16a can be represented by the system diagram shown in FIG. FIG. 40 is a system diagram in which this is converted by the Miller's theorem.

When the impedance Z1 shown in FIG. 40 is expressed using the impedance Z0 shown in FIG. 39,

[Equation 28] Becomes Here, the capacitance conversion circuit 16a shown in FIG.
In the case of, the impedance Z0 = 1 / (jωC0), and by substituting this into the equation (28),

[Equation 29]

[Equation 30] Becomes In this equation (30), the capacitance C0 of the capacitor 210 in the capacitance conversion circuit 16a is apparently (1-
K4) shows that it has doubled.

Therefore, when the gain K4 is negative, (1-K4) is always larger than 1, so that the electrostatic capacitance C0 can be changed to the larger one.

By the way, the gain of the amplifier in the capacitance conversion circuit 16a shown in FIG. 38, that is, the operational amplifier 212.
The gain K4 of the amplifier formed by the whole of
From equation and (27),

[Equation 31] Becomes Substituting equation (31) into equation (30),

[Equation 32] Becomes Therefore, by setting the resistance value of the four resistors 216, 218, 220, 222 to a predetermined value, the two terminals 22
The apparent capacitance C between 4 and 226 can be increased.

When the gain of the amplifier by the first stage operational amplifier 212 is 1, that is, when R16 is infinite (resistor 216 is removed) or R18 is set to 0Ω as described above, R18 / R16 When = 0, the above (3
Equation 2 is simplified to

[Expression 33] Becomes

FIG. 41 is a diagram showing the structure of the capacitance conversion circuit 16b from which the resistor 216 connected to the inverting input terminal of the first operational amplifier 212 shown in FIG. 38 is removed. In this case, since the electrostatic capacitance C appearing between the terminals 224 and 226 is expressed by the equation (33), C0 can be changed to the larger one by changing the ratio of R22 and R20.

As described above, the capacitance conversion circuit 16 described above
a or 16b is a resistance ratio of the resistance 220 and the resistance 222 R22 /
By changing R20 or the resistance ratio R18 / R16 of the resistor 216 and the resistor 218, the electrostatic capacitance C0 of the capacitor 210 actually formed on the semiconductor substrate can be converted to an apparently larger one. Therefore, in the case where the entire oscillator 1 shown in FIG. 1 and the like is formed on a semiconductor substrate, a capacitor 210 having a small capacitance C0 is formed on the semiconductor substrate, and the capacitor 210 shown in FIG. The circuit shown at 41 allows conversion into a large capacitance C, which is convenient for integration.

Further, at least one of the resistors 216, 218, 220, 222 (at least one of the resistors 220, 222 in the case of the capacitance conversion circuit 16b shown in FIG. 41) is formed by a variable resistor. Therefore, specifically, the junction type or MOS type F
By connecting the ET or p-channel FET and the n-channel FET in parallel to form a variable resistance, it is possible to easily form a capacitor having a variable capacitance.
Therefore, by using this capacitor instead of the variable capacitance diode shown in FIG. 27, the phase shift amount can be arbitrarily changed within a certain range. Therefore, the phase shift amount of the signal that makes one round in the oscillator is 0 °.
Can be changed, and the oscillation frequency of the oscillator of each embodiment can be arbitrarily changed.

Since the first stage operational amplifier 212 is used as a buffer for increasing the input impedance as described above, the operational amplifier 212 may be replaced with an emitter follower circuit or a source follower circuit.

FIG. 42 is a diagram showing the configuration of the electrostatic capacitance conversion circuit 16c using the emitter follower circuit in the first stage. The capacitance conversion circuit 16c shown in the figure has an emitter follower circuit 22 including a first-stage operational amplifier 212 and two resistors 216 and 218 shown in FIG.
It has a configuration replaced with 8.

FIG. 43 is a diagram showing the configuration of the capacitance conversion circuit 16d using the source follower circuit in the first stage. The electrostatic capacitance conversion circuit 16d shown in the figure has a configuration in which the first-stage operational amplifier 212 and the two resistors 216 and 218 shown in FIG. 38 are replaced with a source follower circuit 230 including an FET and a resistor.

The capacitance conversion circuits 16c and 16 described above are also provided.
Each of d is a resistor 2 connected to the operational amplifier 214.
The point that the apparent capacitance C between the terminals 224 and 226 can be arbitrarily changed by changing the resistance ratio of the resistors 20 and 222 is the same as the capacitance conversion circuit 16a shown in FIG. 38 and the like. . Therefore, at least one of the resistors 220 and 222 is
By replacing the junction-type or MOS-type FET or the variable resistance in which the p-channel FET and the n-channel FET are connected in parallel, a capacitance variable capacitor can be constructed. By using it instead of the capacitance diode, the phase shift amount can be arbitrarily changed within a certain range. Therefore, in each oscillator, the phase shift amount of the signal that makes one round is 0
It is possible to change the frequency at which the angle becomes 0, and it is possible to arbitrarily change the oscillation frequency of the oscillator of each embodiment.

By the way, in FIGS. 38 to 43 described above,
The case where the apparent capacitance is made larger than the capacitance actually possessed by the capacitor element by combining the amplifier having the predetermined gain and the capacitor has been described, but an inductor is used instead of the capacitor, and this inductor is It is also possible to increase the apparent inductance.

That is, when the impedance Z0 shown in FIG. 39 is used to express the impedance Z1 shown in FIG. 40 as described above, the expression (28) is obtained. Here, in the case of the inductor having the inductance L0, the impedance Z0 = jωL0, which is substituted into the equation (28) to obtain

[Equation 34]

[Equation 35] Becomes This equation (35) shows that the inductance actually possessed by the inductor element has become 1 / (1-K4) times, and apparently when the gain K4 is set between 0 and 1. It can be seen that the inductance of is increased.

FIG. 44 shows the phase shift circuit 10 shown in FIG.
It is a figure which shows the modification which comprised the inductor 17 or 37 used for L and 30L not by a single element but by a circuit, and the inductance of an inductor element (inductor conductor) actually formed on a semiconductor substrate which makes an inductance look large. Functions as a conversion circuit. The entire circuit shown in FIG. 44 corresponds to the inductor 17 or 37 included in the phase shift circuit 10L, 30L.

Inductance conversion circuit 17c shown in FIG.
Is an inductor 260 having a predetermined inductance L0
And two operational amplifiers 262 and 264 and two resistors 266 and 268
It is configured to include and.

The operational amplifier 262 in the first stage is a non-inverting amplifier with a gain of 1 whose output terminal is connected to the inverting input terminal, and mainly functions as a buffer for impedance conversion. Similarly, the output terminal of the second-stage operational amplifier 264 is connected to the inverting input terminal, and functions as a non-inverting amplifier having a gain of 1. Further, a voltage dividing circuit by resistors 266 and 268 is inserted between these two non-inverting amplifiers.

By thus inserting the voltage dividing circuit between them, the gain of the entire amplifier including the two non-inverting amplifiers can be freely set between 0 and 1.

The inductance conversion circuit 17 shown in FIG.
In c, when the transfer function of the entire circuit (amplifier) excluding the inductor 260 is K4, this gain K4 is expressed by resistors 266 and 268.
Determined by the voltage division ratio of the voltage dividing circuit
If the respective resistance values are R66 and R68,

[Equation 36] Becomes Substituting this gain K4 into equation (35) and calculating the apparent inductance L,

(37) Becomes Therefore, the resistance ratio of resistors 266 and 268 is R68 / R66.
By increasing, the apparent inductance L between the two terminals 254 and 256 can be increased. For example, when R68 = R66, the inductance L can be doubled from L0 from the equation (37).

As described above, the above-described inductance conversion circuit 17c changes the voltage division ratio of the voltage dividing circuit inserted between the two non-inverting amplifiers to make the inductance L0 of the inductor 260 actually connected to appear. Can be made bigger. Therefore, when the entire oscillator 1 shown in FIG. 1 and the like is formed on a semiconductor substrate, an inductor 260 having a small inductance L0 is formed on the semiconductor substrate by a spiral conductor or the like. The inductance conversion circuit shown in FIG. 44 can convert to a large inductance L, which is convenient for integration. In particular, if a large inductance can be secured in this way, it becomes easy to reduce the oscillation frequency of the oscillator 1 shown in FIG. 1 to a relatively low frequency range. In addition, by integrating,
It is possible to reduce the mounting area of the entire oscillator and reduce the material cost.

Incidentally, in addition to the case where the voltage dividing ratio of the voltage dividing circuit by the resistors 266 and 268 is fixed, at least one of these two resistors 266 and 268 is formed by a variable resistor. Type FET or p-channel FET and n-channel FET are connected in parallel to form a variable resistance, and this voltage division ratio may be continuously changed. In this case, the operational amplifier 26 shown in FIG.
The gain of the entire amplifier including 2,264 changes,
The inductance L between the terminals 254 and 256 also changes continuously. Therefore, by using this inductance conversion circuit 17c instead of the variable inductor 17a shown in FIG. 28, the phase shift amount in each phase shift circuit can be arbitrarily changed within a certain range. Therefore, it is possible to change the frequency at which the phase shift amount of the signal that makes one round in the oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency of the oscillator described above.

Since the gain of the entire amplifier including the two operational amplifiers 262 and 264 is set to 1 or less in the inductance conversion circuit 17c shown in FIG. 44, the whole is replaced with the emitter follower circuit or the source follower circuit. Good.

FIG. 45 is a diagram showing the structure of an inductance conversion circuit in which the entire amplifier including the operational amplifiers 262 and 264 is replaced with an emitter follower circuit. The inductance conversion circuit 17d shown in FIG.
A bipolar transistor 278 to which 4 and 276 are connected, a voltage dividing point by these two resistors 274 and 276, and a transistor 278.
It is configured to include an inductor 260 connected to the base of the capacitor and a capacitor 280 for blocking a direct current.
Inductor 260 Capacitor 280 inserted on one end side
Has an extremely small impedance at the operating frequency, that is, a large capacitance so as not to affect the frequency characteristics.

The gain of the emitter follower circuit described above is determined mainly by the resistance ratio of the two resistors 274 and 276, and since the gain is always less than 1, as shown in the equation (35), the inductor is actually used. Inductance L0 of 260
It can be made larger in appearance. Moreover, since only one emitter follower circuit is used, the circuit configuration can be simplified and the maximum operating frequency can be set high.

FIG. 45B is a diagram showing a modification thereof,
The difference is that the two resistors 274 and 276 in FIG. 9A are replaced with a variable resistor 282. By using the variable resistor 282 in this way, the gain can be changed arbitrarily and continuously, so that the apparent inductance L can be changed arbitrarily and continuously, and the inductance conversion circuit 17e can be changed. The variable inductor 17 shown in FIG.
By using it instead of a, the phase shift amount in each phase shift circuit can be arbitrarily changed within a certain range. Therefore, it is possible to change the frequency at which the phase shift amount of the signal that makes one round in the oscillator becomes 0 °, and it is possible to arbitrarily change the oscillation frequency of the oscillator described above.

In the inductance conversion circuit 17e shown in FIG. 45B, the two resistors 274 and 276 in FIG. 45A are replaced by one variable resistor 282.
At least one of 74 and 276 may be configured by a variable resistor.

FIG. 46 is a circuit in which each of the inductance conversion circuits 17d and 17e shown in FIGS. 45A and 45B is realized by a source follower circuit, and the bipolar transistor 278 is replaced with an FET 284. FIG. 46 (A) corresponds to FIG. 45 (A), and FIG. 46 (B) corresponds to FIG. 45 (B).

FIG. 47 is a diagram showing a modification of the inductance conversion circuit 17c shown in FIG. 44, in which the inductance conversion circuit 17f does not use a DC current blocking capacitor.
The configuration of is shown. The inductance conversion circuit 17f shown in FIG. 47 is an npn-type bipolar transistor 286.
And a resistor 290 connected to its emitter, a pnp bipolar transistor 288 and a resistor 292 connected to its emitter, and an inductor having an inductance L0.
It consists of 260 and.

The one transistor 286 and the resistor 290 described above
Form a first emitter follower circuit, and the other transistor 288 and the resistor 292 form a second emitter follower circuit, which are connected in cascade. Moreover,
npn-type transistor 286 and pnp-type transistor 2
Since the 88 is used, the base potential of the transistor 286 at one end of the inductor 260 and the emitter potential of the transistor 288 can be set to be substantially the same, and the DC current blocking capacitor 280 is not required.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

For example, the oscillator 1 or the like of the above-described embodiment includes two phase shift circuits, but when the oscillation frequency is variable, the CR circuit or the LR circuit included in both phase shift circuits is used. In addition to the case of changing at least one element constant of the resistance and the capacitor or the inductor which configures, the case of changing at least one element constant of the resistor, the capacitor and the inductor which configure the CR circuit or the LR circuit included in one phase shift circuit, Conceivable. Alternatively, the variable resistors 14, 34, etc. in each phase shift circuit shown in FIG. 1 and the like may be replaced with resistors having a fixed resistance value to form an oscillator having a fixed oscillation frequency.

Further, in the above-mentioned FIG. 1 and the like, the case where the junction type FET 12 or FET 32 is used to form the phase shift circuit 10 or the like is shown, but the phase shift circuit is formed by a MOS type FET or a bipolar transistor. It may be configured.

In a phase shift circuit in which the FET is replaced with a bipolar transistor, a current flows between the base and the emitter when an input signal is input to the base, so that the voltage appearing at the emitter (AC voltage) and the voltage appearing at the collector (AC voltage) ( AC voltage) is not exactly the same. However, when the current amplification factor is several tens to one hundred times, the difference is 1% to several%, which can be practically ignored.
Alternatively, this difference may be corrected by setting the collector resistance slightly larger than the emitter resistance.

In particular, when the phase shift circuit is composed of bipolar transistors, the upper limit of the operating frequency can be increased and the potential difference between the base and the emitter is F.
Since it is smaller than the potential difference between the gate and source of ET, it is possible to reduce the attenuation of the signal amplitude input to and output from the phase shift circuit. Therefore, it is preferable to configure at least the first-stage phase shift circuit using bipolar transistors. However, since the second-stage phase shift circuit needs to have a high input impedance, it is preferable to use FETs.

In addition, the oscillator of the above-described embodiment is constructed from one of the two phase shift circuits and the non-inverting circuit 50 constituting the oscillator, or one of the two phase shift circuits and the phase inverting circuit 80. I tried to extract the sine wave signal from the two circuits,
The sine wave signal may be taken out from two or all of the three circuits. In particular, when the time constants of the two phase shift circuits forming the oscillator are set to be the same, the phase shift amount in each phase shift circuit becomes 90 °, so two-phase outputs whose phases are shifted by 90 ° are generated. You can take it out. Also, two-phase outputs whose phases are mutually inverted can be taken out from the phase inversion circuit 80 and the phase shift circuit in the preceding stage.

[0229]

As is clear from the description based on each of the above embodiments, when the oscillation frequency is high, each element constituting the oscillator of the present invention can be formed by the integrated circuit manufacturing method. The oscillator can be miniaturized as an integrated circuit on a semiconductor wafer, and can be manufactured inexpensively by mass production. Further, the inductance of the inductor in each phase shift circuit can be converted to a larger one by using the inductance conversion circuit or the capacitance of the capacitor by using the capacitance conversion circuit, and the oscillation frequency can be lowered. .

In particular, the channel between the source and drain of the FET is used as the variable resistance of the CR circuit or the LR circuit in each phase shift circuit, and the control voltage applied to the gate of this FET is changed to change the resistance of the channel. With this configuration, it is possible to avoid the influence of the inductance and the capacitance of the wiring that applies the control voltage, and it is possible to obtain an oscillator having ideal characteristics almost as designed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an oscillator according to a first embodiment of the invention,

FIG. 2 is a diagram showing an extracted configuration of a phase shift circuit in the preceding stage shown in FIG.

FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit and the voltage appearing at a capacitor or the like;

FIG. 4 is an equivalent view of the phase shift circuit shown in FIG.

FIG. 5 is a diagram showing an extracted configuration of a phase shift circuit at a subsequent stage shown in FIG.

FIG. 6 is a vector diagram showing the relationship between the input / output voltage of a subsequent phase shift circuit and the voltage appearing in an inductor or the like;

7 is an equivalent view of the phase shift circuit shown in FIG.

FIG. 8 is a system diagram in which the entire two phase shift circuits and the non-inverting circuit are replaced with a circuit having a transfer function K1;

FIG. 9 is a system diagram obtained by converting the system shown in FIG. 8 according to Miller's theorem,

FIG. 10 is a diagram showing a modification of the oscillator of the first embodiment,

FIG. 11 is a circuit diagram showing a configuration of an oscillator according to a second embodiment of the invention.

FIG. 12 is a diagram showing an extracted configuration of the phase shift circuit at the preceding stage shown in FIG.

FIG. 13 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit and the voltage appearing in the inductor or the like;

14 is a diagram equivalently showing the phase shift circuit shown in FIG. 12,

FIG. 15 is a diagram showing an extracted configuration of a phase shift circuit at a subsequent stage shown in FIG.

FIG. 16 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit and the voltage appearing at a capacitor or the like;

FIG. 17 is an equivalent view of the phase shift circuit shown in FIG.

FIG. 18 is a diagram showing a modification of the oscillator of the second embodiment,

FIG. 19 is a circuit diagram showing a configuration of an oscillator according to a third embodiment,

FIG. 20 is a diagram showing a modification of the oscillator of the third embodiment,

FIG. 21 is a circuit diagram showing a configuration of an oscillator according to a fourth embodiment,

FIG. 22 is a diagram showing a modification of the oscillator of the fourth embodiment;

FIG. 23 is a diagram showing a connection form of a phase shift circuit and a non-inverting circuit;

FIG. 24 is a diagram showing a connection form of a phase shift circuit and a phase inversion circuit;

FIG. 25 is a diagram showing a configuration of a phase shift circuit in which a variable resistance of the phase shift circuit is replaced with an FET,

FIG. 26 is a diagram showing a configuration of a phase shift circuit in which a variable resistance of the phase shift circuit is replaced with an FET,

FIG. 27 is a diagram showing a configuration of a phase shift circuit in which a capacitor of the phase shift circuit is replaced with a variable capacitance diode;

FIG. 28 is a diagram showing a configuration of a phase shift circuit in which the inductor of the phase shift circuit is replaced with a variable inductor;

FIG. 29 is a diagram showing an example of a variable inductor,

30 is a diagram showing in more detail the shapes of the inductor conductor and the control conductor of the variable inductor shown in FIG. 29;

31 is an enlarged cross-sectional view taken along the line AA of FIG. 30,

32 is a diagram showing a modification of the variable inductor shown in FIG. 29,

33 is a diagram showing a modification of the variable inductor shown in FIG. 29,

34 is a diagram showing a modification of the variable inductor shown in FIG. 29,

FIG. 35 is a view showing another example of the variable inductor,

36 is a diagram showing in more detail the shapes of the inductor conductor and the control conductor of the variable inductor shown in FIG. 35;

37 is an enlarged sectional view taken along line BB of FIG. 36,

FIG. 38 is a diagram showing a configuration of a capacitance conversion circuit that apparently increases the capacitance actually possessed by a capacitor;

39 is a diagram showing the circuit shown in FIG. 38 using a transfer function,

FIG. 40 is a diagram obtained by converting the configuration shown in FIG. 39 according to Miller's theorem,

41 is a diagram showing a configuration of a capacitance conversion circuit obtained by simplifying the circuit of FIG. 38;

FIG. 42 is a diagram showing a configuration of a capacitance conversion circuit using an emitter follower circuit in the first stage,

FIG. 43 is a diagram showing a configuration of a capacitance conversion circuit using a source follower circuit in the first stage,

FIG. 44 is a diagram showing the configuration of an inductance conversion circuit that apparently increases the inductance that the inductor actually has;

45 is a diagram showing the configuration of an inductance conversion circuit in which the entire amplifier including the two operational amplifiers included in FIG. 44 is replaced with an emitter follower circuit;

46 is a diagram showing a configuration in which the circuit of FIG. 45 is realized by a source follower circuit,

FIG. 47 is a view showing a modified example of the inductance conversion circuit,

FIG. 48 is a circuit diagram showing an example of a conventional sine wave oscillator,

FIG. 49 is a circuit diagram showing an example of a conventional sine wave oscillator.

[Explanation of symbols]

 1 Oscillator 10C, 30L Phase shift circuit 12, 32 Field effect transistor (FET) 14, 34 Variable resistor 16, 39 Capacitor 37 Inductor 18, 20, 38, 40 Resistor 50 Non-inverting circuit 70 Feedback resistor 92 Output terminal

Claims (26)

[Claims] 1. A conversion means for converting an input AC signal into an AC signal of the same phase and an opposite phase and outputting the AC signal, and one AC signal converted by the conversion means passes through a capacitor and the other AC signal is a resistance. A first phase-shifting circuit including a synthesizing means for synthesizing via an input means, a converting means for converting an input AC signal into an in-phase and an anti-phase alternating-current signal and outputting the AC signal, and one of the conversion means converted by the converting means. A second phase shift circuit including a synthesizing means for synthesizing the alternating current signal via the inductor and the other alternating current signal via the resistor, and amplifying the alternating current signal with a predetermined amplification degree without changing the phase of the input alternating current signal. A non-inverting circuit for outputting, and each of the first and second phase shift circuits and the non-inverting circuit are cascaded, and the output of the final stage of the plurality of cascaded circuits is While returning to the input side , An oscillator characterized by taking out a sine wave oscillation output from any one of these plurality of circuits. 2. The conversion means included in the phase shift circuit according to claim 1, wherein the source and the drain, or the emitter and the collector are respectively connected to resistors having substantially equal resistance values, and a gate or It is composed of a transistor to which an input signal is input to the base, and a series circuit composed of the reactance element composed of the capacitor or the inductor and the resistance is connected between the source / drain or the emitter / collector of the transistor. An oscillator characterized in that the reactance element and the resistor are connected in opposite manners in the first and second phase shift circuits. 3. The method according to claim 1 or 2, wherein the first and second phase shift circuits and the non-inverting circuit are 2
An oscillator characterized by taking out phase output. 4. A conversion means for converting an input AC signal into an in-phase and an opposite-phase AC signal and outputting the AC signal, and one AC signal converted by the conversion means and a resistance of the other AC signal via a capacitor. A first phase-shifting circuit including a synthesizing means for synthesizing via an input means, a converting means for converting an input AC signal into an in-phase and an anti-phase alternating-current signal and outputting the AC signal, and one of the conversion means converted by the converting means. A second phase shift circuit including a synthesizing means for synthesizing the alternating current signal via the inductor and the other alternating current signal via the resistor, and inverting the phase of the input alternating current signal and amplifying it with a predetermined amplification degree. And a phase inversion circuit for outputting, wherein each of the first and second phase shift circuits and the phase inversion circuit is connected in cascade, and the output of the final stage in the plurality of circuits connected in cascade is Returned to the input side An oscillator characterized by taking out a sine wave oscillation output from any one of these circuits. 5. The conversion means included in the phase shift circuit according to claim 4, wherein the source and the drain are respectively connected to the source and the drain and the emitter and the collector are respectively connected with resistors having substantially the same resistance value, and the gate or the It is composed of a transistor to which an input signal is input to the base, and a series circuit composed of the reactance element composed of the capacitor or the inductor and the resistance is connected between the source / drain or the emitter / collector of the transistor. An oscillator characterized in that the reactance element and the resistor are connected in the same manner in the first and second phase shift circuits. 6. The oscillator according to claim 4, wherein two-phase outputs are taken out from the first and second phase shift circuits and the phase inversion circuit. 7. The oscillation frequency according to claim 1, wherein the resistance of the combining means included in at least one of the two phase shift circuits is formed by a variable resistance, and the resistance value is changed. Oscillator characterized by changing. 8. The oscillator according to claim 7, wherein the variable resistance is formed by a channel of an FET, and a channel voltage is changed by changing a gate voltage. 9. The channel according to claim 7, wherein the variable resistor is formed by connecting a p-channel type FET and an n-channel type FET in parallel, and changing the magnitude of the gate voltage of each FET having a different polarity. An oscillator characterized by changing resistance. 10. The oscillation according to claim 1, wherein the capacitor included in the synthesizing means of one of the two phase shift circuits is formed of a variable capacitance element, and the capacitance is changed. An oscillator characterized by changing the frequency. 11. The oscillator according to claim 10, wherein the variable capacitance element is formed of a variable capacitance diode whose reverse bias voltage can be changed or an FET whose gate capacitance can be changed by changing the gate voltage. 12. The oscillating frequency according to claim 1, wherein the oscillation frequency is changed by changing an inductance of the inductor included in the combining means of one of the two phase shift circuits. Oscillator. 13. The inductor of the synthesizing means according to claim 12, wherein the inductor conductor is formed on the substrate in a substantially planar spiral shape, and is formed on the substrate in a substantially concentric shape with the inductor conductor. And a control conductor through which a predetermined DC bias current flows, and a magnetic body formed so as to cover the inductor conductor and the control conductor, and change the DC bias current flowing through the control conductor. An oscillator characterized by changing the inductance appearing at both ends of the inductor conductor. 14. The inductor of the synthesizing means according to claim 12, wherein the inductor conductor is formed in a spiral shape in a substantially planar shape on a substrate, and is substantially planar at a position on the substrate adjacent to the inductor conductor. A control conductor, which is formed in a spiral shape and in which a predetermined DC bias current flows, and a magnetic body formed in an annular shape so as to penetrate through the spiral centers of the inductor conductor and the control conductor, An oscillator comprising: a DC bias current flowing through the control conductor to change an inductance appearing at both ends of the inductor conductor. 15. The resistor according to claim 1, wherein the synthesizing means included in at least one of the two phase shift circuits has a plurality of resistors having a fixed resistance value. An oscillator characterized in that the oscillation frequency is changed by selectively connecting. 16. The capacitor according to claim 1, wherein the capacitors included in the synthesizing means of one of the two phase shift circuits have a plurality of capacitors having a fixed limiting capacity, and are switched by a switch. An oscillator characterized in that the oscillation frequency is changed by selectively connecting. 17. The inductor according to claim 1, wherein the inductor included in the synthesizing means of one of the two phase shift circuits has a plurality of inductors of fixed inductance, and is selected by switching a switch. An oscillator characterized in that the oscillation frequency is changed by electrically connecting the oscillators. 18. The capacitor according to claim 1, wherein a capacitor included in the combining means of one of the two phase shift circuits is provided between an amplifier having a negative gain and an input / output of the amplifier. An oscillator characterized in that the capacitance viewed from the input side of the amplifier is made larger than the capacitance actually possessed by the capacitor element by replacing with a capacitor element connected in parallel. 19. The oscillator according to claim 18, wherein the oscillation frequency is changed by changing the gain of the amplifier to change the electrostatic capacitance viewed from the input side of the amplifier. 20. The amplifier according to claim 1, wherein an inductor included in the combining means of one of the two phase shift circuits has a gain set between 0 and 1.
An oscillator characterized in that by replacing with an inductor element connected in parallel between the input and output of the amplifier, the inductance seen from the input side of the amplifier is made larger than the actual inductance of the inductor element. 21. The oscillator according to claim 20, wherein the oscillation frequency is changed by changing the gain of the amplifier to change the inductance viewed from the input side of the amplifier. 22. A first reactance comprising a conversion means for converting an input AC signal into an AC signal of the same phase and an opposite phase and outputting the AC signal, and the converted two AC signals of either a capacitor or an inductor. A first-stage phase shift circuit including an element and a means for synthesizing and shifting a phase via a first resistor, and a conversion means for converting an input AC signal into an in-phase and an anti-phase AC signal and outputting the AC signal. And the converted two AC signals are combined with a second reactance element composed of the other one of a capacitor and an inductor via a second resistor, and a direction opposite to that of the phase shift circuit of the first stage is obtained. And a non-inverting circuit that outputs the output of the phase shifting circuit of the second stage in the same phase, and the output of the non-inverting circuit of the first stage. Return to the input of the eye phase shift circuit An oscillator, comprising: 23. A first reactance comprising a conversion means for converting an input AC signal into an AC signal of the same phase and an opposite phase and outputting the AC signal; A first-stage phase shift circuit including an element and a means for synthesizing and shifting a phase via a first resistor, and a conversion means for converting an input AC signal into an in-phase and an anti-phase AC signal and outputting the AC signal. And the converted two AC signals are combined with the second reactance element composed of the other one of the capacitor and the inductor via the second resistor, and are combined in the same direction as the phase shift circuit of the first stage. A second-stage phase-shift circuit that shifts the phase; a phase-inverting circuit that inverts the phase of the output of the second-stage phase-shift circuit; and an output of the phase-inverting circuit that shifts the output of the first-stage phase-shift circuit. A circuit that returns to the input of Oscillator, characterized in that it comprises. 24. The oscillation frequency is changed by changing the first resistance of the phase shift circuit of the first stage and / or the second resistance of the phase shift circuit of the second stage according to claim 22 or 23. An oscillator characterized by: 25. The resistance of each of the first and second stage phase shift circuits according to claim 22 or 23,
An oscillator formed by T channels. 26. The oscillator according to claim 1, which is formed as a semiconductor integrated circuit.