JP3628389B2 - Tuning amplifier - Google Patents

Description

で表すことができる。
【００６５】
ところで、前段の移相回路１０Ｃの伝達関数Ｋ２ は、可変抵抗１６の抵抗値をＲ、キャパシタ１４の静電容量をＣ、これら可変抵抗１６とキャパシタ１４からなるＣＲ回路の時定数をＴ_１ とすると、
【数２】

となる。ここで、ｋは入出力信号の減衰比であり、１以下の値となる。
【００６６】
また、後段の移相回路１１０Ｃの伝達関数Ｋ３ は、可変抵抗１１６の抵抗値をＲ、キャパシタ１１４の静電容量をＣ、これら可変抵抗１１６とキャパシタ１１４からなるＣＲ回路の時定数をＴ_２ とすると、
【数３】

となる。したがって、移相回路１０Ｃ、１１０Ｃと利得（−１／ｋ）の位相反転回路８０を接続した場合の全体の伝達関数Ｋ１ は、
【数４】

となる。なお、計算を簡単なものとするために、各移相回路の時定数Ｔ_１ 、Ｔ_２ をともにＴとした。この（４）式を上述した（１）式に代入すると、
【数５】

となる。
【００６７】
この（５）式によれば、ω＝０（直流の領域）のときにＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。また、ω＝∞のときにも最大減衰量を与えることがわかる。さらに、ω＝１／Ｔの同調点（各移相回路の時定数が異なる場合には、ω＝１／√（Ｔ_１ ・Ｔ_２ ）の同調点）においてはＡ＝１であって帰還抵抗７０と入力抵抗７４の抵抗比ｎに無関係であることがわかる。換言すれば、図８に示すように、ｎの値を変化させても同調点がずれることなく、かつ同調点の減衰量も変化しない。
【００６８】
このように、この実施形態の同調増幅器１によれば、帰還抵抗７０と入力抵抗７４の抵抗比ｎを変えても同調周波数および同調時の利得が一定であり、最大減衰量のみを変化させることができる。反対に、最大減衰量は上述した抵抗比ｎによって決定されるため、各移相回路１０Ｃ、１１０Ｃ内の可変抵抗１６あるいは１１６の抵抗値を変えて同調周波数を変えた場合であっても、この最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【００６９】
また、第１の実施形態の同調増幅器１は、ＦＥＴやオペアンプあるいはキャパシタや抵抗を組み合わせて構成しており、どの構成素子も半導体基板上に形成することができることから、同調周波数および最大減衰量を調整し得る同調増幅器１の全体を半導体基板上に形成して集積回路とすることも容易である。
【００７０】
ところで、上述した第１の実施形態の同調増幅器では、２つの移相回路１０Ｃ、１１０Ｃのそれぞれをキャパシタ１４あるいは１１４を含んで構成したが、キャパシタの代わりにインダクタを用いることもできる。
【００７１】
図９は、前段の移相回路１０Ｃの変形例を示す図であり、ＦＥＴのソース・ドレイン間にＬＲ回路を接続した移相回路１０Ｌの構成が示されている。同図に示す移相回路１０Ｌは、図２に示した移相回路１０Ｃ内の可変抵抗１６とキャパシタ１４からなるＣＲ回路を、インダクタ１７と可変抵抗１６からなるＬＲ回路に置き換えた構成を有している。図９に示すように、可変抵抗１６の一方端がＦＥＴ１２のソースに接続されているとともに、インダクタ１７の一方端が直流電流阻止用のキャパシタ１９を介してＦＥＴ１２のドレインに接続されている。
【００７２】
したがって、ＦＥＴ１２のソースおよびドレインに現れる電圧のそれぞれを可変抵抗１６あるいはインダクタ１７を介して合成した信号が出力端２４から出力される。
【００７３】
図１０は、移相回路１０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【００７４】
移相回路１０Ｃについて説明したように、ＦＥＴ１２のソースとドレインにはそれぞれ入力電圧と同相および逆相であって電圧振幅がＥｉ の交流電圧が現れるため、ソース・ドレイン間の電位差（交流成分）は２Ｅｉ となる。また、インダクタ１７の両端に現れる電圧ＶＬ１と可変抵抗１６の両端に現れる電圧ＶＲ３とは互いに９０°位相がずれており、これらをベクトル的に合成（加算）したものが、ＦＥＴ１２のソース・ドレイン間の電位差２Ｅｉ に等しくなる。
【００７５】
したがって、図１０に示すように、電圧Ｅｉ の２倍を斜辺とし、インダクタ１７の両端電圧ＶＬ１と可変抵抗１６の両端電圧ＶＲ３とが直交する２辺を構成する直角三角形を形成することになる。このため、入力信号の振幅が一定で周波数のみが変化した場合には、図１０に示す半円の円周に沿ってインダクタ１７の両端電圧ＶＬ１と可変抵抗１６の両端電圧ＶＲ３とが変化する。
【００７６】
ところで、インダクタ１７と可変抵抗１６の接続点とアースとの電位差を出力電圧Ｅｏ として取り出すものとすると、この出力電圧Ｅｏ は、図１０に示した半円においてその中心点を始点とし、電圧ＶＬ１と電圧ＶＲ３とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ に等しくなる。しかも、入力信号の周波数が変化しても、このベクトルの終点は円周上を移動するだけであるため、周波数に応じて出力振幅が変化しない安定した出力を得ることができる。
【００７７】
また、図１０から明らかなように、電圧ＶＬ１と電圧ＶＲ３とは円周上で直角に交わるため、理論的にはＦＥＴ１２のゲートに印加される入力電圧と電圧ＶＬ１との位相差は、周波数ωが０から∞まで変化するに従って９０°から０°まで変化する。そして、移相回路１０Ｌ全体の位相シフト量φ１ はその２倍であり、周波数に応じて１８０°から０°まで変化する。しかも、可変抵抗１６の抵抗値Ｒを可変することにより、位相シフト量φ１ を変化させることができる。
【００７８】
なお、移相回路１０Ｌの伝達関数は、可変抵抗１６の抵抗値をＲ、インダクタ１７のインダクタンスをＬ、これら可変抵抗１６とインダクタ１７からなるＬＲ回路の時定数をＴ_１ （＝Ｌ／Ｒ）とすると、上述した（２）式で表すことができる。すなわち、時定数を用いて表現すると、図２に示した移相回路１０Ｃと図９に示した移相回路１０Ｌとが等価であることがわかる。
【００７９】
したがって、図１において、前段の移相回路１０Ｃを図９に示す移相回路１０Ｌに置き換えて同調増幅器を構成することもでき、この場合であっても、最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【００８０】
特に、前段の移相回路１０Ｃを図９に示す移相回路１０Ｌに置き換えた場合には、前段の移相回路１０Ｌ内のＬＲ回路の時定数ＴはＬ／Ｒであり、後段の移相回路１１０Ｃ内のＣＲ回路の時定数ＴはＣＲであって、それぞれにおいて抵抗値Ｒが分母と分子に分かれるため、例えば半導体基板上に同調増幅器の全体を形成するとともに各可変抵抗をＦＥＴで形成したような場合には、各可変抵抗の抵抗値の温度変化に対する同調周波数の変動を抑制する、いわゆる温度補償が可能となる。この点については、後述する各種の同調増幅器をＣＲ回路を含む移相回路とＬＲ回路を含む移相回路とを組み合わせて構成する場合についても同様である。
【００８１】
図１１は、後段の移相回路１１０Ｃの変形例を示す図であり、オペアンプの入力側にＬＲ回路を接続した移相回路１１０Ｌの構成が示されている。同図に示す移相回路１１０Ｌは、図４に示した移相回路１１０Ｃ内の可変抵抗１１６とキャパシタ１１４からなるＣＲ回路を、インダクタ１１７と可変抵抗１１６からなるＬＲ回路に置き換えた構成を有している。図１１に示すように、可変抵抗１１６の一方端が入力端１２２に接続され、可変抵抗１１６とインダクタ１１７の接続点がオペアンプ１１２の非反転入力端子に接続されている。
【００８２】
図１２は、移相回路１１０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【００８３】
同図に示すように、インダクタ１１７の両端に現れる電圧ＶＬ２と可変抵抗１１６の両端に現れる電圧ＶＲ４とは互いに９０°位相がずれており、これらをベクトル的に加算したものが入力電圧Ｅｉ ′となる。したがって、入力信号の振幅が一定で周波数のみが変化した場合には、図１２に示す半円の円周に沿ってインダクタ１１７の両端電圧ＶＬ２と可変抵抗１１６の両端電圧ＶＲ４とが変化する。
【００８４】
また、上述したように電圧ＶＬ２から電圧ＶＲ４をベクトル的に減算したものが出力電圧Ｅｏ となる。非反転入力端子に印加される電圧ＶＬ２を基準に考えると、入力電圧Ｅｉ ′と出力電圧Ｅｏ とは電圧ＶＲ４を合成する方向が異なるだけでありその絶対値は等しくなる。したがって、入出力電圧の大きさと位相の関係は、入力電圧Ｅｉ ′および出力電圧Ｅｏ を斜辺とし、電圧ＶＲ４の２倍を底辺とする二等辺三角形で表すことができ、出力信号の振幅は周波数に関係なく入力信号の振幅と同じであって、位相シフト量は図１２に示すφ２ で表されることがわかる。
【００８５】
また、図１２から明らかなように、電圧ＶＬ２と電圧ＶＲ４とは円周上で直角に交わるため、理論的には入力電圧Ｅｉ ′と電圧ＶＬ２との位相差は、周波数ωが０から∞まで変化するに従って９０°から０°まで変化する。そして、移相回路１１０Ｌ全体のシフト量φ２ はその２倍であり、周波数に応じて１８０°から０°まで変化する。しかも、可変抵抗１１６の抵抗値Ｒを可変することにより、位相シフト量φ２ を変化させることができる。
【００８６】
なお、移相回路１１０Ｌの伝達関数は、可変抵抗１１６の抵抗値をＲ、インダクタ１１７のインダクタンスをＬ、これら可変抵抗１１６とインダクタ１１７からなるＬＲ回路の時定数をＴ_２ （＝Ｌ／Ｒ）とすると、上述した（３）式で表すことができる。すなわち、時定数を用いて表現すると、図４に示した移相回路１１０Ｃと図１１に示した移相回路１１０Ｌとが等価であることがわかる。
【００８７】
したがって、図１において、後段の移相回路１１０Ｃを図１１に示す移相回路１１０Ｌに置き換えて同調増幅器を構成することもでき、この場合であっても、最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【００８８】
なお、図１において、前段の移相回路１０Ｃを図９に示す移相回路１０Ｌに置き換えるとともに、後段の移相回路１１０Ｃを図１１に示す移相回路１１０Ｌに置き換えて同調増幅器を構成することもできる。特に、同調増幅器を構成する２つの移相回路をともにＬＲ回路を含むように構成すると、集積回路として同調増幅器を形成した場合に各移相回路に含まれるインダクタのインダクタンスを小さくして周波数ω（＝Ｒ／Ｌ）を高くすることが容易であり、同調周波数を高周波化するのに適している。
【００８９】
また、上述した各種の同調増幅器では、前段に移相回路１０Ｃあるいは１０Ｌを、後段に移相回路１１０Ｃあるいは１１０Ｌをそれぞれ配置したが、これらの全体によって入出力信号間の位相シフト量が１８０°となればよいことから、これらの前後を入れ換えて前段に移相回路１１０Ｃあるいは１１０Ｌを、後段に移相回路１０Ｃあるいは１０Ｌをそれぞれ配置して同調増幅器を構成するようにしてもよい。
【００９０】
（第２の実施形態）
図１３は、本発明を適用した第２の実施形態の同調増幅器の構成を示す回路図である。同図に示す同調増幅器２は、それぞれが入力信号の位相を所定量シフトさせることにより所定の周波数において合計で１８０°の位相シフトを行う２つの移相回路３０Ｃおよび１３０Ｃと、移相回路１３０Ｃの出力信号の位相を反転するとともに所定の増幅度で増幅して出力する位相反転回路８０と、帰還抵抗７０および入力抵抗７４（入力抵抗７４は帰還抵抗７０のｎ倍の抵抗値を有しているものとする）のそれぞれを介することにより位相反転回路８０から出力される信号（帰還信号）と入力端子９０に入力される信号（入力信号）とを所定の割合で加算する加算回路とを含んで構成されている。
【００９１】
図１４は、図１３に示した前段の移相回路３０Ｃの構成を抜き出して示したものである。同図に示す前段の移相回路３０Ｃは、ゲートがキャパシタ４８を介して入力端４２に接続されたＦＥＴ３２と、このＦＥＴ３２のソース・ドレイン間に直列に接続された可変抵抗３６およびキャパシタ３４と、ＦＥＴ３２のドレインと正電源との間に接続された抵抗３８と、ＦＥＴ３２のソースとアースとの間に接続された抵抗４０とを含んで構成されている。
【００９２】
ここで、上述したＦＥＴ３２のソースおよびドレインに接続された２つの抵抗４０、３８の抵抗値はほぼ等しく設定されており、入力端４２に印加される入力電圧の交流成分に着目すると、位相が一致した信号がＦＥＴ３２のソースから、位相が反転した信号がＦＥＴ３２のドレインからそれぞれ出力されるようになっている。
【００９３】
なお、ＦＥＴ３２のゲートと入力端４２との間に挿入されたキャパシタ４８は直流電流を阻止するためのものであり、そのインピーダンスは動作周波数において極めて小さく、すなわち大きな静電容量を有している。また、ＦＥＴ３２のゲートとアースとの間に接続された抵抗４６は、ＦＥＴ３２に適切なバイアス電圧を印加するためのものである。
【００９４】
このような構成を有する移相回路３０Ｃにおいて、所定の交流信号が入力端４２に入力されると、すなわちＦＥＴ３２のゲートに所定の交流電圧（入力電圧）が印加されると、ＦＥＴ３２のソースにはこの入力電圧と同相の交流電圧が現れ、反対にＦＥＴ３２のドレインにはこの入力電圧と逆相であってソースに現れる電圧と振幅が等しい交流電圧が現れる。このソースおよびドレインに現れる交流電圧の振幅をともにＥｉ とする。
【００９５】
このＦＥＴ３２のソース・ドレイン間にはキャパシタ３４と可変抵抗３６とにより構成される直列回路が接続されている。したがって、ＦＥＴ３２のソースおよびドレインに現れる電圧のそれぞれを可変抵抗３６あるいはキャパシタ３４を介して合成した信号が出力端４４から出力される。
【００９６】
図１５は、移相回路３０Ｃの入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【００９７】
ＦＥＴ３２のソースとドレインにはそれぞれ入力電圧と同相および逆相であって電圧振幅がＥｉ の交流電圧が現れるため、ソース・ドレイン間の電位差（交流成分）は２Ｅｉ となる。また、キャパシタ３４の両端に現れる電圧ＶＣ３と可変抵抗３６の両端に現れる電圧ＶＲ５とは互いに９０°位相がずれており、これらをベクトル的に合成（加算）したものが、ＦＥＴ３２のソース・ドレイン間の電位差２Ｅｉ に等しくなる。
【００９８】
したがって、図１５に示すように、電圧Ｅｉ の２倍を斜辺とし、キャパシタ３４の両端電圧ＶＣ３と可変抵抗３６の両端電圧ＶＲ５とが直交する２辺を構成する直角三角形を形成することになる。このため、入力信号の振幅が一定で周波数のみが変化した場合には、図１５に示す半円の円周に沿ってキャパシタ３４の両端電圧ＶＣ３と可変抵抗３６の両端電圧ＶＲ５とが変化する。
【００９９】
ところで、可変抵抗３６とキャパシタ３４の接続点とアースとの電位差を出力電圧Ｅｏ として取り出すものとすると、この出力電圧Ｅｏ は、図１５に示した半円においてその中心点を始点とし、電圧ＶＣ３と電圧ＶＲ５とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ に等しくなる。しかも、入力信号の周波数が変化しても、このベクトルの終点は円周上を移動するだけであるため、周波数に応じて出力振幅が変化しない安定した出力を得ることができる。
【０１００】
また、図１５から明らかなように、電圧ＶＣ３と電圧ＶＲ５とは円周上で直角に交わるため、理論的にはＦＥＴ３２のゲートに印加される入力電圧と電圧ＶＣ３との位相差は、周波数ωが０から∞まで変化するに従って０°から９０°まで変化する。そして、移相回路３０Ｃ全体の位相シフト量φ３ はその２倍であり、周波数に応じて０°から１８０°まで変化する。しかも、可変抵抗３６の抵抗値Ｒを可変することにより、位相シフト量φ３ を変化させることができる。
【０１０１】
図１６は、図１３に示した後段の移相回路１３０Ｃの構成を抜き出して示したものである。同図に示す後段の移相回路１３０Ｃは、差動入力増幅器の一種であるオペアンプ１３２と、入力端１４２に入力された信号の位相を所定量シフトさせてオペアンプ１３２の非反転入力端子に入力する可変抵抗１３６およびキャパシタ１３４と、入力端１４２とオペアンプ１３２の反転入力端子との間に挿入された抵抗１３８と、オペアンプ１３２の出力端１４４と反転入力端子との間に挿入された抵抗１４０とを含んで構成されている。
【０１０２】
このような構成を有する移相回路１３０Ｃにおいて、所定の交流信号が入力端１４２に入力されると、オペアンプ１３２の非反転入力端子には、キャパシタ１３４の両端に現れる電圧ＶＣ４が印加される。
【０１０３】
また、図１６に示したオペアンプ１３２の２入力（反転入力端子と非反転入力端子）間には電位差が生じないので、オペアンプ１３２の反転入力端子の電位と、可変抵抗１３６とキャパシタ１３４の接続点の電位とは等しくなる。したがって、抵抗１３８の両端には、可変抵抗１３６の両端に現れる電圧ＶＲ６と同じ電圧ＶＲ６が現れる。
【０１０４】
ここで、抵抗１３８と抵抗１４０の各抵抗値が等しい場合には、これら２つの抵抗１３８、１４０に同じ電流が流れるため、抵抗１４０の両端にも電圧ＶＲ６が現れる。しかも、これら２つの抵抗１３８、１４０の各両端に現れる電圧ＶＲ６はベクトル的に同方向を向いており、オペアンプ１３２の反転入力端子（電圧ＶＣ４）を基準にして考えると、抵抗１３８の両端電圧ＶＲ６をベクトル的に加算したものが入力電圧Ｅｉ ′に、抵抗１４０の両端電圧Ｒ６をベクトル的に減算したものが出力電圧Ｅｏ になる。
【０１０５】
図１７は、後段の移相回路１３０Ｃの入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【０１０６】
同図に示すように、キャパシタ１３４の両端に現れる電圧ＶＣ４と可変抵抗１３６の両端に現れる電圧ＶＲ６とは互いに９０°位相がずれており、これらをベクトル的に加算したものが入力電圧Ｅｉ ′となる。したがって、入力信号の振幅が一定で周波数のみが変化した場合には、図１７に示す半円の円周に沿ってキャパシタ１３４の両端電圧ＶＣ４と可変抵抗１３６の両端電圧ＶＲ６とが変化する。
【０１０７】
また、上述したように電圧ＶＣ４から電圧ＶＲ６をベクトル的に減算したものが出力電圧Ｅｏ となる。非反転入力端子に印加される電圧ＶＣ４を基準に考えると、入力電圧Ｅｉ ′と出力電圧Ｅｏ とは電圧ＶＲ６を合成する方向が異なるだけでありその絶対値は等しくなる。したがって、入出力電圧の大きさと位相の関係は、入力電圧Ｅｉ ′および出力電圧Ｅｏ を斜辺とし、電圧ＶＲ６の２倍を底辺とする二等辺角形で表すことができ、出力信号の振幅は周波数に関係なく入力信号の振幅と同じであって、位相シフト量は図１７に示すφ４ で表されることがわかる。
【０１０８】
また、図１７から明らかなように、電圧ＶＣ４と電圧ＶＲ６とは円周上で直角に交わるため、理論的には入力電圧Ｅｉ ′と電圧ＶＣ４との位相差は、周波数ωが０から∞まで変化するに従って０°から９０°まで変化する。そして、移相回路１３０Ｃ全体のシフト量φ４ はその２倍であり、周波数に応じて０°から１８０°まで変化する。しかも、可変抵抗１３６の抵抗値Ｒを可変することにより、位相シフト量φ４ を変化させることができる。
【０１０９】
このようにして、２つの移相回路３０Ｃ、１３０Ｃのそれぞれにおいて位相が所定量シフトされる。しかも、図１５および図１７に示すように、各移相回路３０Ｃ、１３０Ｃにおける入出力電圧の相対的な位相関係は同方向であって、所定の周波数において２つの移相回路３０Ｃ、１３０Ｃの全体により位相シフト量が１８０°となる信号が出力される。
【０１１０】
また、図１３に示した位相反転回路８０は図１に示したものであり、抵抗８４、８６の抵抗比によって決まる増幅度を有する増幅回路として機能するとともに、入力信号の位相を反転して出力する。
【０１１１】
この位相反転回路８０の出力は、出力端子９２から同調増幅器２の出力として取り出されるとともに、帰還抵抗７０を介して前段の移相回路３０Ｃの入力側に帰還されており、この帰還された信号と入力抵抗７４を介して入力される信号とが加算され、この加算された電圧が移相回路３０Ｃの入力端（図１４に示した入力端４２）に印加されている。
【０１１２】
また、上述した位相反転回路８０の増幅度を調整することにより、図１３に構成を示す同調増幅器２のループゲインをほぼ１に設定することができる。すなわち、実際には前段の移相回路３０Ｃを通すことにより信号振幅の減衰が生じた分を位相反転回路８０で補うことにより、ループゲインをほぼ１に設定することが可能となる。
【０１１３】
ところで、前段の移相回路３０Ｃの伝達関数Ｋ２１は、可変抵抗３６の抵抗値をＲ、キャパシタ３４の静電容量をＣ、これら可変抵抗３６とキャパシタ３４からなるＣＲ回路の時定数をＴ_１ とすると、
【数６】

となる。ここで、ｋは入出力信号の減衰比であり、１以下の値となる。
【０１１４】
また、後段の移相回路１３０Ｃの伝達関数Ｋ３１は、可変抵抗１３６の抵抗値をＲ、キャパシタ１３４の静電容量をＣ、これら可変抵抗１３６とキャパシタ１３４からなるＣＲ回路の時定数をＴ_２ とすると、
【数７】

となる。したがって、移相回路３０Ｃ、１３０Ｃと利得（−１／ｋ）の位相反転回路８０を接続した場合の全体の伝達関数Ｋ１１は、
【数８】

となって、第１の実施形態の同調増幅器１について計算した（４）式と同じとなる。すなわち、第２のの実施形態の同調増幅器２全体の伝達関数も（５）式に示したＡをそのまま適用することができる。
【０１１５】
したがって、ω＝０（直流の領域）のときにＡ＝−１／（２ｎ＋１）となって、最大減衰量を与えることがわかる。また、ω＝∞のときにも最大減衰量を与えることがわかる。さらに、ω＝１／Ｔの同調点（各移相回路の時定数が異なる場合には、ω＝１／√（Ｔ_１ ・Ｔ_２ ）の同調点）においてはＡ＝１であって帰還抵抗７０と入力抵抗７４の抵抗比ｎに無関係であることがわかる。換言すれば、図８に示すように、ｎの値を変化させても同調点がずれることなく、かつ同調点の減衰量も変化しない。
【０１１６】
このように、この実施形態の同調増幅器２によれば、帰還抵抗７０と入力抵抗７４の抵抗比ｎを変えても同調周波数および同調時の利得が一定であり、最大減衰量のみを変化させることができる。反対に、最大減衰量は上述した抵抗比ｎによって決定されるため、各移相回路３０Ｃ、１３０Ｃ内の可変抵抗３６あるいは１３６の抵抗値を変えて同調周波数を変えた場合であっても、この最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【０１１７】
また、第２の実施形態の同調増幅器２は、ＦＥＴやオペアンプあるいはキャパシタや抵抗を組み合わせて構成しており、どの構成素子も半導体基板上に形成することができることから、同調周波数および最大減衰量を調整し得る同調増幅器２の全体を半導体基板上に形成して集積回路とすることも容易である。
【０１１８】
ところで、上述した第２の実施形態の同調増幅器２では、２つの移相回路３０Ｃ、１３０Ｃのそれぞれをキャパシタ３４あるいは１３４を含んで構成したが、キャパシタの代わりにインダクタを用いることもできる。
【０１１９】
図１８は、前段の移相回路３０Ｃの変形例を示す図であり、ＦＥＴのソース・ドレイン間にＬＲ回路を接続した移相回路３０Ｌの構成が示されている。同図に示す移相回路３０Ｌは、図１４に示した移相回路３０Ｃ内のキャパシタ３４と可変抵抗３６からなるＣＲ回路を、可変抵抗３６とインダクタ３７からなるＬＲ回路に置き換えた構成を有している。図１８に示すように、インダクタ３７の一方端が直流阻止用のキャパシタ３９を介してＦＥＴ３２のソースに接続されているとともに、可変抵抗３６の一方端がＦＥＴ３２のドレインに接続されている。
【０１２０】
したがって、ＦＥＴ３２のソースおよびドレインに現れる電圧のそれぞれをインダクタ３７あるいは可変抵抗３６を介して合成した信号が出力端４４から出力される。
【０１２１】
図１９は、移相回路３０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【０１２２】
移相回路３０Ｃについて説明したように、ＦＥＴ３２のソースとドレインにはそれぞれ入力電圧と同相および逆相であって電圧振幅がＥｉ の交流電圧が現れるため、ソース・ドレイン間の電位差（交流成分）は２Ｅｉ となる。また、可変抵抗３６の両端に現れる電圧ＶＲ７とインダクタ３７の両端に現れる電圧ＶＬ３とは互いに９０°位相がずれており、これらをベクトル的に合成（加算）したものが、ＦＥＴ３２のソース・ドレイン間の電位差２Ｅｉ に等しくなる。
【０１２３】
したがって、図１９に示すように、電圧Ｅｉ の２倍を斜辺とし、可変抵抗３６の両端電圧ＶＲ７とインダクタ３７の両端電圧ＶＬ３とが直交する２辺を構成する直角三角形を形成することになる。このため、入力信号の振幅が一定で周波数のみが変化した場合には、図１９に示す半円の円周に沿って可変抵抗３６の両端電圧ＶＲ７とインダクタ３７の両端電圧ＶＬ３とが変化する。
【０１２４】
ところで、可変抵抗３６とインダクタ３７の接続点とアースとの電位差を出力電圧Ｅｏ として取り出すものとすると、この出力電圧Ｅｏ は、図１９に示した半円においてその中心点を始点とし、電圧ＶＲ７と電圧ＶＬ３とが交差する円周上の一点を終点とするベクトルで表すことができ、その大きさは半円の半径Ｅｉ に等しくなる。しかも、入力信号の周波数が変化しても、このベクトルの終点は円周上を移動するだけであるため、周波数に応じて出力振幅が変化しない安定した出力を得ることができる。
【０１２５】
また、図１９から明らかなように、電圧ＶＲ７と電圧ＶＬ３とは円周上で直角に交わるため、理論的にはＦＥＴ３２のゲートに印加される入力電圧と電圧ＶＲ７との位相差は、周波数ωが０から∞まで変化するに従って０°から９０°まで変化する。そして、移相回路３０Ｌ全体の位相シフト量φ３ はその２倍であり、周波数に応じて０°から１８０°まで変化する。しかも、可変抵抗３６の抵抗値Ｒを可変することにより、位相シフト量φ３ を変化させることができる。
【０１２６】
なお、移相回路３０Ｌの伝達関数は、可変抵抗３６の抵抗値をＲ、インダクタ３７のインダクタンスをＬ、これら可変抵抗３６とインダクタ３７からなるＬＲ回路の時定数をＴ_１ （＝Ｌ／Ｒ）とすると、上述した（６）式で表すことができる。すなわち、時定数を用いて表現すると、図１４に示した移相回路３０Ｃと図１８に示した移相回路３０Ｌとが等価であることがわかる。
【０１２７】
したがって、図１３において、前段の移相回路３０Ｃを図１８に示す移相回路３０Ｌに置き換えて同調増幅器を構成することもでき、この場合であっても、最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【０１２８】
図２０は、後段の移相回路１３０Ｃの変形例を示す図であり、オペアンプの入力側にＬＲ回路を接続した移相回路１３０Ｌの構成が示されている。同図に示す移相回路１３０Ｌは、図１６に示した移相回路１３０Ｃ内の可変抵抗１３６とキャパシタ１３４からなるＣＲ回路を、インダクタ１３７と可変抵抗１３６からなるＬＲ回路に置き換えた構成を有している。図２０に示すように、インダクタ１３７の一方端が入力端１４２に接続され、インダクタ１３７と可変抵抗１３６の接続点がオペアンプ１３２の非反転入力端子に接続されている。
【０１２９】
図２１は、移相回路１３０Ｌの入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【０１３０】
同図に示すように、可変抵抗１３６の両端に現れる電圧ＶＲ８とインダクタ１３７の両端に現れる電圧ＶＬ４とは互いに９０°位相がずれており、これらをベクトル的に加算したものが入力電圧Ｅｉ ′となる。したがって、入力信号の振幅が一定で周波数のみが変化した場合には、図２１に示す半円の円周に沿って可変抵抗１３６の両端電圧ＶＲ８とインダクタ１３７の両端電圧ＶＬ４とが変化する。
【０１３１】
また、上述したように電圧ＶＲ８から電圧ＶＬ４をベクトル的に減算したものが出力電圧Ｅｏ となる。非反転入力端子に印加される電圧ＶＲ８を基準に考えると、入力電圧Ｅｉ ′と出力電圧Ｅｏ とは電圧ＶＬ４を合成する方向が異なるだけでありその絶対値は等しくなる。したがって、入出力電圧の大きさと位相の関係は、入力電圧Ｅｉ ′および出力電圧Ｅｏ を斜辺とし、電圧ＶＬ４の２倍を底辺とする二等辺三角形で表すことができ、出力信号の振幅は周波数に関係なく入力信号の振幅と同じであって、位相シフト量は図２１に示すφ４ で表されることがわかる。
【０１３２】
また、図２１から明らかなように、電圧ＶＲ８と電圧ＶＬ４とは円周上で直角に交わるため、理論的には入力電圧Ｅｉ ′と電圧ＶＲ８との位相差は、周波数ωが０から∞まで変化するに従って０°から９０°まで変化する。そして、移相回路１３０Ｌ全体のシフト量φ４ はその２倍であり、周波数に応じて０°から１８０°まで変化する。しかも、可変抵抗１３６の抵抗値Ｒを可変することにより、位相シフト量φ４ を変化させることができる。
【０１３３】
なお、移相回路１３０Ｌの伝達関数は、可変抵抗１３６の抵抗値をＲ、インダクタ１３７のインダクタンスをＬ、これら可変抵抗１３６とインダクタ１３７からなるＬＲ回路の時定数をＴ３１（＝Ｌ／Ｒ）とすると、上述した（７）式で表すことができる。すなわち、時定数を用いて表現すると、図１６に示した移相回路１３０Ｃと図２０に示した移相回路１３０Ｌとが等価であることがわかる。
【０１３４】
したがって、図１３において、後段の移相回路１３０Ｃを図２０に示す移相回路１３０Ｌに置き換えて同調増幅器を構成することもでき、この場合であっても、最大減衰量に影響を与えることはなく、同調周波数、同調周波数における利得、最大減衰量を互いに干渉しあうことなく調整することができる。
【０１３５】
なお、図１３において、前段の移相回路３０Ｃを図１８に示す移相回路３０Ｌに置き換えるとともに、後段の移相回路１３０Ｃを図２０に示す移相回路１３０Ｌに置き換えて同調増幅器を構成することもできる。
【０１３６】
また、上述した各種の同調増幅器では、前段に移相回路３０Ｃあるいは３０Ｌを、後段に移相回路１３０Ｃあるいは１３０Ｌをそれぞれ配置したが、これらの全体によって入出力信号間の位相シフト量が１８０°となればよいことから、これらの前後を入れ換えて前段に移相回路１３０Ｃあるいは１３０Ｌを、後段に移相回路３０Ｃあるいは３０Ｌをそれぞれ配置して同調増幅器を構成するようにしてもよい。
【０１３７】
（その他の実施形態）
ところで、上述した各実施形態の同調増幅器は、２つの移相回路と位相反転回路によって構成されており、接続された３つの回路の全体によって所定の周波数において合計の位相シフト量を０°にすることにより所定の同調動作を行うようになっている。したがって、位相シフト量だけに着目すると、移相回路と位相反転回路をどのような順番で接続するかはある程度の自由度があり、必要に応じて接続順番を決めることができる。
【０１３８】
図２２は、２つの移相回路と位相反転回路を組み合わせて同調増幅器を構成した場合において、その接続状態を示す図である。なお、これらの図において、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａは、各同調増幅器の出力信号と入力信号とを所定の割合で加算するためのものであり、最も一般的には図１等に示すように、帰還側インピーダンス素子７０ａとして帰還抵抗７０を、入力側インピーダンス素子７４ａとして入力抵抗７４を使用する。
【０１３９】
但し、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａは、それぞれの素子に入力された信号の位相関係を変えることなく加算できればよいことから、帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａをともにキャパシタにより、あるいは帰還側インピーダンス素子７０ａおよび入力側インピーダンス素子７４ａをともにインダクタにより形成するようにしてもよい。または、抵抗やキャパシタあるいはインダクタを組み合わせることにより、インピーダンスの実数分および虚数分の比を同時に調整しうるようにして各インピーダンス素子を形成してもよい。
【０１４０】
図２２（Ａ）には２つの移相回路の後段に位相反転回路８０を配置した構成が示されており、図１に示した同調増幅器１あるいは図１３に示した同調増幅器２に対応している。このように、後段に位相反転回路８０を配置した場合には、この位相反転回路８０に出力バッファの機能を持たせることにより、大きな出力電流を取り出すこともできる。
【０１４１】
図２２（Ｂ）には２つの移相回路の間に位相反転回路８０を配置した構成が示されている。このように、中間に位相反転回路８０を配置した場合には、前段の移相回路と後段の移相回路の相互干渉を完全に防止することができる。
【０１４２】
図２２（Ｃ）には２つの移相回路のさらに前段に位相反転回路８０を配置した構成が示されている。このように、前段に位相反転回路８０を配置した場合には、前段の移相回路に対する帰還側インピーダンス素子７０ａや入力側インピーダンス素子７４ａの影響を最小限に抑えることができる。
【０１４３】
また、上述した各実施形態において示した移相回路には可変抵抗１６等が含まれている。これらの可変抵抗は、具体的には接合型あるいはＭＯＳ型のＦＥＴを用いて実現することができる。
【０１４４】
図２３は、図１に示した同調増幅器１を構成する２種類の移相回路内の可変抵抗をＦＥＴに置き換えた場合の移相回路の構成を示す図である。同図（Ａ）には、移相回路１０Ｃにおいて可変抵抗１６をＦＥＴに置き換えた構成が示されている。同図（Ｂ）には、移相回路１１０Ｃにおいて可変抵抗１１６をＦＥＴに置き換えた構成が示されている。
【０１４５】
このように、ＦＥＴのソース・ドレイン間に形成されるチャネルを抵抗体として利用して可変抵抗１６あるいは１１６の代わりに使用すると、ゲート電圧を可変に制御してこのチャネル抵抗をある範囲で任意に変化させて各移相回路における位相シフト量を変えることができる。したがって、各同調増幅器において一巡する信号の位相シフト量が０°となる周波数を変えることができるため、同調増幅器の同調周波数を任意に変更することができる。
【０１４６】
なお、図２３に示した各移相回路は、可変抵抗を１つのＦＥＴ、すなわちｐチャネルあるいはｎチャネルのＦＥＴによって構成したが、ｐチャネルのＦＥＴとｎチャネルのＦＥＴとを並列接続して１つの可変抵抗を構成するようにしてもよい。抵抗値を可変する場合にはこのゲート電圧の大きさを変えればよい。このように、２つのＦＥＴを組み合わせて可変抵抗を構成することにより、ＦＥＴの非線形領域の改善を行うことができるため、同調信号の歪みを少なくすることができる。
【０１４７】
また、図２３には図１に示した同調増幅器１を構成する２つの移相回路１０Ｃ、１１０Ｃ内の可変抵抗をＦＥＴに置き換えた場合について説明したが、図１３に示す同調増幅器２を構成する２つの移相回路３０Ｃ、１３０Ｃ内の可変抵抗をＦＥＴに置き換える場合や、図９等に示すその他の移相回路内の可変抵抗をＦＥＴに置き換える場合も同様である。
【０１４８】
また、上述した各実施形態において示した移相回路は、キャパシタ１４等と直列に接続された可変抵抗の抵抗値を変化させて位相シフト量を変化させることにより全体の同調周波数を変えるようにしたが、キャパシタ１４等を可変容量素子によって形成し、その静電容量を変化させることにより全体の同調周波数を変えるようにしてもよい。
【０１４９】
図２４は、図１に示した同調増幅器１を構成する２種類の移相回路内のキャパシタを可変容量ダイオードに置き換えた場合の移相回路の構成を示す図である。同図（Ａ）には、移相回路１０Ｃにおいて可変抵抗１６を固定抵抗に置き換えるとともにキャパシタ１４を可変容量ダイオードに置き換えた構成が示されている。同図（Ｂ）には、移相回路１１０Ｃにおいて可変抵抗１１６を固定抵抗に置き換えるとともにキャパシタ１１４を可変容量ダイオードに置き換えた構成が示されている。
【０１５０】
なお、図２４（Ａ）、（Ｂ）において、可変容量ダイオードに直列に接続されたキャパシタは、可変容量ダイオードのアノード・カソード間に逆バイアス電圧を印加する際にその直流電流を阻止するためのものであり、そのインピーダンスは動作周波数において極めて小さく、すなわち大きな静電容量を有している。また、図２４（Ａ）、（Ｂ）に示したキャパシタの両端の電位は直流成分をみると一定であるため、交流成分の振幅より大きな逆バイアス電圧をアノード・カソード間に印加することにより、各可変容量ダイオードを容量可変のキャパシタとして機能させることができる。
【０１５１】
このように、キャパシタ１４あるいは１１４を可変容量ダイオードで構成し、そのアノード・カソード間に印加する逆バイアス電圧の大きさを可変に制御してこの可変容量ダイオードの静電容量をある範囲で任意に変化させて各移相回路における位相シフト量を変えることができる。したがって、同調増幅器において一巡する信号の位相シフト量が０°となる周波数を変えることができ、同調増幅器の同調周波数を任意に変更することができる。
【０１５２】
ところで、上述した図２４（Ａ）、（Ｂ）では可変容量素子として可変容量ダイオードを用いたが、ソースおよびドレインを直流的に固定電位に接続するとともにゲートに可変電圧を印加したＦＥＴを用いるようにしてもよい。上述したように、図２４（Ａ）、（Ｂ）に示した可変容量ダイオードの両端電位は直流的に固定されているため、これらの可変容量ダイオードを上述したＦＥＴに置き換えるだけでよく、ゲートに印加する電圧を可変することによりゲート容量、すなわちＦＥＴが有する静電容量を変えることができる。
【０１５３】
また、上述した図２４（Ａ）、（Ｂ）では可変容量ダイオードの静電容量のみを可変したが、同時に可変抵抗の抵抗値を可変するようにしてもよい。また、これらの可変抵抗を図２３に示したようにＦＥＴのチャネル抵抗を利用して形成することができることはいうまでもない。特に、ｐチャネルのＦＥＴとｎチャネルのＦＥＴとを並列接続して１つの可変抵抗を構成した場合には、ＦＥＴの非線形領域の改善を行うことができるため、同調信号の歪みを少なくすることができる。
【０１５４】
なお、図２４には図１に示した同調増幅器１を構成する２つの移相回路１０Ｃ、１１０Ｃ内のキャパシタを可変容量素子に置き換えた場合について説明したが、図１３に示す同調増幅器２を構成する２つの移相回路３０Ｃ、１３０Ｃ内のキャパシタを可変容量素子に置き換える場合も同様である。
【０１５５】
また、、上述した各実施形態において示した移相回路は、インダクタ１７等と直列に接続された可変抵抗の抵抗値を変化させて位相シフト量を変化させることにより全体の同調周波数を変えるようにしたが、インダクタ１７等を可変インダクタによって形成し、そのインダクタンスを変化させることにより全体の同調周波数を変えるようにしてもよい。
【０１５６】
図２５は、各種の移相回路内のインダクタを可変インダクタに置き換えた場合の構成を示す図である。同図（Ａ）には、図９に示した移相回路１０Ｌにおいてインダクタ１７を可変インダクタ１７ａに置き換えた構成が示されている。同図（Ｂ）には、図１１に示した移相回路１１０Ｌにおいてインダクタ１１７を可変インダクタ１１７ａに置き換えた構成が示されている。
【０１５７】
このように、インダクタ１７あるいは１１７を可変インダクタ１７ａあるいは１１７ａに置き換えて、それらが有するインダクタンスをある範囲で任意に変化させて各移相回路における位相シフト量を変えることができる。したがって、各同調増幅器において一巡する信号の位相シフト量が０°となる周波数を変えることができ、同調周波数を任意に変更することができる。
【０１５８】
また、上述した図２５（Ａ）、（Ｂ）では可変インダクタ１７ａ等のインダクタンスのみを可変したが、同時に可変抵抗の抵抗値を可変するようにしてもよい。また、図２５では図９あるいは図１１に示した移相回路内のインダクタ１７等を可変インダクタに置き換えた場合について説明したが、図１８に示した移相回路３０Ｌ内のインダクタ３７あるいは図２０に示した移相回路１３０Ｌ内のインダクタ１３７を可変インダクタに置き換える場合も同様である。
【０１５９】
ところで、上述したように可変抵抗や可変容量素子あるいは可変インダクタを用いる場合の他、素子定数が異なる複数の抵抗あるいはキャパシタを用意しておいて、スイッチを切り換えることにより、これら複数の素子の中から１つあるいは複数を選ぶようにしてもよい。この場合にはスイッチ切り換えにより接続する素子の個数および接続方法（直列接続、並列接続あるいはこれらの組み合わせ）によって、素子定数を不連続に切り換えることができる。例えば、可変抵抗の代わりに抵抗値がＲ、２Ｒ、４Ｒ、…といった２のｎ乗の系列の複数の抵抗を用意しておいて、１つあるいは任意の複数を選択して直列接続することにより、等間隔の抵抗値の切り換えをより少ない素子で容易に実現することができる。同様に、キャパシタの代わりに静電容量がＣ、２Ｃ、４Ｃ、…といった２のｎ乗の系列の複数のキャパシタを用意しておいて、１つあるいは任意の複数を選択して並列接続することにより、等間隔の静電容量の切り換えをより少ない素子で容易に実現することができる。このため、同調周波数が複数ある回路、例えばＡＭラジオに本実施形態の同調増幅器を適用して、複数の放送局から１局を選局して受信するような用途に適している。
【０１６０】
図２６は、図２５に示した可変インダクタ１７ａ等の具体例を示す図であり、半導体基板上に形成された平面構造の概略が示されている。なお、同図に示す可変インダクタ１７ａの構造は、そのまま可変インダクタ１３７ａ等にも適用することができる。
【０１６１】
同図に示す可変インダクタ１７ａは、半導体基板３１０上に形成された渦巻き形状のインダクタ導体３１２と、その外周を周回するように形成された制御用導体３１４と、これらインダクタ導体３１２および制御用導体３１４の両方を覆うように形成された絶縁性磁性体３１８とを含んで構成されている。
【０１６２】
上述した制御用導体３１４は、制御用導体３１４の両端に可変のバイアス電圧を印加するために可変電圧電源３１６が接続され、この可変電圧電源３１６によって印加する直流バイアス電圧を可変に制御することにより、制御用導体３１４に流れるバイアス電流を変化させることができる。
【０１６３】
また、半導体基板３１０は、例えばｎ型シリコン基板（ｎ−Ｓｉ基板）やその他の半導体材料（例えばゲルマニウムやアモルファスシリコン等の非晶質材料）が用いられる。また、インダクタ導体３１２は、アルミニウムや金等の金属薄膜あるいはポリシリコン等の半導体材料を渦巻き形状に形成されている。
【０１６４】
なお、図２６に示した半導体基板３１０には、可変インダクタ１７ａの他に図９等に示した移相回路を含む同調増幅器の他の構成部品が形成されている。
【０１６５】
図２７は、図２６に示した可変インダクタ１７ａのインダクタ導体３１２および制御用導体３１４の形状をさらに詳細に示す図である。
【０１６６】
同図に示すように、内周側に位置するインダクタ導体３１２は、所定ターン数（例えば約４ターン）の渦巻き形状に形成されており、その両端には２つの端子電極３２２、３２４が接続されている。同様に、外周側に位置する制御用導体３１４は、所定ターン数（例えば約２ターン）の渦巻き形状に形成されており、その両端には２つの制御電極３２６、３２８が接続されている。
【０１６７】
図２８は、図２７のＡ−Ａ線拡大断面図であり、インダクタ導体３１２と制御用導体３１４を含む絶縁性磁性体３１８の横断面が示されている。
【０１６８】
同図に示すように、半導体基板３１０表面に絶縁性の磁性体膜３１８ａを介してインダクタ導体３１２および制御用導体３１４が形成されており、さらにその表面に絶縁性の磁性体膜３１８ｂが被覆形成されている。これら２つの磁性体膜３１８ａ、３１８ｂによって図２６に示した絶縁性磁性体３１８が形成されている。
【０１６９】
例えば、磁性体膜３１８ａ、３１８ｂとしては、ガンマ・フェライトやバリウム・フェライト等の各種磁性体膜を用いることができる。また、これらの磁性体膜の材質や形成方法については各種のものが考えられ、例えばＦｅＯ等を真空蒸着して磁性体膜を形成する方法や、その他分子線エピタキシー法（ＭＢＥ法）、化学気相成長法（ＣＶＤ法）、スパッタ法等を用いて磁性体膜を形成する方法等がある。
【０１７０】
なお、絶縁膜３３０は、非磁性体材料によって形成されており、インダクタ導体３１２および制御用導体３１４の各周回部分の間を覆っている。このようにして各周回部分間の磁性体膜３１８ａ、３１８ｂを排除することにより、各周回部分間に生じる漏れ磁束を最小限に抑えることができるため、インダクタ導体３１２が発生する磁束を有効に利用して大きなインダクタンスを有する可変インダクタ１７ａを実現することができる。
【０１７１】
このように、図２６等に示した可変インダクタ１７ａは、インダクタ導体３１２と制御用導体３１４とを覆うように絶縁性磁性体３１８（磁性体膜３１８ａ、３１８ｂ）が形成されており、制御用導体３１４に流す直流バイアス電流を可変に制御することにより、上述した絶縁性磁性体３１８を磁路とするインダクタ導体３１２の飽和磁化特性が変化し、インダクタ導体３１２が有するインダクタンスが変化する。
【０１７２】
したがって、インダクタ導体３１２のインダクタンスそのものを直接変化させることができ、しかも、半導体基板３１０上に薄膜形成技術や半導体製造技術を用いて形成することができるため製造が容易となる。さらに、半導体基板３１０上には同調増幅器１等の他の構成部品を形成することも可能であるため、各実施形態の同調増幅器の全体を集積化によって一体形成する場合に適している。
【０１７３】
なお、図２６等に示した可変インダクタ１７ａは、インダクタ導体３１２と制御用導体３１４とを交互に周回させたり、インダクタ導体３１２と制御用導体３１４とを重ねて形成するようにしてもよい。いずれの場合であっても、制御用導体３１４に流す直流バイアス電流を変化させることにより絶縁性磁性体３１８の飽和磁化特性を変えることができ、インダクタ導体３１２が有するインダクタンスをある範囲で変化させることができる。
【０１７４】
また、図２６等に示した可変インダクタ１７ａは、半導体基板３１０上にインダクタ導体３１２等を形成する場合を例にとり説明したが、セラミックス等の絶縁性あるいは導電性の各種基板上に形成するようにしてもよい。
【０１７５】
また、磁性体膜３１８ａ、３１８ｂとして絶縁性材料を用いたが、メタル粉（ＭＰ）のような導電性材料を用いるようにしてもよい。但し、このような導電性の磁性体膜を上述した絶縁性の磁性体膜３１８ａ等に置き換えて使用すると、インダクタ導体３１２等の各周回部分が短絡されてインダクタ導体として機能しなくなるため、各インダクタ導体と導電性の磁性体膜との間を電気的に絶縁する必要がある。この絶縁方法としては、インダクタ導体３１２等を酸化して絶縁酸化膜を形成する方法や、化学気相法等によりシリコン酸化膜あるいは窒化膜を形成する方法等がある。
【０１７６】
特に、メタル粉等の導電性材料は、ガンマ・フェライト等の絶縁性材料に比べると透磁率が大きいため、大きなインダクタンスを確保することができる利点がある。
【０１７７】
また、図２６等に示した可変インダクタ１７ａは、インダクタ導体３１２と制御用導体３１４の両方の全体を絶縁性磁性体３１８で覆うようにしたが、一部のみを覆って磁路を形成するようにしてもよい。このように、磁路となる絶縁性磁性体（あるいは導電性磁性体でもよい）を部分的に形成した場合には、磁路が狭まることによりインダクタ導体３１２および制御用導体３１４によって生じる磁束が飽和しやすくなる。したがって、制御用導体３１４に少ないバイアス電流を流した場合であっても磁束が飽和し、少ないバイアス電流を可変に制御することによりインダクタ導体３１２のインダクタンスを変えることができる。このため、制御系の構造を簡略化することができる。
【０１７８】
また、図２６等に示した可変インダクタ１７ａは、インダクタ導体３１２と制御用導体３１４とを同心状に巻回して形成したが、これら各導体を半導体基板３１０表面の隣接した位置に形成してそれらの間を絶縁性あるいは導電性の磁性体によって形成した磁路によって磁気結合させてもよい。
【０１７９】
図２９は、インダクタ導体と制御用導体とを隣接した位置に並べて形成した場合の可変インダクタ１７ｂの概略を示す平面図である。
【０１８０】
同図に示す可変インダクタ１７ｂは、半導体基板３１０上に形成された渦巻き形状のインダクタ導体３１２ａと、このインダクタ導体３１２ａと隣接した位置に形成された渦巻き形状の制御用導体３１４ａと、インダクタ導体３１２ａと制御用導体３１４ａの各渦巻き中心を覆うように形成された絶縁性磁性体（あるいは導電性磁性体）３１９とを含んで構成されている。
【０１８１】
図２６等に示した可変インダクタ１７ａと同様に、制御用導体３１４ａにはその両端に可変のバイアス電圧を印加するために可変電圧電源３１６が接続されており、この可変電圧電源３１６によって印加するバイアス電圧を可変に制御することにより、制御用導体３１４ａに流れる所定のバイアス電流を変化させることができる。
【０１８２】
上述した可変インダクタ１７ｂは、インダクタ導体３１２ａと制御用導体３１４ａの各渦巻き中心を通るように環状の絶縁性磁性体３１９（磁性体膜３１９ａ、３１９ｂ）が形成されている。したがって、制御用導体３１４ａに流す直流バイアス電流を可変に制御することにより、上述した磁性体３１９を磁路とするインダクタ導体３１２ａの飽和磁化特性が変化し、インダクタ導体３１２ａが有するインダクタンスも変化する。
【０１８３】
また、上述した各実施形態の同調増幅器１等を半導体基板上に形成した場合には、キャパシタ１４等としてあまり大きな静電容量を設定することができない。したがって、半導体基板上に実際に形成したキャパシタの小さな静電容量を回路を工夫することにより、見かけ上大きくすることができれば時定数Ｔを大きな値に設定して同調周波数の低周波数化を図る際に都合がよい。
【０１８４】
図３０は、図１等に示した移相回路１０Ｃ等に用いたキャパシタ１４等を素子単体ではなく回路によって構成した変形例を示す図であり、実際に半導体基板上に形成されるキャパシタの静電容量を見かけ上大きくみせる静電容量変換回路として機能する。なお、図３０に示した回路全体が移相回路１０Ｃ等に含まれるキャパシタ１４等に対応している。
【０１８５】
図３０に示す静電容量変換回路１４ａは、所定の静電容量Ｃ０ を有するキャパシタ２１０と、２つのオペアンプ２１２、２１４と、４つの抵抗２１６、２１８、２２０、２２２とを含んで構成されている。
【０１８６】
１段目のオペアンプ２１２は、出力端子と反転入力端子との間に抵抗２１８（この抵抗値をＲ１８とする）が接続されており、さらにこの反転入力端子が抵抗２１６（この抵抗値をＲ１６とする）を介して接地されている。
【０１８７】
１段目のオペアンプ２１２の非反転入力端子に印加される電圧Ｅ１ と出力端子に現れる電圧Ｅ２ との間には、
【数９】

の関係がある。この１段目のオペアンプ２１２は、主にインピーダンス変換を行うバッファとして機能するものであり、利得は１であってもよい。利得１の場合とはＲ１８／Ｒ１６＝０のとき、すなわちＲ１６を無限大（抵抗２１６を除去すればよい）、あるいはＲ１８を０Ω（直結すればよい）に設定する。
【０１８８】
また、２段目のオペアンプ２１４は、出力端子と反転入力端子との間に抵抗２２２（この抵抗値をＲ２２とする）が接続されているとともに反転入力端子と上述したオペアンプ２１２の出力端子との間に抵抗２２０（この抵抗値をＲ２０とする）が接続されており、さらに非反転入力端子が接地されている。
【０１８９】
２段目のオペアンプ２１４の出力端子に現れる電圧をＥ３ とすると、この電圧Ｅ３ と１段目のオペアンプ２１２の出力端子に現れる電圧Ｅ２ との間には、
【数１０】

の関係がある。このように２段目のオペアンプ２１４は反転増幅器として機能するものであり、その入力側を高インピーダンスに設定するために１段目のオペアンプ２１２が使用されている。
【０１９０】
また、このような接続がなされた１段目のオペアンプ２１２の非反転入力端子と２段目のオペアンプ２１４の出力端子との間には、上述したように所定の静電容量を有するキャパシタ２１０が接続されている。
【０１９１】
図３０に示した静電容量変換回路１４ａにおいて、キャパシタ２１０を除く回路全体の伝達関数をＫ４ とすると、静電容量変換回路１４ａは図３１に示すシステム図で表すことができる。図３２は、これをミラーの定理によって変換したシステム図である。
【０１９２】
図３１に示したインピーダンスＺ０ を用いて図３２に示したインピーダンスＺ１ を表すと、
【数１１】

となる。ここで、図３０に示した静電容量変換回路１４ａの場合には、インピーダンスＺ０ ＝１／（ｊωＣ０ ）であり、これを（１１）式に代入して、
【数１２】

【数１３】

となる。この（１３）式は、静電容量変換回路１４ａにおいてキャパシタ２１０が有する静電容量Ｃ０ が見掛け上は（１−Ｋ４）倍になったことを示している。したがって、増幅器の利得Ｋ４ が負の場合には（１−Ｋ４）は常に１より大きくなるため、静電容量Ｃ０ を大きいほうに変化させることができる。
【０１９３】
ところで、図３０に示した静電容量変換回路１４ａにおける増幅器の利得、すなわちオペアンプ２１２と２１４の全体により構成される増幅器の利得Ｋ４ は、（９）式および（１０）式から、
【数１４】

となる。この（１４）式を（１３）式に代入すると、
【数１５】

となる。したがって、４つの抵抗２１６、２１８、２２０、２２２の抵抗値を所定の値に設定することにより、２つの端子２２４、２２６間の見掛け上の静電容量Ｃを大きくすることができる。
【０１９４】
また、１段目のオペアンプ２１２による増幅器の利得が１の場合、すなわち上述したようにＲ１６を無限大（抵抗２１６を除去）、あるいはＲ１８を０Ωに設定したときであってＲ１８／Ｒ１６＝０の場合には、上述した（１５）式は簡略化されて、
【数１６】

となる。
【０１９５】
このように、上述した静電容量変換回路１４ａは、抵抗２２０と抵抗２２２との抵抗比Ｒ２２／Ｒ２０あるいは抵抗２１６と抵抗２１８との抵抗比Ｒ１８／Ｒ１６を変えることにより、実際に半導体基板上に形成するキャパシタ２１０の静電容量Ｃ０ を見掛け上大きい方に変換することができる。そのため、半導体基板上に図１等に示した同調増幅器１等の全体を形成するような場合には、半導体基板上に小さな静電容量Ｃ０ を有するキャパシタ２１０を形成しておいて、図３０に示した回路によって大きな静電容量Ｃに変換することができ、集積化に際して好都合となる。特に、このようにして大きな静電容量を確保することができれば、図１に示した同調増幅器１等の全体の実装面積を小型化して、材料コスト等の低減も可能となる。
【０１９６】
また、抵抗２１６、２１８、２２０、２２２の中の少なくとも１つを可変抵抗により形成することにより、具体的には接合型やＭＯＳ型のＦＥＴあるいはｐチャネルＦＥＴとｎチャネルＦＥＴとを並列に接続して可変抵抗を形成することにより、容易に静電容量が可変のキャパシタを形成することができる。したがって、このキャパシタを図２４に示した可変容量ダイオードの代わりに使用することにより、位相シフト量をある範囲で任意に変化させることができる。このため、同調増幅器において一巡する信号の位相シフト量が０°となる周波数を変えることができ、上述した同調増幅器の同調周波数を任意に変更することができる。
【０１９７】
なお、上述したように第１段目のオペアンプ２１２は入力インピーダンスを高くするためのバッファとして用いているため、このオペアンプ２１２をエミッタホロワ回路あるいはソースホロワ回路に置き換えるようにしてもよい。
【０１９８】
ところで、上述した図３０では、所定の利得を有する増幅器とキャパシタとを組み合わせることにより、見かけ上の静電容量を実際にキャパシタ素子が有する静電容量より大きくする場合を説明したが、キャパシタの代わりにインダクタを用い、このインダクタが有するインダクタンスを見かけ上大きくすることもできる。
【０１９９】
すなわち、上述したように図３１に示したインピーダンスＺ０ を用いて図３２に示したインピーダンスＺ１ を表すと（１１）式のようになる。ここで、インダクタンスＬ０ を有するインダクタの場合には、インピーダンスＺ０ ＝ｊωＬ０ であり、これを（１１）式に代入して、
【数１７】

【数１８】

となる。この（１８）式は、実際にインダクタ素子が有するインダクタンスが見かけ上１／（１−Ｋ４ ）倍になったことを示しており、利得Ｋ４ が０から１の間に設定されているときには見かけ上のインダクタンスが大きくなることがわかる。
【０２００】
図３３は、図９等に示した移相回路１０Ｌ等に用いたインダクタ１７等を素子単体ではなく回路によって構成した変形例を示す図であり、実際に半導体基板上に形成されるインダクタ素子（インダクタ導体）のインダクタンスを見かけ上大きくみせるインダクタンス変換回路として機能する。なお、図３３に示した回路全体が移相回路１０Ｌに含まれるインダクタ１７等に対応している。
【０２０１】
図３３に示すインダクタンス変換回路１７ｃは、所定のインダクタンスＬ０ を有するインダクタ２６０と、２つのオペアンプ２６２、２６４と、２つの抵抗２６６、２６８とを含んで構成されている。
【０２０２】
１段目のオペアンプ２６２は、出力端子が反転入力端子に接続された利得１の非反転増幅器であって、主にインピーダンス変換を行うバッファとして機能する。同様に、２段目のオペアンプ２６４も出力端子が反転入力端子に接続されており、利得１の非反転増幅器として機能する。また、これら２つの非反転増幅器の間には抵抗２６６と２６８による分圧回路が挿入されている。
【０２０３】
このように、間に分圧回路を挿入することにより、２つの非反転増幅器を含む増幅器全体の利得を０から１の間で自由に設定することができる。
【０２０４】
図３３に示したインダクタンス変換回路１７ｃにおいて、インダクタ２６０を除く回路（増幅器）全体の伝達関数をＫ４ とすると、この利得Ｋ４ は抵抗２６６と２６８によって構成される分圧回路の分圧比によって決まり、それぞれの抵抗値をＲ６６、Ｒ６８とすると、
【数１９】

となる。この利得Ｋ４ を（１８）式に代入して見かけ上のインダクタンスＬを計算すると、
【数２０】

となる。したがって、抵抗２６６と２６８の抵抗比Ｒ６８／Ｒ６６を大きくすることにより、２つの端子２５４、２５６間の見かけ上のインダクタンスＬを大きくすることができる。例えば、Ｒ６８＝Ｒ６６の場合には、（２０）式からインダクタンスＬをＬ０ の２倍にすることができる。
【０２０５】
このように、上述したインダクタンス変換回路１７ｃは、２つの非反転増幅器の間に挿入された分圧回路の分圧比を変えることにより、実際に接続されているインダクタ２６０のインダクタンスＬ０ を見かけ上大きくすることができる。そのため、半導体基板上に図９等に示した移相回路を含む同調増幅器の全体を形成するような場合には、半導体基板上に小さなインダクタンスＬ０ を有するインダクタ２６０をスパイラル状の導体等によって形成しておいて、図３３に示したインダクタンス変換回路によって大きなインダクタンスＬに変換することができ、集積化に際して好都合となる。特に、このようにして大きなインダクタンスを確保することができれば、同調増幅器の同調周波数を比較的低い周波数領域まで下げることが容易となる。また、集積化を行うことにより、同調増幅器全体の実装面積を小型化して、材料コスト等の低減も可能となる。
【０２０６】
なお、抵抗２６６、２６８による分圧回路の分圧比を固定した場合の他、これら２つの抵抗２６６、２６８の少なくとも一方を可変抵抗により形成することにより、具体的には接合型やＭＯＳ型のＦＥＴあるいはｐチャネルＦＥＴとｎチャネルＦＥＴとを並列に接続して可変抵抗を形成することにより、この分圧比を連続的に変化させてもよい。この場合には、図３３に示したオペアンプ２６２、２６４を含んで構成される増幅器全体の利得が変わり、端子２５４、２５６間のインダクタンスＬも連続的に変化する。したがって、このインダクタンス変換回路１７ｃを図２５に示した可変インダクタ１７ａ等の代わりに使用することにより、各移相回路における位相シフト量をある範囲で任意に変化させることができる。このため、同調増幅器において一巡する信号の位相シフト量が０°となる周波数を変えることができ、上述した同調増幅器の同調周波数を任意に変更することができる。
【０２０７】
また、図３３に示したインダクタンス変換回路１７ｃは、２つのオペアンプ２６２、２６４を含む増幅器全体の利得が１以下に設定されているため、全体をエミッタホロワ回路あるいはソースホロワ回路に置き換えるようにしてもよい。
【０２０８】
なお、この発明は上述した各種の実施形態に限定されるものではなく、この発明の要旨の範囲内で種々の変形実施が可能である。
【０２０９】
例えば、図１等に示した各同調増幅器においては、帰還側インピーダンス素子として抵抗値が固定の帰還抵抗７０を用い、入力側インピーダンス素子として抵抗値が固定の入力抵抗７４を用いるようにしたが、少なくとも一方の抵抗を可変抵抗により構成して最大減衰量を任意に変更可能に形成してもよい。この場合に、可変抵抗を図２３に示したようにＦＥＴのチャネル抵抗を利用して形成することができることはいうまでもない。特に、ｐチャネルのＦＥＴとｎチャネルのＦＥＴとを並列接続して１つの可変抵抗を構成した場合には、ＦＥＴの非線形領域の改善を行うことができるため、同調信号の歪みを少なくすることができる。
【０２１０】
同様に、帰還側インピーダンス素子および入力側インピーダンス素子をキャパシタとした場合には少なくとも一方を可変容量ダイオードやゲート容量可変のＦＥＴにより構成して最大減衰量を任意に変更可能に形成してもよい。
【０２１１】
また、上述した実施形態の同調増幅器１等には２つの移相回路が含まれているが、同調周波数を可変する場合には、両方の移相回路に含まれるＣＲ回路あるいはＬＲ回路を構成する抵抗とキャパシタあるいはインダクタの少なくとも１つの素子定数を変える場合の他、一方の移相回路に含まれるＣＲ回路あるいはＬＲ回路を構成する抵抗とキャパシタあるいはインダクタの少なくとも１つの素子定数を変える場合が考えられる。また、全ての抵抗やキャパシタあるいはインダクタの各素子定数を固定して、同調周波数が固定の同調増幅器を構成することもできる。
【０２１２】
また、上述した各実施形態においては、同調増幅器を構成する一方の移相回路１０Ｃ、１０Ｌ等を接合型のＦＥＴを用いて構成したが、ＭＯＳ型のＦＥＴにより、あるいはバイポーラトランジスタによって移相回路を構成するようにしてもよい。
【０２１３】
ＦＥＴをバイポーラトランジスタに置き換えた移相回路においては、入力信号がベースに入力されたときにベース・エミッタ間で電流が流れるため、エミッタに現れる電圧（交流電圧）とコレクタに現れる電圧（交流電圧）とは正確には同じにはならない。但し、電流増幅度が数十倍から百倍程度である場合には、その差は１％から数％であり、事実上無視することができる。あるいは、エミッタ抵抗よりコレクタ抵抗を若干大きく設定することにより、この差を補正するようにしてもよい。
【０２１４】
特に、バイポーラトランジスタを用いて移相回路を構成した場合には、動作周波数の上限を高くすることができ、また、ベース・エミッタ間の電位差がＦＥＴのゲート・ソース間の電位差よりも小さいため移相回路に入出力される信号振幅の減衰を少なくすることができる。したがって、バイポーラトランジスタを用いて構成した移相回路は、同調増幅器の前段に用いる場合に適している。
【０２１５】
また、上述した各実施形態においては、同調増幅器を構成する一方の移相回路１１０Ｃ、１１０Ｌ等をオペアンプを用いて構成することにより安定度を高めることができるが、各実施形態のような使い方をする場合にはオフセット電圧や電圧利得はそれほど高性能なものが要求されないため、所定の増幅度を有する差動入力増幅器を各移相回路内のオペアンプの代わりに使用するようにしてもよい。
【０２１６】
図３４は、オペアンプの構成の中で各実施形態の移相回路の動作に必要な部分を抽出した回路図であり、全体が所定の増幅度を有する差動入力増幅器として動作する。同図に示す差動入力増幅器は、ＦＥＴにより構成された差動入力段３００と、この差動入力段３００に定電流を与える定電流回路３０２と、定電流回路３０２に所定のバイアス電圧を与えるバイアス回路３０４と、差動入力段３００に接続された出力アンプ３０６とによって構成されている。同図に示すように、実際のオペアンプに含まれている電圧利得を稼ぐための多段増幅回路を省略して、差動入力増幅器の構成を簡略化し、広帯域化を図ることができる。このように、回路の簡略化を行うことにより、動作周波数の上限を高くすることができるため、その分この差動入力増幅器を用いて構成した同調増幅器１等の動作周波数の上限を高くすることができる。
【０２１７】
【発明の効果】
上述したように、各請求項に係る発明においては、第１および第２の移相回路のそれぞれにおいて入出力信号の振幅が変化せずに位相のみがキャパシタ等の素子定数に応じて所定量シフトされており、２つの移相回路の全体により位相シフト量の合計が１８０°となるような周波数で同調動作が行われる。
【０２１８】
特に、上述した移相回路に含まれる差動入力増幅器を演算増幅器とした場合には、移相回路の動作を安定させることができる。
【０２１９】
また、入力側インピーダンス素子と帰還側インピーダンス素子の両方をともに抵抗により、あるいはともにキャパシタにより形成しておいて、少なくとも一方の素子定数を変化させることにより、同調点における振幅変動を伴わずに同調点から離れた周波数領域での最大減衰量を任意に変化させることができる。
【０２２０】
また、移相回路に含まれるキャパシタやインダクタあるいはこれらの素子と直列に接続された抵抗の各素子定数を変化させることにより、各移相回路における位相シフト量が変わるため、２つの移相回路の全体により位相シフト量の合計が１８０°となる周波数、すなわち同調周波数を任意に変化させることができる。特に、抵抗値を変化させる場合にはＦＥＴのソース・ドレイン間抵抗を利用し、キャパシタの静電容量を変化させる場合には可変容量ダイオード等の素子を利用することができ、これらは半導体基板上に形成する場合に適している。さらに、インダクタについては、半導体基板上に形成された相互に磁気結合した２本の電極において、一方の電極に流す直流バイアス電流の大きさを変えることにより他方の電極が有するインダクタンスを直接変化させることができ、この場合も可変インダクタを半導体基板上に形成する場合に適している。
【０２２１】
また、上述したように同調周波数を変化させるには、抵抗等の素子定数を連続的に変化させる場合のほか、複数の抵抗等をスイッチ切り換えにより選択的に用いてもよい。
【０２２２】
また、移相回路に含まれるキャパシタやインダクタは、キャパシタ素子あるいはインダクタ素子と増幅器とを並列接続した回路に置き換えることにより、実際にキャパシタ素子が有する静電容量やインダクタ素子が有するインダクタンスを見かけ上大きくみせることができる。したがって、実際には少ない占有面積でキャパシタ素子やインダクタ素子を形成しておいて、これらの静電容量やインダクタンスを大きな値に変換することができ、半導体基板の占有面積を少なくすることができる。
【０２２３】
また、各請求項の同調増幅器を構成する各素子は集積回路の製法によって形成することが可能であるから、同調増幅器を半導体ウエハ上に集積回路として小型に形成でき、大量生産によって安価に作ることができる。
【０２２４】
特に、各移相回路におけるＣＲ回路の可変抵抗としてＦＥＴのソース・ドレイン間のチャネルを使用し、このＦＥＴのゲートに印加する制御電圧を変化させてチャネルの抵抗を変化させるように構成すると、制御電圧を印加する配線のインダクタンスや静電容量の影響を回避することができ、ほぼ設計どおりの理想的な特性を備えた同調増幅器を得ることができる。
【０２２５】
また、この発明の同調増幅器は、最大減衰量が入力側インピーダンス素子と帰還側インピーダンス素子の抵抗比によって決まるとともに、同調周波数が各移相回路におけるＣＲ回路やＬＲ回路の時定数によって決まるため、最大減衰量や同調周波数および同調周波数における利得を互いに干渉しあうことなく設定することができる。
【図面の簡単な説明】
【図１】この発明を適用した第１の実施形態の同調増幅器の構成を示す回路図である。
【図２】図１に示した前段の移相回路の構成を抜き出して示した回路図である。
【図３】前段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図４】図１に示した後段の移相回路の構成を抜き出して示した回路図である。
【図５】後段の位相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図６】２つの移相回路の全体を所定の伝達関数を有する回路に置き換えたシステム図である。
【図７】図６に示すシステムをミラーの定理によって変換したシステム図である。
【図８】第１の実施形態の同調増幅器の同調特性を示す図である。
【図９】移相回路の他の例を示す回路図である。
【図１０】図９に示す移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１１】移相回路の他の例を示す回路図である。
【図１２】図１１に示す移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１３】この発明を適用した第２の実施形態の同調増幅器の構成を示す回路図である。
【図１４】図１３に示した前段の移相回路の構成を抜き出して示した回路図である。
【図１５】前段の移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図１６】図１３に示した後段の移相回路の構成を抜き出して示した回路図である。
【図１７】後段の移相回路の入出力電圧とキャパシタ等に現れる電圧との関係を示すベクトル図である。
【図１８】移相回路の他の例を示す回路図である。
【図１９】図１８に示す移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図２０】移相回路の他の例を示す回路図である。
【図２１】図２０に示す移相回路の入出力電圧とインダクタ等に現れる電圧との関係を示すベクトル図である。
【図２２】移相回路と位相反転回路との接続形態を示す図である。
【図２３】移相回路の可変抵抗をＦＥＴに置き換えた移相回路の構成を示す図である。
【図２４】移相回路のキャパシタを可変容量ダイオードに置き換えた移相回路の構成を示す図である。
【図２５】移相回路のインダクタを可変インダクタに置き換えた移相回路の構成を示す図である。
【図２６】可変インダクタの一例を示す図である。
【図２７】図２６に示した可変インダクタのインダクタ導体および制御用導体の形状をさらに詳細に示す図である。
【図２８】図２７のＡ−Ａ線拡大断面図である。
【図２９】可変インダクタの他の例を示す図である。
【図３０】キャパシタが実際に有する静電容量を見かけ上大きくする静電容量変換回路の構成を示す図である。
【図３１】図３０に示した回路を伝達関数を用いて表した図である。
【図３２】図３１に示す構成をミラーの定理によって変換した図である。
【図３３】インダクタが実際に有するインダクタンスを見かけ上大きくするインダクタンス変換回路の構成を示す図である。
【図３４】オペアンプの構成の中でこの発明の移相回路の動作に必要な部分を抽出した回路図である。
【図３５】従来の同調増幅器における同調周波数、同調周波数における利得、最大減衰量の関係の一例を示す特性曲線図である。
【符号の説明】
１ 同調増幅器
１０Ｃ、１１０Ｃ 移相回路
１２ ＦＥＴ
１４、１１４ キャパシタ
１６、１１６ 可変抵抗
１８、２０、１１８、１２０ 抵抗
８０ 位相反転回路
８２、１１２ オペアンプ
７０ 帰還抵抗
７４ 入力抵抗[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tuning amplifier that can be easily integrated, and more particularly to a tuning amplifier that can arbitrarily adjust a tuning frequency and a maximum attenuation amount without interfering with each other.
[0002]
[Prior art]
Conventionally, various amplifier circuits using active elements and reactance elements as tuning amplifiers have been proposed and put into practical use.
[0003]
[Problems to be solved by the invention]
In the conventional tuning amplifier, when the tuning frequency is adjusted, the Q and gain depending on the LC circuit are changed, and when the maximum attenuation is adjusted, the tuning frequency is changed. Also, the characteristic curves A and B in FIG. Thus, since the gain at the tuning frequency changes when the maximum attenuation is adjusted, it is extremely difficult to adjust the tuning frequency, the gain at the tuning frequency, and the maximum attenuation C1 and C2 without interfering with each other.
[0004]
Further, it has been difficult to form a tuning amplifier capable of adjusting the tuning frequency and the maximum attenuation amount by an integrated circuit.
[0005]
The present invention has been conceived to solve such problems.
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a tuned amplifier according to claim 1 comprises:
An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting the input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means through the first capacitor and the other AC signal as the first A first phase shift circuit including a synthesis means for synthesis via a resistor;
A differential input amplifier having one end of a second resistor connected to the inverting input terminal; a third resistor connected between the inverting input terminal and the output terminal of the differential input amplifier; A fourth circuit connected to the other end of the resistor and a series circuit composed of a second capacitor, and a connection portion of the fourth resistor and the second capacitor is connected to a non-inverting input terminal of the differential input amplifier. A second phase shift circuit connected to
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. To do.
[0007]
The tuned amplifier of claim 2 comprises:
An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting the input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means through the first inductor and the other AC signal as the first A first phase shift circuit including a synthesis means for synthesis via a resistor;
A differential input amplifier having one end of a second resistor connected to the inverting input terminal; a third resistor connected between the inverting input terminal and the output terminal of the differential input amplifier; A fourth circuit connected to the other end of the resistor and a series circuit including a second inductor, and a connection part of the fourth resistor and the second inductor is connected to a non-inverting input terminal of the differential input amplifier. A second phase shift circuit connected to
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. To do.
[0008]
The tuned amplifier of claim 3 comprises:
An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting an input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means via a capacitor, and the other AC signal via a first resistor A first phase shift circuit including combining means for combining, a differential input amplifier having one end of a second resistor connected to the inverting input terminal, an inverting input terminal and an output terminal of the differential input amplifier, And a series circuit including a fourth resistor and an inductor connected to the other end of the second resistor, and a connection portion of the fourth resistor and the inductor. A second phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. To do.
[0009]
The tuned amplifier of claim 4 comprises:
An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting an input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means via an inductor, and the other AC signal via a first resistor A first phase shift circuit including combining means for combining, a differential input amplifier having one end of a second resistor connected to the inverting input terminal, an inverting input terminal and an output terminal of the differential input amplifier, And a series circuit composed of a fourth resistor and a capacitor connected to the other end of the second resistor, and a connection portion of the fourth resistor and the capacitor. A second phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. To do.
[0010]
The tuned amplifier according to claim 5 is the tuned amplifier according to any one of claims 1 to 4, wherein the first and second phase shift circuits are such that an output voltage is both in a leading phase or both in a lagging phase with respect to an input voltage. The tuning operation is performed at a frequency at which the total phase shift amount of the first and second phase shift circuits is 180 °.
[0011]
A tuning amplifier according to a sixth aspect of the present invention is the tuning amplifier according to any one of the first to fifth aspects, wherein the differential input amplifier is an operational amplifier.
[0012]
According to a seventh aspect of the present invention, in the tuning amplifier according to any one of the first to sixth aspects, each of the input side impedance element and the feedback side impedance element is a resistor.
[0013]
The tuning amplifier according to claim 8 is the tuning amplifier according to claim 7, wherein at least one of the input-side impedance element and the feedback-side impedance element is formed by a variable resistor, and a resistance ratio of the input-side impedance element and the feedback-side impedance element is changed. Thus, the maximum attenuation is changed.
[0014]
A tuning amplifier according to a ninth aspect is characterized in that, in any one of the first to sixth aspects, each of the input side impedance element and the feedback side impedance element is a capacitor.
[0015]
A tuning amplifier according to a tenth aspect is the tuning amplifier according to the ninth aspect, wherein at least one of the input-side impedance element and the feedback-side impedance element is formed by a variable capacitance element, and the capacitance of the input-side impedance element and the feedback-side impedance element. The maximum attenuation is changed by changing the ratio.
[0016]
A tuning amplifier according to an eleventh aspect is the tuning amplifier according to any one of the first to sixth aspects, wherein the first resistor included in the first phase shift circuit and the fourth resistor included in the second phase shift circuit. At least one is formed by a variable resistor, and the tuning frequency is changed by changing the resistance value.
[0017]
A tuned amplifier according to a twelfth aspect is characterized in that, in the eighth or eleventh aspect, the variable resistance is formed by a channel of the FET, and the channel resistance is changed by changing a gate voltage.
[0018]
A tuning amplifier according to a thirteenth aspect is the tuning amplifier according to the eighth or eleventh aspect, wherein the variable resistor is formed by connecting the source and drain of a p-channel type FET and an n-channel type FET in parallel. The channel resistance is changed by changing the size.
[0019]
A tuning amplifier according to a fourteenth aspect is the tuning amplifier according to any one of the first, third, and fourth aspects, wherein the capacitor included in at least one of the first and second phase shift circuits is formed by a variable capacitance element, and the capacitance It is characterized in that the tuning frequency is changed by changing.
[0020]
A tuned amplifier according to claim 15 is characterized in that in claim 10 or 14, the variable capacitance element is formed by a variable capacitance diode whose reverse bias voltage can be changed, or an FET whose gate capacitance can be changed by changing the gate voltage. To do.
[0021]
A tuning amplifier according to a sixteenth aspect is the tuning amplifier according to any one of the second to fourth aspects, wherein the tuning frequency is changed by changing an inductance of the inductor included in at least one of the first and second phase shift circuits. It is characterized by.
[0022]
A tuned amplifier according to a seventeenth aspect is the tuned amplifier according to the sixteenth aspect, wherein the inductor is formed on a semiconductor substrate and has two spiral electrodes magnetically coupled to each other through a magnetic material, The inductance of the other electrode is changed by changing the magnitude of the DC bias current flowing through the other electrode.
[0023]
The tuned amplifier of claim 18 in claim 16,
The inductor is
An inductor conductor formed in a substantially spiral shape on a substrate;
A control conductor formed on the substrate and substantially concentrically with the inductor conductor, through which a predetermined DC bias current flows;
A magnetic body formed to cover the inductor conductor and the control conductor;
And changing the DC bias current flowing through the control conductor to change the inductance appearing at both ends of the inductor conductor.
[0024]
The tuned amplifier according to claim 19 is according to claim 16,
The inductor is
An inductor conductor formed in a substantially spiral shape on a substrate;
A control conductor which is formed in a substantially flat spiral shape at a position adjacent to the inductor conductor on the substrate, and a predetermined DC bias current flows;
A magnetic body formed in an annular shape so as to pass through each of the spiral centers of the inductor conductor and the control conductor;
And changing the DC bias current flowing through the control conductor to change the inductance appearing at both ends of the inductor conductor.
[0025]
A tuned amplifier according to claim 20 is the tuning amplifier according to any one of claims 1 to 6, wherein the first resistor included in the first phase shift circuit and the fourth resistor included in the second phase shift circuit. The tuning frequency is changed by replacing at least one of the resistors with a plurality of resistors whose resistance values are fixed and selectively connecting them by switching.
[0026]
A tuning amplifier according to a twenty-first aspect is the tuning amplifier according to any one of the first, third, and fourth aspects, wherein the capacitor included in at least one of the first and second phase shift circuits is replaced with a plurality of capacitors having fixed capacitances. Instead, the tuning frequency is changed by selective connection by switching.
[0027]
A tuned amplifier according to claim 22 is the switch according to any one of claims 2 to 4, wherein the inductor included in at least one of the first and second phase shift circuits is replaced with a plurality of inductors having fixed inductances. The tuning frequency is changed by selectively connecting by switching.
[0028]
A tuned amplifier according to claim 23 is the amplifier according to any one of claims 1, 3, and 4, wherein the capacitor included in at least one of the first and second phase shift circuits includes an amplifier having a negative gain. By replacing with a capacitor element connected in parallel between the input and output of the amplifier, the capacitance viewed from the input side of the amplifier is actually made larger than the capacitance of the capacitor element.
[0029]
A tuning amplifier according to a twenty-fourth aspect is characterized in that, in the twenty-third aspect, the tuning frequency is changed by changing a gain of the amplifier and changing a capacitance viewed from an input side of the amplifier.
[0030]
A tuned amplifier according to claim 25 is the amplifier according to any one of claims 2 to 4, wherein the inductor included in at least one of the first and second phase shift circuits has a gain set between 0 and 1. The inductance viewed from the input side of the amplifier is actually made larger than the inductance of the inductor element by replacing with an inductor element connected in parallel between the input and output of the amplifier.
[0031]
A tuning amplifier according to a twenty-sixth aspect is the tuning amplifier according to the twenty-fifth aspect, wherein the tuning frequency is changed by changing a gain of the amplifier and changing an inductance viewed from an input side of the amplifier.
[0032]
A tuned amplifier according to claim 27 is formed as a semiconductor integrated circuit according to any one of claims 1 to 26.
[0033]
In the invention according to each of the above-described claims, the amplitude of the input / output signal does not change in each of the first and second phase shift circuits, and only the phase is shifted by a predetermined amount according to the element constant such as the capacitor. The total phase shift amount is 180 ° by the two phase shift circuits as a whole, that is, the tuning operation is performed at a frequency such that the total phase shift amount is 360 ° by the two phase shift circuits and the phase inversion circuit as a whole. Is called.
[0034]
In particular, when the differential input amplifier included in the above-described phase shift circuit is an operational amplifier, the operation of the phase shift circuit can be stabilized.
[0035]
Also, both the input-side impedance element and the feedback-side impedance element are both formed by resistors or capacitors, and by changing at least one element constant, the tuning point is not accompanied by amplitude fluctuation at the tuning point. It is possible to arbitrarily change the maximum attenuation amount in the frequency region away from.
[0036]
Further, by changing each element constant of the capacitor or inductor included in the phase shift circuit or a resistor connected in series with these elements, the amount of phase shift in each phase shift circuit changes. As a whole, the frequency at which the total phase shift amount is 180 °, that is, the tuning frequency can be arbitrarily changed. In particular, when changing the resistance value, the resistance between the source and drain of the FET can be used, and when changing the capacitance of the capacitor, an element such as a variable capacitance diode can be used. Suitable for forming in Furthermore, with respect to the inductor, in the two magnetically coupled electrodes formed on the semiconductor substrate, the inductance of the other electrode can be directly changed by changing the magnitude of the DC bias current flowing to one electrode. This is also suitable for forming a variable inductor on a semiconductor substrate.
[0037]
Further, in order to change the tuning frequency as described above, a plurality of resistors or the like may be selectively used by switching a switch in addition to continuously changing the element constant such as a resistor.
[0038]
In addition, the capacitors and inductors included in the phase shift circuit are apparently large by replacing the capacitor element or a circuit in which the inductor element and the amplifier are connected in parallel, thereby actually increasing the capacitance of the capacitor element and the inductance of the inductor element. Can show. Therefore, in practice, capacitor elements and inductor elements can be formed with a small occupied area, and these capacitances and inductances can be converted into large values, and the occupied area of the semiconductor substrate can be reduced.
[0039]
In addition, any component of the above-described tuning amplifier can be formed on a semiconductor substrate. When integrated in this way, the entire circuit can be reduced in size and the manufacturing cost can be reduced.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a tuning amplifier according to an embodiment to which the present invention is applied will be described in detail with reference to the drawings.
[0041]
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a tuning amplifier according to a first embodiment to which the present invention is applied. The tuning amplifier 1 shown in FIG. 1 includes two phase shift circuits 10C and 110C that each perform a phase shift of 180 ° in total at a predetermined frequency by shifting the phase of an input signal by a predetermined amount, and a phase shift circuit 110C. A phase inverting circuit 80 that inverts the phase of the output signal and amplifies and outputs the signal with a predetermined amplification factor, and a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times that of the feedback resistor 70). And an adder circuit that adds a signal (feedback signal) output from the phase inverting circuit 80 and a signal (input signal) input to the input terminal 90 at a predetermined ratio. It is configured.
[0042]
FIG. 2 shows an extracted configuration of the preceding phase shift circuit 10C shown in FIG. The front phase shift circuit 10C shown in the figure includes an FET 12 whose gate is connected to the input terminal 22 via a capacitor 28, a capacitor 14 and a variable resistor 16 connected in series between the source and drain of the FET 12, The resistor 18 is connected between the drain of the FET 12 and the positive power supply, and the resistor 20 is connected between the source of the FET 12 and the ground.
[0043]
Here, the resistance values of the two resistors 20 and 18 connected to the source and drain of the FET 12 described above are set to be substantially equal, and the phase is matched when focusing on the AC component of the input voltage applied to the input terminal 22. The output signal is output from the source of the FET 12 and the inverted signal is output from the drain of the FET 12.
[0044]
The capacitor 28 inserted between the gate of the FET 12 and the input terminal 22 is for blocking a direct current, and its impedance is extremely small at the operating frequency, that is, has a large capacitance. A resistor 26 connected between the gate of the FET 12 and the ground is for applying an appropriate bias voltage to the FET 12.
[0045]
In the phase shift circuit 10C having such a configuration, when a predetermined AC signal is input to the input terminal 22, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 12, the source of the FET 12 is An AC voltage having the same phase as the input voltage appears, and on the other hand, an AC voltage having the same amplitude as that of the voltage appearing at the source and opposite in phase to the input voltage appears at the drain of the FET 12. The amplitude of the AC voltage appearing at the source and the drain is assumed to be Ei.
[0046]
A series circuit including a variable resistor 16 and a capacitor 14 is connected between the source and drain of the FET 12. Therefore, a signal obtained by synthesizing the voltages appearing at the source and drain of the FET 12 via the capacitor 14 or the variable resistor 16 is output from the output terminal 24.
[0047]
FIG. 3 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10C and the voltage appearing in the capacitor or the like.
[0048]
Since an AC voltage having the same phase and opposite phase as the input voltage and having a voltage amplitude of Ei appears at the source and drain of the FET 12, the potential difference (AC component) between the source and drain becomes 2Ei. Further, the voltage VR1 appearing at both ends of the variable resistor 16 and the voltage VC1 appearing at both ends of the capacitor 14 are out of phase with each other by 90 °, and these are synthesized (added) in vector between the source and drain of the FET 12. Is equal to the potential difference 2Ei.
[0049]
Therefore, as shown in FIG. 3, a right triangle that forms two sides where the voltage VR1 of the variable resistor 16 and the voltage VC1 of the capacitor 14 are orthogonal to each other is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR1 across the variable resistor 16 and the voltage VC1 across the capacitor 14 change along the circumference of the semicircle shown in FIG.
[0050]
If the potential difference between the connection point of the variable resistor 16 and the capacitor 14 and the ground is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where the voltage VC1 intersects, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0051]
As apparent from FIG. 3, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 12 and the voltage VR1 is theoretically the frequency ω. Changes from 90 ° to 0 ° as 0 changes from 0 to ∞. The phase shift amount φ1 of the entire phase shift circuit 10C is twice that and changes from 180 ° to 0 ° according to the frequency. In addition, the phase shift amount φ1 can be changed by varying the resistance value R of the variable resistor 16.
[0052]
FIG. 4 shows an extracted configuration of the subsequent phase shift circuit 110C shown in FIG. The subsequent phase shift circuit 110C shown in the figure shifts the phase of the signal input to the input terminal 122 by a predetermined amount and inputs it to the non-inverting input terminal of the operational amplifier 112, which is a kind of differential input amplifier. A capacitor 114 and a variable resistor 116, a resistor 118 inserted between the input terminal 122 and the inverting input terminal of the operational amplifier 112, and a resistor 120 inserted between the output terminal 124 of the operational amplifier 112 and the inverting input terminal. It is configured to include.
[0053]
In the phase shift circuit 110 </ b> C having such a configuration, when a predetermined AC signal is input to the input terminal 122, the voltage VR <b> 2 that appears across the variable resistor 116 is applied to the non-inverting input terminal of the operational amplifier 112.
[0054]
Further, since there is no potential difference between the two inputs (inverted input terminal and non-inverted input terminal) of the operational amplifier 112 shown in FIG. 4, the potential of the inverted input terminal of the operational amplifier 112 and the connection point between the capacitor 114 and the variable resistor 116. Is equal to the potential. Therefore, the same voltage VC2 as the voltage VC2 appearing across the capacitor 114 appears across the resistor 118.
[0055]
Here, when the resistance values of the resistor 118 and the resistor 120 are equal, the same current flows through the two resistors 118 and 120, so that the voltage VC 2 appears at both ends of the resistor 120. In addition, the voltage VC2 appearing at both ends of the two resistors 118 and 120 is vector-oriented in the same direction, and the voltage VC2 across the resistor 118 is considered based on the inverting input terminal (voltage VR2) of the operational amplifier 112. Is added to the input voltage Ei ', and the output voltage Eo is obtained by subtracting the voltage C2 across the resistor 120 in vector.
[0056]
FIG. 5 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit 110C and the voltage appearing in the capacitor or the like.
[0057]
As shown in the figure, the voltage VR2 appearing at both ends of the variable resistor 116 and the voltage VC2 appearing at both ends of the capacitor 114 are 90 ° out of phase with each other, and the vector addition of these is the input voltage Ei ′. Become. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VR2 of the variable resistor 116 and the both-ends voltage VC2 of the capacitor 114 change along the circumference of the semicircle shown in FIG.
[0058]
As described above, the output voltage Eo is obtained by subtracting the voltage VC2 from the voltage VR2 in a vector manner. Considering the voltage VR2 applied to the non-inverting input terminal as a reference, the input voltage Ei ′ and the output voltage Eo differ only in the direction of synthesizing the voltage VC2, and their absolute values are equal. Therefore, the relationship between the magnitude of the input / output voltage and the phase can be expressed by an isosceles square with the input voltage Ei ′ and the output voltage Eo as the hypotenuse and the base of twice the voltage VC2, and the amplitude of the output signal is represented by the frequency. Regardless of the amplitude of the input signal, it can be seen that the phase shift amount is represented by φ2 shown in FIG.
[0059]
Further, as apparent from FIG. 5, since the voltage VR2 and the voltage VC2 intersect at right angles on the circumference, the phase difference between the input voltage Ei ′ and the voltage VR2 theoretically has a frequency ω from 0 to ∞. It changes from 90 ° to 0 ° as it changes. The shift amount φ2 of the entire phase shift circuit 110C is twice that, and changes from 180 ° to 0 ° depending on the frequency. In addition, the phase shift amount φ2 can be changed by varying the resistance value R of the variable resistor 116.
[0060]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10C and 110C. Moreover, as shown in FIGS. 3 and 5, the relative phase relationship of the input voltages in the respective phase shift circuits 10C and 110C is the same direction, and the two phase shift circuits 10C and 110C as a whole at a predetermined frequency. A signal with a phase shift amount of 180 ° is output.
[0061]
1 includes an operational amplifier 82 in which an input signal is input to an inverting input terminal via a resistor 84 and a non-inverting input terminal is grounded, and an inverting input terminal and an output of the operational amplifier 82. And a resistor 86 connected between the terminals. When an AC signal is input to the inverting input terminal of the operational amplifier 82 via the resistor 84, a reversed-phase signal whose phase is reversed is output from the output terminal of the operational amplifier 82. This reversed-phase signal is shown in FIG. It is taken out from the output terminal 92 of the tuning amplifier 1.
[0062]
The output of the phase inverting circuit 80 is fed back to the input side of the previous phase shift circuit 10C through the feedback resistor 70, and the fed back signal and the signal input through the input resistor 74 are connected. The added voltage is applied to the input terminal (input terminal 22 shown in FIG. 2) of the preceding phase shift circuit 10C.
[0063]
Further, the amplification degree of the phase inverting circuit 80 described above is determined by the resistance ratio of the resistors 84 and 86, and by adjusting this resistance ratio, the loop gain of the tuning amplifier 1 having the configuration shown in FIG. Yes. In other words, the loop gain can be set to approximately 1 by actually compensating for the amount of attenuation of the signal amplitude caused by passing through the preceding phase shift circuit 10C with the phase inversion circuit 80.
[0064]
FIG. 6 is a system diagram in which the entire two phase shift circuits 10C and 110C having the above-described configuration and the phase inversion circuit 80 are replaced with a circuit having a transfer function K1, and a resistor R0 is connected in parallel with the circuit having the transfer function K1. Is connected to an input resistor 74 having a resistance value (nR0) that is n times that of the feedback resistor 70 in series. FIG. 7 is a system diagram in which the system shown in FIG. 6 is converted by Miller's theorem, and the transfer function A of the entire system after conversion is
[Expression 1]

Can be expressed as
[0065]
By the way, the transfer function K2 of the phase shift circuit 10C in the previous stage is such that the resistance value of the variable resistor 16 is R, the capacitance of the capacitor 14 is C, and the time constant of the CR circuit comprising the variable resistor 16 and the capacitor 14 is T. ₁ Then,
[Expression 2]

It becomes. Here, k is the attenuation ratio of the input / output signal and takes a value of 1 or less.
[0066]
Further, the transfer function K3 of the phase-shift circuit 110C at the subsequent stage is such that the resistance value of the variable resistor 116 is R, the capacitance of the capacitor 114 is C, and the time constant of the CR circuit composed of the variable resistor 116 and the capacitor 114 is T. ₂ Then,
[Equation 3]

It becomes. Therefore, the overall transfer function K1 when the phase shift circuits 10C and 110C and the phase inversion circuit 80 with a gain (−1 / k) are connected is
[Expression 4]

It becomes. In order to simplify the calculation, the time constant T of each phase shift circuit ₁ , T ₂ Both are T. Substituting this equation (4) into the above equation (1),
[Equation 5]

It becomes.
[0067]
According to the equation (5), it can be seen that when ω = 0 (DC region), A = −1 / (2n + 1), and the maximum attenuation is given. It can also be seen that the maximum attenuation is given when ω = ∞. Further, the tuning point of ω = 1 / T (when the time constants of the phase shift circuits are different, ω = 1 / √ (T ₁ ・ T ₂ It can be seen that A = 1 at the tuning point)) and is independent of the resistance ratio n of the feedback resistor 70 and the input resistor 74. In other words, as shown in FIG. 8, even if the value of n is changed, the tuning point is not shifted and the attenuation at the tuning point is not changed.
[0068]
Thus, according to the tuning amplifier 1 of this embodiment, even if the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, the tuning frequency and the gain at the time of tuning are constant, and only the maximum attenuation is changed. Can do. On the contrary, since the maximum attenuation is determined by the resistance ratio n described above, even when the tuning frequency is changed by changing the resistance value of the variable resistor 16 or 116 in each of the phase shift circuits 10C and 110C, The maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0069]
In addition, the tuning amplifier 1 of the first embodiment is configured by combining FETs, operational amplifiers, capacitors, and resistors, and any component can be formed on a semiconductor substrate, so that the tuning frequency and the maximum attenuation can be increased. It is easy to form an integrated circuit by forming the entire tuning amplifier 1 that can be adjusted on a semiconductor substrate.
[0070]
By the way, in the tuning amplifier of the first embodiment described above, each of the two phase shift circuits 10C and 110C includes the capacitor 14 or 114, but an inductor can be used instead of the capacitor.
[0071]
FIG. 9 is a diagram showing a modified example of the previous phase shift circuit 10C, and shows the configuration of the phase shift circuit 10L in which an LR circuit is connected between the source and drain of the FET. The phase shift circuit 10L shown in the figure has a configuration in which the CR circuit composed of the variable resistor 16 and the capacitor 14 in the phase shift circuit 10C shown in FIG. 2 is replaced with an LR circuit composed of the inductor 17 and the variable resistor 16. ing. As shown in FIG. 9, one end of the variable resistor 16 is connected to the source of the FET 12, and one end of the inductor 17 is connected to the drain of the FET 12 through a DC current blocking capacitor 19.
[0072]
Therefore, a signal obtained by synthesizing each of the voltages appearing at the source and drain of the FET 12 via the variable resistor 16 or the inductor 17 is output from the output terminal 24.
[0073]
FIG. 10 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10L and the voltage appearing in the inductor or the like.
[0074]
As described with respect to the phase shift circuit 10C, since an AC voltage having the same voltage amplitude and Ei as the input voltage appears at the source and drain of the FET 12, respectively, the potential difference (AC component) between the source and drain is 2Ei. In addition, the voltage VL1 appearing at both ends of the inductor 17 and the voltage VR3 appearing at both ends of the variable resistor 16 are out of phase with each other by 90 °. Is equal to the potential difference 2Ei.
[0075]
Therefore, as shown in FIG. 10, a right-angled triangle that forms two sides where the voltage VL1 across the inductor 17 and the voltage VR3 across the variable resistor 16 are orthogonal is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VL1 of the inductor 17 and the both-ends voltage VR3 of the variable resistor 16 change along the circumference of the semicircle shown in FIG.
[0076]
If the potential difference between the connection point of the inductor 17 and the variable resistor 16 and the ground is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where the voltage VR3 intersects, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0077]
Further, as apparent from FIG. 10, since the voltage VL1 and the voltage VR3 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 12 and the voltage VL1 is theoretically the frequency ω. Changes from 90 ° to 0 ° as 0 changes from 0 to ∞. The phase shift amount φ1 of the entire phase shift circuit 10L is twice that, and changes from 180 ° to 0 ° according to the frequency. In addition, the phase shift amount φ1 can be changed by varying the resistance value R of the variable resistor 16.
[0078]
Note that the transfer function of the phase shift circuit 10L is such that the resistance value of the variable resistor 16 is R, the inductance of the inductor 17 is L, and the time constant of the LR circuit composed of the variable resistor 16 and the inductor 17 is T. ₁ If (= L / R), it can be expressed by the above-described equation (2). That is, when expressed using a time constant, it can be seen that the phase shift circuit 10C shown in FIG. 2 is equivalent to the phase shift circuit 10L shown in FIG.
[0079]
Accordingly, in FIG. 1, a tuned amplifier can be configured by replacing the preceding phase shift circuit 10C with the phase shift circuit 10L shown in FIG. 9, and even in this case, the maximum attenuation is not affected. The tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0080]
In particular, when the preceding phase shift circuit 10C is replaced with the phase shift circuit 10L shown in FIG. 9, the time constant T of the LR circuit in the previous phase shift circuit 10L is L / R, and the subsequent phase shift circuit Since the time constant T of the CR circuit in 110C is CR and the resistance value R is divided into a denominator and a numerator in each of them, for example, the entire tuning amplifier is formed on a semiconductor substrate and each variable resistor is formed by an FET. In such a case, so-called temperature compensation is possible, in which fluctuations in the tuning frequency with respect to temperature changes in the resistance values of the variable resistors are suppressed. The same applies to the case where various tuning amplifiers described later are configured by combining a phase shift circuit including a CR circuit and a phase shift circuit including an LR circuit.
[0081]
FIG. 11 is a diagram illustrating a modified example of the subsequent phase shift circuit 110C, and shows a configuration of the phase shift circuit 110L in which an LR circuit is connected to the input side of the operational amplifier. The phase shift circuit 110L shown in the figure has a configuration in which the CR circuit composed of the variable resistor 116 and the capacitor 114 in the phase shift circuit 110C shown in FIG. 4 is replaced with an LR circuit composed of the inductor 117 and the variable resistor 116. ing. As shown in FIG. 11, one end of the variable resistor 116 is connected to the input end 122, and the connection point between the variable resistor 116 and the inductor 117 is connected to the non-inverting input terminal of the operational amplifier 112.
[0082]
FIG. 12 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 110L and the voltage appearing in the inductor or the like.
[0083]
As shown in the figure, the voltage VL2 appearing at both ends of the inductor 117 and the voltage VR4 appearing at both ends of the variable resistor 116 are 90 ° out of phase with each other. Become. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VL2 of the inductor 117 and the both-ends voltage VR4 of the variable resistor 116 change along the circumference of the semicircle shown in FIG.
[0084]
As described above, the output voltage Eo is obtained by subtracting the voltage VR4 from the voltage VL2 in a vector manner. Considering the voltage VL2 applied to the non-inverting input terminal as a reference, the input voltage Ei 'and the output voltage Eo differ only in the direction in which the voltage VR4 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and phase of the input / output voltage can be represented by an isosceles triangle with the input voltage Ei ′ and the output voltage Eo as the hypotenuse and the base of twice the voltage VR4, and the amplitude of the output signal depends on the frequency. Regardless of the amplitude of the input signal, it can be seen that the phase shift amount is represented by φ2 shown in FIG.
[0085]
Further, as apparent from FIG. 12, since the voltage VL2 and the voltage VR4 intersect at right angles on the circumference, the phase difference between the input voltage Ei ′ and the voltage VL2 theoretically has a frequency ω from 0 to ∞. It changes from 90 ° to 0 ° as it changes. The shift amount φ2 of the entire phase shift circuit 110L is twice that, and changes from 180 ° to 0 ° depending on the frequency. In addition, the phase shift amount φ2 can be changed by varying the resistance value R of the variable resistor 116.
[0086]
Note that the transfer function of the phase shift circuit 110L is that the resistance value of the variable resistor 116 is R, the inductance of the inductor 117 is L, and the time constant of the LR circuit composed of the variable resistor 116 and the inductor 117 is T. ₂ If (= L / R), it can be expressed by the above-described equation (3). That is, when expressed using a time constant, it can be seen that the phase shift circuit 110C shown in FIG. 4 is equivalent to the phase shift circuit 110L shown in FIG.
[0087]
Therefore, in FIG. 1, it is possible to configure a tuning amplifier by replacing the subsequent phase shift circuit 110C with the phase shift circuit 110L shown in FIG. 11, and even in this case, the maximum attenuation is not affected. The tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0088]
In FIG. 1, the preceding phase shift circuit 10C may be replaced with the phase shift circuit 10L shown in FIG. 9, and the subsequent phase shift circuit 110C may be replaced with the phase shift circuit 110L shown in FIG. it can. In particular, when the two phase shift circuits constituting the tuning amplifier are both configured to include the LR circuit, when the tuning amplifier is formed as an integrated circuit, the inductance of the inductor included in each phase shift circuit is reduced and the frequency ω ( = R / L) can be easily increased, and is suitable for increasing the tuning frequency.
[0089]
Further, in the various tuning amplifiers described above, the phase shift circuit 10C or 10L is disposed in the previous stage and the phase shift circuit 110C or 110L is disposed in the subsequent stage, respectively, and the phase shift amount between the input and output signals is 180 ° as a whole. Therefore, the phase amplifier 110C or 110L may be replaced in the preceding stage and the phase shift circuit 10C or 10L may be disposed in the subsequent stage to configure the tuning amplifier.
[0090]
(Second Embodiment)
FIG. 13 is a circuit diagram showing a configuration of a tuning amplifier according to the second embodiment to which the present invention is applied. The tuning amplifier 2 shown in FIG. 2 includes two phase shift circuits 30C and 130C that respectively shift the phase of the input signal by a predetermined amount to shift the phase by 180 ° in total at a predetermined frequency, and the phase shift circuit 130C. A phase inverting circuit 80 that inverts the phase of the output signal and amplifies and outputs the signal with a predetermined amplification factor, and a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times that of the feedback resistor 70). And an adder circuit that adds a signal (feedback signal) output from the phase inverting circuit 80 and a signal (input signal) input to the input terminal 90 at a predetermined ratio. It is configured.
[0091]
FIG. 14 shows an extracted configuration of the previous phase shift circuit 30C shown in FIG. The phase-shift circuit 30C in the preceding stage shown in the figure includes an FET 32 whose gate is connected to the input terminal 42 via a capacitor 48, a variable resistor 36 and a capacitor 34 connected in series between the source and drain of the FET 32, The resistor 38 is connected between the drain of the FET 32 and the positive power supply, and the resistor 40 is connected between the source of the FET 32 and the ground.
[0092]
Here, the resistance values of the two resistors 40 and 38 connected to the source and drain of the FET 32 described above are set to be approximately equal, and the phase is matched when focusing on the AC component of the input voltage applied to the input terminal 42. The output signal is output from the source of the FET 32 and the inverted signal is output from the drain of the FET 32.
[0093]
The capacitor 48 inserted between the gate of the FET 32 and the input terminal 42 is for blocking a direct current, and its impedance is extremely small at the operating frequency, that is, has a large capacitance. A resistor 46 connected between the gate of the FET 32 and the ground is for applying an appropriate bias voltage to the FET 32.
[0094]
In the phase shift circuit 30C having such a configuration, when a predetermined AC signal is input to the input terminal 42, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 32, the source of the FET 32 is An AC voltage having the same phase as the input voltage appears. On the other hand, an AC voltage having the same amplitude as that of the voltage appearing at the source and opposite in phase to the input voltage appears at the drain of the FET 32. The amplitude of the AC voltage appearing at the source and the drain is assumed to be Ei.
[0095]
A series circuit including a capacitor 34 and a variable resistor 36 is connected between the source and drain of the FET 32. Therefore, a signal obtained by synthesizing the voltages appearing at the source and drain of the FET 32 via the variable resistor 36 or the capacitor 34 is output from the output terminal 44.
[0096]
FIG. 15 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30C and the voltage appearing in the capacitor or the like.
[0097]
Since an AC voltage having the same phase and opposite phase to the input voltage and having a voltage amplitude of Ei appears at the source and drain of the FET 32, the potential difference (AC component) between the source and drain becomes 2Ei. Further, the voltage VC3 appearing at both ends of the capacitor 34 and the voltage VR5 appearing at both ends of the variable resistor 36 are out of phase with each other by 90 °, and these are combined (added) in a vector manner between the source and drain of the FET 32. Is equal to the potential difference 2Ei.
[0098]
Therefore, as shown in FIG. 15, a right-angled triangle that forms two sides in which the voltage VC3 across the capacitor 34 and the voltage VR5 across the variable resistor 36 are orthogonal to each other has twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC3 across the capacitor 34 and the voltage VR5 across the variable resistor 36 change along the circumference of the semicircle shown in FIG.
[0099]
If the potential difference between the connection point of the variable resistor 36 and the capacitor 34 and the ground is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be expressed as a vector whose end point is one point on the circumference where the voltage VR5 intersects, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0100]
Further, as apparent from FIG. 15, since the voltage VC3 and the voltage VR5 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VC3 is theoretically the frequency ω. As 0 changes from 0 to ∞, it changes from 0 ° to 90 °. The phase shift amount φ3 of the entire phase shift circuit 30C is twice that and changes from 0 ° to 180 ° depending on the frequency. In addition, the phase shift amount φ3 can be changed by varying the resistance value R of the variable resistor 36.
[0101]
FIG. 16 shows an extracted configuration of the subsequent phase shift circuit 130C shown in FIG. The latter-stage phase shift circuit 130C shown in the figure shifts the phase of the signal input to the input terminal 142 by a predetermined amount and inputs it to the non-inverting input terminal of the operational amplifier 132 as a kind of differential input amplifier. A variable resistor 136 and a capacitor 134, a resistor 138 inserted between the input terminal 142 and the inverting input terminal of the operational amplifier 132, and a resistor 140 inserted between the output terminal 144 of the operational amplifier 132 and the inverting input terminal. It is configured to include.
[0102]
In the phase shift circuit 130 </ b> C having such a configuration, when a predetermined AC signal is input to the input terminal 142, the voltage VC <b> 4 that appears across the capacitor 134 is applied to the non-inverting input terminal of the operational amplifier 132.
[0103]
Further, since there is no potential difference between the two inputs (inverted input terminal and non-inverted input terminal) of the operational amplifier 132 shown in FIG. 16, the potential of the inverted input terminal of the operational amplifier 132 and the connection point between the variable resistor 136 and the capacitor 134 are obtained. Is equal to the potential. Accordingly, the same voltage VR6 appears at both ends of the resistor 138 as the voltage VR6 that appears at both ends of the variable resistor 136.
[0104]
Here, when the resistance values of the resistor 138 and the resistor 140 are equal, the same current flows through the two resistors 138 and 140, so that the voltage VR 6 appears at both ends of the resistor 140. Moreover, the voltage VR6 appearing at both ends of the two resistors 138 and 140 is vector-oriented in the same direction, and the voltage VR6 across the resistor 138 is considered based on the inverting input terminal (voltage VC4) of the operational amplifier 132. Is added to the input voltage Ei ', and the output voltage Eo is obtained by subtracting the voltage R6 across the resistor 140 in vector.
[0105]
FIG. 17 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit 130C and the voltage appearing in the capacitor or the like.
[0106]
As shown in the figure, the voltage VC4 appearing at both ends of the capacitor 134 and the voltage VR6 appearing at both ends of the variable resistor 136 are 90 ° out of phase with each other, and the vector addition of these is the input voltage Ei ′. Become. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC4 across the capacitor 134 and the voltage VR6 across the variable resistor 136 change along the circumference of the semicircle shown in FIG.
[0107]
As described above, the output voltage Eo is obtained by subtracting the voltage VR6 from the voltage VC4 in a vector manner. Considering the voltage VC4 applied to the non-inverting input terminal as a reference, the input voltage Ei ′ and the output voltage Eo differ only in the direction in which the voltage VR6 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and the phase of the input / output voltage can be expressed by an isosceles square with the input voltage Ei ′ and the output voltage Eo as the hypotenuse and twice the voltage VR6 as the base, and the amplitude of the output signal depends on the frequency. Regardless of the amplitude of the input signal, it can be seen that the phase shift amount is represented by φ4 shown in FIG.
[0108]
Further, as apparent from FIG. 17, since the voltage VC4 and the voltage VR6 intersect at right angles on the circumference, the phase difference between the input voltage Ei ′ and the voltage VC4 is theoretically from 0 to ∞. It changes from 0 ° to 90 ° as it changes. The shift amount φ4 of the entire phase shift circuit 130C is twice that, and changes from 0 ° to 180 ° depending on the frequency. In addition, the phase shift amount φ4 can be changed by varying the resistance value R of the variable resistor 136.
[0109]
In this way, the phase is shifted by a predetermined amount in each of the two phase shift circuits 30C and 130C. Moreover, as shown in FIGS. 15 and 17, the relative phase relationship between the input and output voltages in the phase shift circuits 30C and 130C is the same direction, and the entire two phase shift circuits 30C and 130C at a predetermined frequency. Thus, a signal with a phase shift amount of 180 ° is output.
[0110]
The phase inverting circuit 80 shown in FIG. 13 is the same as that shown in FIG. 1 and functions as an amplifier circuit having an amplification degree determined by the resistance ratio of the resistors 84 and 86, and also outputs the signal by inverting the phase of the input signal. To do.
[0111]
The output of the phase inverting circuit 80 is taken out from the output terminal 92 as the output of the tuning amplifier 2 and is fed back to the input side of the previous phase shift circuit 30C via the feedback resistor 70. The signal input through the input resistor 74 is added, and the added voltage is applied to the input terminal (the input terminal 42 shown in FIG. 14) of the phase shift circuit 30C.
[0112]
Further, by adjusting the amplification degree of the phase inverting circuit 80 described above, the loop gain of the tuning amplifier 2 having the configuration shown in FIG. In other words, in practice, the phase inversion circuit 80 compensates for the amount of attenuation of the signal amplitude caused by passing through the preceding phase shift circuit 30C, so that the loop gain can be set to approximately 1.
[0113]
By the way, the transfer function K21 of the preceding phase shift circuit 30C has the resistance value of the variable resistor 36 as R, the capacitance of the capacitor 34 as C, and the time constant of the CR circuit composed of these variable resistor 36 and capacitor 34 as T. ₁ Then,
[Formula 6]

It becomes. Here, k is the attenuation ratio of the input / output signal and takes a value of 1 or less.
[0114]
Further, the transfer function K31 of the subsequent phase shift circuit 130C has the resistance value of the variable resistor 136 as R, the capacitance of the capacitor 134 as C, and the time constant of the CR circuit composed of these variable resistor 136 and capacitor 134 as T. ₂ Then,
[Expression 7]

It becomes. Therefore, the total transfer function K11 when the phase shift circuits 30C and 130C and the phase inversion circuit 80 having a gain (−1 / k) are connected is as follows.
[Equation 8]

This is the same as the equation (4) calculated for the tuning amplifier 1 of the first embodiment. That is, A shown in the equation (5) can be applied as it is to the transfer function of the entire tuning amplifier 2 of the second embodiment.
[0115]
Therefore, it can be seen that when ω = 0 (DC region), A = −1 / (2n + 1), which gives the maximum attenuation. It can also be seen that the maximum attenuation is given when ω = ∞. Further, the tuning point of ω = 1 / T (when the time constants of the phase shift circuits are different, ω = 1 / √ (T ₁ ・ T ₂ It can be seen that A = 1 at the tuning point)) and is independent of the resistance ratio n of the feedback resistor 70 and the input resistor 74. In other words, as shown in FIG. 8, even if the value of n is changed, the tuning point is not shifted and the attenuation at the tuning point is not changed.
[0116]
Thus, according to the tuning amplifier 2 of this embodiment, even if the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, the tuning frequency and the gain at the time of tuning are constant, and only the maximum attenuation is changed. Can do. On the contrary, since the maximum attenuation is determined by the resistance ratio n described above, even when the tuning frequency is changed by changing the resistance value of the variable resistor 36 or 136 in each of the phase shift circuits 30C and 130C, The maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0117]
In addition, the tuning amplifier 2 of the second embodiment is configured by combining FETs, operational amplifiers, capacitors, and resistors, and any component can be formed on a semiconductor substrate. Therefore, the tuning frequency and the maximum attenuation can be increased. It is easy to form an integrated circuit by forming the entire tuning amplifier 2 that can be adjusted on a semiconductor substrate.
[0118]
Incidentally, in the tuning amplifier 2 of the second embodiment described above, each of the two phase shift circuits 30C and 130C includes the capacitor 34 or 134, but an inductor may be used instead of the capacitor.
[0119]
FIG. 18 is a diagram showing a modified example of the previous phase shift circuit 30C, and shows the configuration of the phase shift circuit 30L in which an LR circuit is connected between the source and drain of the FET. The phase shift circuit 30L shown in the figure has a configuration in which the CR circuit composed of the capacitor 34 and the variable resistor 36 in the phase shift circuit 30C shown in FIG. 14 is replaced with an LR circuit composed of the variable resistor 36 and the inductor 37. ing. As shown in FIG. 18, one end of the inductor 37 is connected to the source of the FET 32 via the DC blocking capacitor 39, and one end of the variable resistor 36 is connected to the drain of the FET 32.
[0120]
Therefore, a signal obtained by synthesizing each of the voltages appearing at the source and drain of the FET 32 via the inductor 37 or the variable resistor 36 is output from the output terminal 44.
[0121]
FIG. 19 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 30L and the voltage appearing in the inductor or the like.
[0122]
As described with respect to the phase shift circuit 30C, an AC voltage having the same phase and opposite phase as the input voltage and having a voltage amplitude of Ei appears at the source and drain of the FET 32, so that the potential difference (AC component) between the source and drain is 2Ei. Further, the voltage VR7 appearing at both ends of the variable resistor 36 and the voltage VL3 appearing at both ends of the inductor 37 are out of phase with each other by 90 °, and these are combined (added) in a vector manner between the source and drain of the FET 32. Is equal to the potential difference 2Ei.
[0123]
Accordingly, as shown in FIG. 19, a right triangle that forms two sides where the voltage VR7 of the variable resistor 36 and the voltage VL3 of the inductor 37 are orthogonal is formed with twice the voltage Ei as the hypotenuse. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VR7 of the variable resistor 36 and the both-ends voltage VL3 of the inductor 37 change along the circumference of the semicircle shown in FIG.
[0124]
If the potential difference between the connection point of the variable resistor 36 and the inductor 37 and the ground is taken out as the output voltage Eo, the output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector whose end point is one point on the circumference where the voltage VL3 intersects, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
[0125]
Further, as apparent from FIG. 19, since the voltage VR7 and the voltage VL3 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 32 and the voltage VR7 is theoretically the frequency ω. As 0 changes from 0 to ∞, it changes from 0 ° to 90 °. The phase shift amount φ3 of the entire phase shift circuit 30L is twice that, and varies from 0 ° to 180 ° depending on the frequency. In addition, the phase shift amount φ3 can be changed by varying the resistance value R of the variable resistor 36.
[0126]
The transfer function of the phase shift circuit 30L is such that the resistance value of the variable resistor 36 is R, the inductance of the inductor 37 is L, and the time constant of the LR circuit composed of the variable resistor 36 and the inductor 37 is T. ₁ If (= L / R), it can be expressed by the above-described equation (6). That is, when expressed using a time constant, it can be seen that the phase shift circuit 30C shown in FIG. 14 is equivalent to the phase shift circuit 30L shown in FIG.
[0127]
Therefore, in FIG. 13, the phase-shift circuit 30C in the previous stage can be replaced with the phase-shift circuit 30L shown in FIG. 18, so that a tuning amplifier can be configured. Even in this case, the maximum attenuation is not affected. The tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0128]
FIG. 20 is a diagram showing a modified example of the latter-stage phase shift circuit 130C, and shows the configuration of the phase shift circuit 130L in which an LR circuit is connected to the input side of the operational amplifier. The phase shift circuit 130L shown in the figure has a configuration in which the CR circuit formed of the variable resistor 136 and the capacitor 134 in the phase shift circuit 130C shown in FIG. 16 is replaced with an LR circuit formed of the inductor 137 and the variable resistor 136. ing. As shown in FIG. 20, one end of the inductor 137 is connected to the input terminal 142, and the connection point between the inductor 137 and the variable resistor 136 is connected to the non-inverting input terminal of the operational amplifier 132.
[0129]
FIG. 21 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 130L and the voltage appearing in the inductor or the like.
[0130]
As shown in the figure, the voltage VR8 appearing at both ends of the variable resistor 136 and the voltage VL4 appearing at both ends of the inductor 137 are out of phase with each other by 90 °, and these are added in vector to obtain the input voltage Ei ′. Become. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-ends voltage VR8 of the variable resistor 136 and the both-ends voltage VL4 of the inductor 137 change along the circumference of the semicircle shown in FIG.
[0131]
As described above, the output voltage Eo is obtained by subtracting the voltage VL4 from the voltage VR8 in a vector manner. Considering the voltage VR8 applied to the non-inverting input terminal as a reference, the input voltage Ei 'and the output voltage Eo differ only in the direction in which the voltage VL4 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and phase of the input / output voltage can be represented by an isosceles triangle with the input voltage Ei ′ and the output voltage Eo as the hypotenuse and the base of twice the voltage VL4. Regardless of the amplitude of the input signal, it can be seen that the phase shift amount is represented by φ4 shown in FIG.
[0132]
Further, as apparent from FIG. 21, since the voltage VR8 and the voltage VL4 intersect at a right angle on the circumference, the phase difference between the input voltage Ei ′ and the voltage VR8 theoretically has a frequency ω from 0 to ∞. It changes from 0 ° to 90 ° as it changes. The shift amount φ4 of the entire phase shift circuit 130L is twice that, and changes from 0 ° to 180 ° depending on the frequency. In addition, the phase shift amount φ4 can be changed by varying the resistance value R of the variable resistor 136.
[0133]
The transfer function of the phase shift circuit 130L is such that the resistance value of the variable resistor 136 is R, the inductance of the inductor 137 is L, and the time constant of the LR circuit composed of the variable resistor 136 and the inductor 137 is T31 (= L / R). Then, it can be expressed by the above-described equation (7). That is, when expressed using a time constant, it can be seen that the phase shift circuit 130C shown in FIG. 16 and the phase shift circuit 130L shown in FIG. 20 are equivalent.
[0134]
Therefore, in FIG. 13, the phase-shift circuit 130C in the subsequent stage can be replaced with the phase-shift circuit 130L shown in FIG. 20, and a tuning amplifier can be configured. Even in this case, the maximum attenuation is not affected. The tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.
[0135]
In FIG. 13, the phase-shift circuit 30C in the previous stage is replaced with the phase-shift circuit 30L shown in FIG. 18, and the phase-shift circuit 130C in the subsequent stage is replaced with the phase-shift circuit 130L shown in FIG. it can.
[0136]
Further, in the various tuning amplifiers described above, the phase shift circuit 30C or 30L is arranged at the front stage and the phase shift circuit 130C or 130L is arranged at the rear stage, respectively, and the phase shift amount between the input and output signals is 180 ° as a whole. Therefore, the tuned amplifier may be configured by switching these before and after and arranging the phase shift circuit 130C or 130L in the previous stage and the phase shift circuit 30C or 30L in the subsequent stage.
[0137]
(Other embodiments)
By the way, the tuning amplifier of each embodiment described above is configured by two phase shift circuits and a phase inversion circuit, and the total phase shift amount is set to 0 ° at a predetermined frequency by the entire three connected circuits. Thus, a predetermined tuning operation is performed. Therefore, focusing only on the phase shift amount, there is a certain degree of freedom in the order in which the phase shift circuit and the phase inversion circuit are connected, and the connection order can be determined as necessary.
[0138]
FIG. 22 is a diagram illustrating a connection state in the case where a tuning amplifier is configured by combining two phase shift circuits and a phase inversion circuit. In these figures, the feedback-side impedance element 70a and the input-side impedance element 74a are for adding the output signals and input signals of the respective tuning amplifiers at a predetermined ratio, and are most commonly shown in FIG. As shown, the feedback resistor 70 is used as the feedback impedance element 70a, and the input resistor 74 is used as the input impedance element 74a.
[0139]
However, since the feedback side impedance element 70a and the input side impedance element 74a need only be added without changing the phase relationship of the signals input to the respective elements, both the feedback side impedance element 70a and the input side impedance element 74a are capacitors. Alternatively, both the feedback side impedance element 70a and the input side impedance element 74a may be formed by inductors. Alternatively, each impedance element may be formed by combining resistors, capacitors, or inductors so that the ratio of the real number and the imaginary number of impedances can be adjusted simultaneously.
[0140]
FIG. 22A shows a configuration in which a phase inverting circuit 80 is arranged after the two phase shift circuits, and corresponds to the tuning amplifier 1 shown in FIG. 1 or the tuning amplifier 2 shown in FIG. Yes. As described above, when the phase inverting circuit 80 is disposed in the subsequent stage, a large output current can be extracted by providing the phase inverting circuit 80 with the function of an output buffer.
[0141]
FIG. 22B shows a configuration in which a phase inversion circuit 80 is disposed between two phase shift circuits. In this way, when the phase inverting circuit 80 is arranged in the middle, mutual interference between the preceding phase shift circuit and the subsequent phase shift circuit can be completely prevented.
[0142]
FIG. 22C shows a configuration in which a phase inverting circuit 80 is arranged further upstream of the two phase shift circuits. As described above, when the phase inverting circuit 80 is arranged in the preceding stage, the influence of the feedback side impedance element 70a and the input side impedance element 74a on the preceding phase shift circuit can be minimized.
[0143]
The phase shift circuit shown in each embodiment described above includes a variable resistor 16 and the like. Specifically, these variable resistors can be realized by using junction type or MOS type FETs.
[0144]
FIG. 23 is a diagram showing a configuration of the phase shift circuit when the variable resistors in the two types of phase shift circuits constituting the tuning amplifier 1 shown in FIG. 1 are replaced with FETs. FIG. 2A shows a configuration in which the variable resistor 16 is replaced with an FET in the phase shift circuit 10C. FIG. 5B shows a configuration in which the variable resistor 116 is replaced with an FET in the phase shift circuit 110C.
[0145]
As described above, when the channel formed between the source and drain of the FET is used as a resistor instead of the variable resistor 16 or 116, the gate voltage is variably controlled to arbitrarily control the channel resistance within a certain range. By changing the phase shift amount, the phase shift amount in each phase shift circuit can be changed. Therefore, since the frequency at which the phase shift amount of the signal that makes a round in each tuning amplifier becomes 0 ° can be changed, the tuning frequency of the tuning amplifier can be arbitrarily changed.
[0146]
In each of the phase shift circuits shown in FIG. 23, the variable resistor is configured by one FET, that is, a p-channel or n-channel FET, but one p-channel FET and n-channel FET are connected in parallel. A variable resistor may be configured. When the resistance value is varied, the magnitude of the gate voltage may be changed. In this way, by configuring the variable resistor by combining two FETs, it is possible to improve the non-linear region of the FETs, so that distortion of the tuning signal can be reduced.
[0147]
FIG. 23 illustrates the case where the variable resistors in the two phase shift circuits 10C and 110C constituting the tuning amplifier 1 shown in FIG. 1 are replaced with FETs. However, the tuning amplifier 2 shown in FIG. The same applies to the case where the variable resistors in the two phase shift circuits 30C and 130C are replaced with FETs, and the case where variable resistors in the other phase shift circuits shown in FIG.
[0148]
In the phase shift circuit shown in each of the above-described embodiments, the overall tuning frequency is changed by changing the phase shift amount by changing the resistance value of the variable resistor connected in series with the capacitor 14 or the like. However, the overall tuning frequency may be changed by forming the capacitor 14 or the like by a variable capacitance element and changing its capacitance.
[0149]
FIG. 24 is a diagram showing a configuration of the phase shift circuit when the capacitors in the two types of phase shift circuits constituting the tuning amplifier 1 shown in FIG. 1 are replaced with variable capacitance diodes. FIG. 2A shows a configuration in which the variable resistor 16 is replaced with a fixed resistor and the capacitor 14 is replaced with a variable capacitance diode in the phase shift circuit 10C. FIG. 5B shows a configuration in which the variable resistor 116 is replaced with a fixed resistor and the capacitor 114 is replaced with a variable capacitance diode in the phase shift circuit 110C.
[0150]
In FIGS. 24A and 24B, the capacitor connected in series with the variable capacitance diode is used to block the direct current when a reverse bias voltage is applied between the anode and cathode of the variable capacitance diode. The impedance is extremely small at the operating frequency, that is, has a large capacitance. In addition, since the potential across the capacitor shown in FIGS. 24A and 24B is constant when looking at the direct current component, by applying a reverse bias voltage larger than the amplitude of the alternating current component between the anode and the cathode, Each variable capacitance diode can function as a variable capacitance capacitor.
[0151]
In this way, the capacitor 14 or 114 is formed of a variable capacitance diode, and the magnitude of the reverse bias voltage applied between its anode and cathode is variably controlled so that the capacitance of the variable capacitance diode can be arbitrarily set within a certain range. By changing the phase shift amount, the phase shift amount in each phase shift circuit can be changed. Therefore, the frequency at which the phase shift amount of the signal that makes a round in the tuning amplifier becomes 0 ° can be changed, and the tuning frequency of the tuning amplifier can be arbitrarily changed.
[0152]
By the way, in FIG. 24A and FIG. 24B described above, a variable capacitance diode is used as the variable capacitance element. However, an FET in which the source and drain are connected to a fixed potential in a DC manner and a variable voltage is applied to the gate is used. It may be. As described above, since the potentials at both ends of the variable capacitance diodes shown in FIGS. 24A and 24B are fixed in a direct current, these variable capacitance diodes need only be replaced with the above-described FET, and the gates can be used. By changing the applied voltage, the gate capacitance, that is, the capacitance of the FET can be changed.
[0153]
In FIGS. 24A and 24B described above, only the capacitance of the variable capacitance diode is varied, but the resistance value of the variable resistor may be varied at the same time. Needless to say, these variable resistors can be formed by using the channel resistance of the FET as shown in FIG. In particular, when a single variable resistor is configured by connecting a p-channel FET and an n-channel FET in parallel, the non-linear region of the FET can be improved, so that distortion of the tuning signal can be reduced. it can.
[0154]
Note that FIG. 24 illustrates the case where the capacitors in the two phase shift circuits 10C and 110C constituting the tuning amplifier 1 shown in FIG. 1 are replaced with variable capacitance elements, but the tuning amplifier 2 shown in FIG. The same applies to the case where the capacitors in the two phase shift circuits 30C and 130C are replaced with variable capacitance elements.
[0155]
In addition, the phase shift circuit shown in each of the above-described embodiments changes the overall tuning frequency by changing the phase shift amount by changing the resistance value of the variable resistor connected in series with the inductor 17 or the like. However, the overall tuning frequency may be changed by forming the inductor 17 or the like by a variable inductor and changing its inductance.
[0156]
FIG. 25 is a diagram showing a configuration when the inductors in various phase shift circuits are replaced with variable inductors. FIG. 9A shows a configuration in which the inductor 17 is replaced with a variable inductor 17a in the phase shift circuit 10L shown in FIG. FIG. 6B shows a configuration in which the inductor 117 is replaced with a variable inductor 117a in the phase shift circuit 110L shown in FIG.
[0157]
In this way, the inductor 17 or 117 is replaced with the variable inductor 17a or 117a, and the phase shift amount in each phase shift circuit can be changed by arbitrarily changing the inductance of the inductor 17 or 117 within a certain range. Accordingly, it is possible to change the frequency at which the phase shift amount of the signal that makes a round in each tuning amplifier becomes 0 °, and to arbitrarily change the tuning frequency.
[0158]
In FIGS. 25A and 25B described above, only the inductance of the variable inductor 17a or the like is varied. However, the resistance value of the variable resistor may be varied at the same time. 25 describes the case where the inductor 17 or the like in the phase shift circuit shown in FIG. 9 or FIG. 11 is replaced with a variable inductor, the inductor 37 in the phase shift circuit 30L shown in FIG. The same applies to the case where the inductor 137 in the illustrated phase shift circuit 130L is replaced with a variable inductor.
[0159]
By the way, in addition to the case of using a variable resistor, variable capacitance element, or variable inductor as described above, a plurality of resistors or capacitors having different element constants are prepared, and by switching the switches, the plurality of elements are selected. One or more may be selected. In this case, the element constants can be switched discontinuously depending on the number of elements to be connected by switching and the connection method (series connection, parallel connection, or a combination thereof). For example, instead of a variable resistor, a plurality of resistors in the n-th power series such as R, 2R, 4R,... Are prepared, and one or any plurality of resistors are selected and connected in series. The switching of resistance values at equal intervals can be easily realized with fewer elements. Similarly, a plurality of 2 n series capacitors having capacitances C, 2C, 4C,... Are prepared instead of capacitors, and one or any plurality of capacitors are selected and connected in parallel. Thus, switching of the capacitance at equal intervals can be easily realized with fewer elements. For this reason, the tuning amplifier of the present embodiment is applied to a circuit having a plurality of tuning frequencies, for example, an AM radio, and is suitable for a purpose of selecting and receiving one station from a plurality of broadcasting stations.
[0160]
FIG. 26 is a diagram showing a specific example of the variable inductor 17a and the like shown in FIG. 25, and schematically shows a planar structure formed on the semiconductor substrate. The structure of the variable inductor 17a shown in the figure can be applied to the variable inductor 137a or the like as it is.
[0161]
The variable inductor 17a shown in the figure includes a spiral inductor conductor 312 formed on a semiconductor substrate 310, a control conductor 314 formed so as to go around the outer periphery thereof, the inductor conductor 312 and the control conductor 314. Insulating magnetic body 318 formed so as to cover both of them.
[0162]
The control conductor 314 described above is connected to a variable voltage power source 316 to apply a variable bias voltage to both ends of the control conductor 314, and the DC bias voltage applied by the variable voltage power source 316 is variably controlled. The bias current flowing through the control conductor 314 can be changed.
[0163]
For the semiconductor substrate 310, for example, an n-type silicon substrate (n-Si substrate) or another semiconductor material (for example, an amorphous material such as germanium or amorphous silicon) is used. The inductor conductor 312 is formed of a metal thin film such as aluminum or gold or a semiconductor material such as polysilicon in a spiral shape.
[0164]
In addition to the variable inductor 17a, other components of the tuning amplifier including the phase shift circuit shown in FIG. 9 and the like are formed on the semiconductor substrate 310 shown in FIG.
[0165]
FIG. 27 is a diagram showing in more detail the shapes of the inductor conductor 312 and the control conductor 314 of the variable inductor 17a shown in FIG.
[0166]
As shown in the figure, the inductor conductor 312 located on the inner peripheral side is formed in a spiral shape having a predetermined number of turns (for example, about 4 turns), and two terminal electrodes 322 and 324 are connected to both ends thereof. ing. Similarly, the control conductor 314 located on the outer peripheral side is formed in a spiral shape having a predetermined number of turns (for example, about 2 turns), and two control electrodes 326 and 328 are connected to both ends thereof.
[0167]
FIG. 28 is an enlarged cross-sectional view taken along the line AA of FIG. 27, and shows a cross section of the insulating magnetic body 318 including the inductor conductor 312 and the control conductor 314.
[0168]
As shown in the figure, an inductor conductor 312 and a control conductor 314 are formed on the surface of a semiconductor substrate 310 via an insulating magnetic film 318a, and further, an insulating magnetic film 318b is formed on the surface thereof. Has been. The insulating magnetic body 318 shown in FIG. 26 is formed by these two magnetic films 318a and 318b.
[0169]
For example, as the magnetic films 318a and 318b, various magnetic films such as gamma-ferrite and barium-ferrite can be used. Various materials and methods for forming these magnetic films are conceivable. For example, a method of forming a magnetic film by vacuum deposition of FeO or the like, other molecular beam epitaxy (MBE), chemical vapor, and the like. There is a method of forming a magnetic film using a phase growth method (CVD method), a sputtering method, or the like.
[0170]
The insulating film 330 is made of a non-magnetic material and covers between the surrounding portions of the inductor conductor 312 and the control conductor 314. By eliminating the magnetic films 318a and 318b between the respective surrounding portions in this way, the leakage magnetic flux generated between the respective surrounding portions can be minimized, so that the magnetic flux generated by the inductor conductor 312 is effectively used. Thus, the variable inductor 17a having a large inductance can be realized.
[0171]
As described above, the variable inductor 17a shown in FIG. 26 and the like has the insulating magnetic body 318 (magnetic films 318a and 318b) formed so as to cover the inductor conductor 312 and the control conductor 314, and the control conductor By variably controlling the DC bias current flowing through 314, the saturation magnetization characteristic of the inductor conductor 312 using the above-described insulating magnetic body 318 as a magnetic path changes, and the inductance of the inductor conductor 312 changes.
[0172]
Therefore, the inductance itself of the inductor conductor 312 can be directly changed, and furthermore, since it can be formed on the semiconductor substrate 310 by using a thin film forming technique or a semiconductor manufacturing technique, the manufacture becomes easy. Furthermore, other components such as the tuning amplifier 1 can be formed on the semiconductor substrate 310, which is suitable when the entire tuning amplifier of each embodiment is integrally formed by integration.
[0173]
Note that the variable inductor 17a shown in FIG. 26 and the like may be formed by alternately winding the inductor conductor 312 and the control conductor 314, or overlapping the inductor conductor 312 and the control conductor 314. In any case, the saturation magnetization characteristic of the insulating magnetic body 318 can be changed by changing the DC bias current flowing through the control conductor 314, and the inductance of the inductor conductor 312 can be changed within a certain range. Can do.
[0174]
The variable inductor 17a shown in FIG. 26 and the like has been described by taking the case where the inductor conductor 312 or the like is formed on the semiconductor substrate 310 as an example. However, the variable inductor 17a may be formed on various insulating or conductive substrates such as ceramics. May be.
[0175]
Further, although the insulating material is used as the magnetic films 318a and 318b, a conductive material such as metal powder (MP) may be used. However, if such a conductive magnetic film is used in place of the above-described insulating magnetic film 318a or the like, the surrounding portions of the inductor conductor 312 and the like are short-circuited and do not function as inductor conductors. It is necessary to electrically insulate between the conductor and the conductive magnetic film. As this insulating method, there are a method of oxidizing the inductor conductor 312 and the like to form an insulating oxide film, a method of forming a silicon oxide film or a nitride film by a chemical vapor deposition method, and the like.
[0176]
In particular, a conductive material such as metal powder has an advantage that a large inductance can be secured since it has a higher magnetic permeability than an insulating material such as gamma and ferrite.
[0177]
In the variable inductor 17a shown in FIG. 26 and the like, both the inductor conductor 312 and the control conductor 314 are entirely covered with the insulating magnetic body 318, but only a part is covered so as to form a magnetic path. It may be. In this way, when an insulating magnetic material (or a conductive magnetic material) that becomes a magnetic path is partially formed, the magnetic flux generated by the inductor conductor 312 and the control conductor 314 is saturated by narrowing the magnetic path. It becomes easy to do. Therefore, even when a small bias current is passed through the control conductor 314, the magnetic flux is saturated, and the inductance of the inductor conductor 312 can be changed by variably controlling the small bias current. For this reason, the structure of the control system can be simplified.
[0178]
In addition, the variable inductor 17a shown in FIG. 26 and the like is formed by concentrically winding the inductor conductor 312 and the control conductor 314. These conductors are formed at adjacent positions on the surface of the semiconductor substrate 310, and they are formed. The gaps may be magnetically coupled by a magnetic path formed of an insulating or conductive magnetic material.
[0179]
FIG. 29 is a plan view schematically showing the variable inductor 17b when the inductor conductor and the control conductor are formed side by side at adjacent positions.
[0180]
The variable inductor 17b shown in the figure includes a spiral inductor conductor 312a formed on a semiconductor substrate 310, a spiral control conductor 314a formed at a position adjacent to the inductor conductor 312a, and an inductor conductor 312a. And an insulating magnetic body (or conductive magnetic body) 319 formed so as to cover each spiral center of the control conductor 314a.
[0181]
Similarly to the variable inductor 17a shown in FIG. 26 and the like, a variable voltage power source 316 is connected to the control conductor 314a in order to apply a variable bias voltage to both ends thereof, and a bias applied by the variable voltage power source 316 is applied. By controlling the voltage variably, a predetermined bias current flowing through the control conductor 314a can be changed.
[0182]
In the variable inductor 17b described above, an annular insulating magnetic body 319 (magnetic films 319a and 319b) is formed so as to pass through the spiral centers of the inductor conductor 312a and the control conductor 314a. Therefore, by variably controlling the DC bias current flowing through the control conductor 314a, the saturation magnetization characteristic of the inductor conductor 312a using the magnetic body 319 as a magnetic path changes, and the inductance of the inductor conductor 312a also changes.
[0183]
Further, when the tuning amplifier 1 or the like of each of the above-described embodiments is formed on a semiconductor substrate, a very large capacitance cannot be set as the capacitor 14 or the like. Accordingly, when the circuit is designed to have a small capacitance of a capacitor actually formed on a semiconductor substrate, if the apparent capacitance can be increased, the time constant T is set to a large value to lower the tuning frequency. Convenient to.
[0184]
FIG. 30 is a diagram showing a modification in which the capacitor 14 and the like used in the phase shift circuit 10C and the like shown in FIG. It functions as a capacitance conversion circuit that makes the capacitance appear larger. 30 corresponds to the capacitor 14 and the like included in the phase shift circuit 10C and the like.
[0185]
The capacitance conversion circuit 14a shown in FIG. 30 includes a capacitor 210 having a predetermined capacitance C0, two operational amplifiers 212 and 214, and four resistors 216, 218, 220, and 222. .
[0186]
In the operational amplifier 212 at the first stage, a resistor 218 (this resistance value is R18) is connected between the output terminal and the inverting input terminal, and this inverting input terminal is a resistor 216 (this resistance value is R16). To be grounded via).
[0187]
Between the voltage E1 applied to the non-inverting input terminal of the first stage operational amplifier 212 and the voltage E2 appearing at the output terminal,
[Equation 9]

There is a relationship. The first-stage operational amplifier 212 functions mainly as a buffer for performing impedance conversion, and the gain may be unity. In the case of gain 1, when R18 / R16 = 0, that is, R16 is set to infinity (the resistor 216 may be removed), or R18 is set to 0Ω (directly connected).
[0188]
In the operational amplifier 214 at the second stage, a resistor 222 (this resistance value is R22) is connected between the output terminal and the inverting input terminal, and between the inverting input terminal and the output terminal of the operational amplifier 212 described above. A resistor 220 (this resistance value is R20) is connected between them, and the non-inverting input terminal is grounded.
[0189]
If the voltage appearing at the output terminal of the second stage operational amplifier 214 is E3, the voltage E3 and the voltage E2 appearing at the output terminal of the first stage operational amplifier 212 are:
[Expression 10]

There is a relationship. Thus, the second-stage operational amplifier 214 functions as an inverting amplifier, and the first-stage operational amplifier 212 is used to set the input side to a high impedance.
[0190]
Further, as described above, the capacitor 210 having a predetermined capacitance is interposed between the non-inverting input terminal of the first-stage operational amplifier 212 and the output terminal of the second-stage operational amplifier 214 thus connected. It is connected.
[0191]
In the capacitance conversion circuit 14a shown in FIG. 30, if the transfer function of the entire circuit excluding the capacitor 210 is K4, the capacitance conversion circuit 14a can be represented by the system diagram shown in FIG. FIG. 32 is a system diagram in which this is converted by the mirror theorem.
[0192]
When the impedance Z1 shown in FIG. 32 is expressed using the impedance Z0 shown in FIG. 31,
[Expression 11]

It becomes. Here, in the case of the capacitance conversion circuit 14a shown in FIG. 30, the impedance is Z0 = 1 / (jωC0), and this is substituted into the equation (11),
[Expression 12]

[Formula 13]

It becomes. This equation (13) indicates that the capacitance C0 of the capacitor 210 in the capacitance conversion circuit 14a is apparently (1−K4) times. Therefore, when the gain K4 of the amplifier is negative, (1−K4) is always larger than 1, so that the capacitance C0 can be changed to a larger value.
[0193]
By the way, the gain of the amplifier in the capacitance conversion circuit 14a shown in FIG. 30, that is, the gain K4 of the amplifier constituted by the whole of the operational amplifiers 212 and 214, is obtained from the equations (9) and (10):
[Expression 14]

It becomes. Substituting this equation (14) into equation (13),
[Expression 15]

It becomes. Therefore, the apparent capacitance C between the two terminals 224 and 226 can be increased by setting the resistance values of the four resistors 216, 218, 220 and 222 to predetermined values.
[0194]
Further, when the gain of the amplifier by the first operational amplifier 212 is 1, that is, as described above, when R16 is infinite (resistor 216 is removed), or when R18 is set to 0Ω, R18 / R16 = 0. In this case, the above equation (15) is simplified,
[Expression 16]

It becomes.
[0195]
As described above, the capacitance conversion circuit 14a described above is actually formed on the semiconductor substrate by changing the resistance ratio R22 / R20 of the resistor 220 and the resistor 222 or the resistance ratio R18 / R16 of the resistor 216 and the resistor 218. The capacitance C0 of the capacitor 210 to be formed can be converted to an apparently larger one. Therefore, when the entire tuning amplifier 1 shown in FIG. 1 or the like is formed on a semiconductor substrate, a capacitor 210 having a small capacitance C0 is formed on the semiconductor substrate, and FIG. The circuit shown can be converted to a large capacitance C, which is advantageous for integration. In particular, if a large capacitance can be ensured in this way, the overall mounting area of the tuning amplifier 1 and the like shown in FIG. 1 can be reduced, and the material cost and the like can be reduced.
[0196]
Further, by forming at least one of the resistors 216, 218, 220, and 222 by a variable resistor, specifically, a junction type or MOS type FET or a p-channel FET and an n-channel FET are connected in parallel. By forming the variable resistor, it is possible to easily form a capacitor having a variable capacitance. Therefore, by using this capacitor instead of the variable capacitance diode shown in FIG. 24, the phase shift amount can be arbitrarily changed within a certain range. Therefore, the frequency at which the phase shift amount of the signal that makes a round in the tuning amplifier becomes 0 ° can be changed, and the tuning frequency of the above-described tuning amplifier can be arbitrarily changed.
[0197]
As described above, since the first stage operational amplifier 212 is used as a buffer for increasing the input impedance, the operational amplifier 212 may be replaced with an emitter follower circuit or a source follower circuit.
[0198]
Incidentally, in FIG. 30 described above, a case has been described in which the apparent capacitance is actually made larger than the capacitance of the capacitor element by combining an amplifier having a predetermined gain and a capacitor. An inductor can be used for the inductor, and the inductance of the inductor can be apparently increased.
[0199]
That is, when the impedance Z1 shown in FIG. 32 is expressed using the impedance Z0 shown in FIG. 31 as described above, the equation (11) is obtained. Here, in the case of an inductor having an inductance L0, impedance Z0 = jωL0, which is substituted into the equation (11),
[Expression 17]

[Expression 18]

It becomes. This equation (18) indicates that the inductance of the inductor element is actually 1 / (1-K4) times, and it appears when the gain K4 is set between 0 and 1. It can be seen that the inductance increases.
[0200]
FIG. 33 is a diagram showing a modified example in which the inductor 17 or the like used in the phase shift circuit 10L or the like shown in FIG. 9 or the like is configured by a circuit instead of a single element, and an inductor element (actually formed on a semiconductor substrate ( It functions as an inductance conversion circuit that makes the inductance of the inductor conductor) appear larger. 33 corresponds to the inductor 17 and the like included in the phase shift circuit 10L.
[0201]
The inductance conversion circuit 17c illustrated in FIG. 33 includes an inductor 260 having a predetermined inductance L0, two operational amplifiers 262 and 264, and two resistors 266 and 268.
[0202]
The first-stage operational amplifier 262 is a non-inverting amplifier with a gain of 1 whose output terminal is connected to the inverting input terminal, and mainly functions as a buffer for impedance conversion. Similarly, the operational amplifier 264 in the second stage has an output terminal connected to the inverting input terminal, and functions as a non-inverting amplifier with a gain of 1. Further, a voltage dividing circuit by resistors 266 and 268 is inserted between these two non-inverting amplifiers.
[0203]
Thus, by inserting the voltage dividing circuit between the two, the gain of the entire amplifier including the two non-inverting amplifiers can be freely set between 0 and 1.
[0204]
In the inductance conversion circuit 17c shown in FIG. 33, if the transfer function of the entire circuit (amplifier) excluding the inductor 260 is K4, the gain K4 is determined by the voltage dividing ratio of the voltage dividing circuit formed by the resistors 266 and 268, respectively. When the resistance value of R66 and R68 is
[Equation 19]

It becomes. Substituting this gain K4 into equation (18) to calculate the apparent inductance L,
[Expression 20]

It becomes. Therefore, the apparent inductance L between the two terminals 254 and 256 can be increased by increasing the resistance ratio R68 / R66 of the resistors 266 and 268. For example, when R68 = R66, the inductance L can be doubled from L0 from the equation (20).
[0205]
Thus, the inductance conversion circuit 17c described above apparently increases the inductance L0 of the inductor 260 that is actually connected by changing the voltage dividing ratio of the voltage dividing circuit inserted between the two non-inverting amplifiers. be able to. Therefore, when the entire tuning amplifier including the phase shift circuit shown in FIG. 9 or the like is formed on the semiconductor substrate, an inductor 260 having a small inductance L0 is formed on the semiconductor substrate by a spiral conductor or the like. Therefore, it can be converted into a large inductance L by the inductance conversion circuit shown in FIG. 33, which is convenient for integration. In particular, if a large inductance can be ensured in this way, it is easy to lower the tuning frequency of the tuning amplifier to a relatively low frequency region. Further, by integrating, the mounting area of the entire tuning amplifier can be reduced, and the material cost and the like can be reduced.
[0206]
In addition to the case where the voltage dividing ratio of the voltage dividing circuit by the resistors 266 and 268 is fixed, at least one of these two resistors 266 and 268 is formed by a variable resistor, specifically, a junction type or MOS type FET. Alternatively, the voltage dividing ratio may be continuously changed by connecting a p-channel FET and an n-channel FET in parallel to form a variable resistor. In this case, the gain of the entire amplifier including the operational amplifiers 262 and 264 shown in FIG. 33 changes, and the inductance L between the terminals 254 and 256 also changes continuously. Therefore, by using this inductance conversion circuit 17c instead of the variable inductor 17a shown in FIG. 25, the phase shift amount in each phase shift circuit can be arbitrarily changed within a certain range. Therefore, the frequency at which the phase shift amount of the signal that makes a round in the tuning amplifier becomes 0 ° can be changed, and the tuning frequency of the above-described tuning amplifier can be arbitrarily changed.
[0207]
In addition, since the gain of the entire amplifier including the two operational amplifiers 262 and 264 is set to 1 or less in the inductance conversion circuit 17c shown in FIG. 33, the whole may be replaced with an emitter follower circuit or a source follower circuit.
[0208]
The present invention is not limited to the various embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
[0209]
For example, in each tuning amplifier shown in FIG. 1 and the like, the feedback resistor 70 having a fixed resistance value is used as the feedback side impedance element, and the input resistance 74 having a fixed resistance value is used as the input side impedance element. At least one of the resistors may be configured by a variable resistor so that the maximum attenuation can be arbitrarily changed. In this case, it goes without saying that the variable resistor can be formed by utilizing the channel resistance of the FET as shown in FIG. In particular, when a single variable resistor is configured by connecting a p-channel FET and an n-channel FET in parallel, the non-linear region of the FET can be improved, so that distortion of the tuning signal can be reduced. it can.
[0210]
Similarly, when the feedback side impedance element and the input side impedance element are capacitors, at least one of them may be constituted by a variable capacitance diode or a gate capacitance variable FET so that the maximum attenuation can be arbitrarily changed.
[0211]
In addition, the tuning amplifier 1 and the like of the above-described embodiment include two phase shift circuits. When the tuning frequency is varied, a CR circuit or an LR circuit included in both phase shift circuits is configured. In addition to changing at least one element constant of the resistor and the capacitor or inductor, there may be a case of changing at least one element constant of the resistor, capacitor or inductor included in the CR circuit or LR circuit included in one phase shift circuit. . It is also possible to configure a tuning amplifier with a fixed tuning frequency by fixing all the element constants of all resistors, capacitors or inductors.
[0212]
Further, in each of the above-described embodiments, one phase shift circuit 10C, 10L, etc. constituting the tuning amplifier is configured using a junction type FET. However, the phase shift circuit is configured using a MOS type FET or a bipolar transistor. You may make it comprise.
[0213]
In a phase shift circuit in which an FET is replaced with a bipolar transistor, a current flows between the base and emitter when an input signal is input to the base, so that the voltage appearing at the emitter (AC voltage) and the voltage appearing at the collector (AC voltage) Is not exactly the same. However, when the current amplification is about several tens to one hundred times, the difference is 1% to several%, and can be ignored in practice. Alternatively, this difference may be corrected by setting the collector resistance slightly larger than the emitter resistance.
[0214]
In particular, when a phase shift circuit is configured using bipolar transistors, the upper limit of the operating frequency can be increased and the potential difference between the base and emitter is smaller than the potential difference between the gate and source of the FET. Attenuation of the signal amplitude input / output to / from the phase circuit can be reduced. Therefore, a phase shift circuit configured using bipolar transistors is suitable for use in a stage preceding a tuning amplifier.
[0215]
Further, in each of the above-described embodiments, the stability can be improved by configuring one of the phase shift circuits 110C, 110L, etc. constituting the tuning amplifier using an operational amplifier. In this case, since the offset voltage and the voltage gain are not required to be so high performance, a differential input amplifier having a predetermined amplification degree may be used instead of the operational amplifier in each phase shift circuit.
[0216]
FIG. 34 is a circuit diagram in which a part necessary for the operation of the phase shift circuit of each embodiment is extracted from the configuration of the operational amplifier, and the whole operates as a differential input amplifier having a predetermined amplification degree. The differential input amplifier shown in FIG. 1 includes a differential input stage 300 composed of FETs, a constant current circuit 302 that supplies a constant current to the differential input stage 300, and a predetermined bias voltage applied to the constant current circuit 302. A bias circuit 304 and an output amplifier 306 connected to the differential input stage 300 are included. As shown in the figure, the configuration of the differential input amplifier can be simplified and the bandwidth can be increased by omitting the multi-stage amplifier circuit for increasing the voltage gain included in the actual operational amplifier. Thus, by simplifying the circuit, the upper limit of the operating frequency can be increased, and accordingly, the upper limit of the operating frequency of the tuning amplifier 1 and the like configured using this differential input amplifier is increased accordingly. Can do.
[0217]
【The invention's effect】
As described above, in the invention according to each claim, the amplitude of the input / output signal does not change in each of the first and second phase shift circuits, and only the phase is shifted by a predetermined amount according to the element constant of the capacitor or the like. The tuning operation is performed at a frequency such that the total amount of phase shift is 180 ° by the two phase shift circuits as a whole.
[0218]
In particular, when the differential input amplifier included in the above-described phase shift circuit is an operational amplifier, the operation of the phase shift circuit can be stabilized.
[0219]
Also, both the input-side impedance element and the feedback-side impedance element are both formed by resistors or capacitors, and by changing at least one element constant, the tuning point is not accompanied by amplitude fluctuation at the tuning point. It is possible to arbitrarily change the maximum attenuation amount in the frequency region away from.
[0220]
Further, by changing each element constant of the capacitor or inductor included in the phase shift circuit or a resistor connected in series with these elements, the amount of phase shift in each phase shift circuit changes. As a whole, the frequency at which the total phase shift amount is 180 °, that is, the tuning frequency can be arbitrarily changed. In particular, when changing the resistance value, the resistance between the source and drain of the FET can be used, and when changing the capacitance of the capacitor, an element such as a variable capacitance diode can be used. Suitable for forming in Furthermore, with respect to the inductor, in the two magnetically coupled electrodes formed on the semiconductor substrate, the inductance of the other electrode can be directly changed by changing the magnitude of the DC bias current flowing to one electrode. This is also suitable for forming a variable inductor on a semiconductor substrate.
[0221]
Further, in order to change the tuning frequency as described above, a plurality of resistors or the like may be selectively used by switching a switch in addition to continuously changing the element constant such as a resistor.
[0222]
In addition, the capacitors and inductors included in the phase shift circuit are apparently large by replacing the capacitor element or a circuit in which the inductor element and the amplifier are connected in parallel, thereby actually increasing the capacitance of the capacitor element and the inductance of the inductor element. Can show. Therefore, in practice, capacitor elements and inductor elements can be formed with a small occupied area, and these capacitances and inductances can be converted into large values, and the occupied area of the semiconductor substrate can be reduced.
[0223]
In addition, since each element constituting the tuning amplifier of each claim can be formed by an integrated circuit manufacturing method, the tuning amplifier can be formed in a small size as an integrated circuit on a semiconductor wafer, and can be made inexpensively by mass production. Can do.
[0224]
In particular, if the channel between the source and drain of the FET is used as the variable resistance of the CR circuit in each phase shift circuit, and the control voltage applied to the gate of this FET is changed to change the resistance of the channel, the control The influence of the inductance and capacitance of the wiring to which the voltage is applied can be avoided, and a tuning amplifier having ideal characteristics almost as designed can be obtained.
[0225]
In the tuning amplifier of the present invention, the maximum attenuation is determined by the resistance ratio of the input side impedance element and the feedback side impedance element, and the tuning frequency is determined by the time constant of the CR circuit and the LR circuit in each phase shift circuit. The attenuation, tuning frequency, and gain at the tuning frequency can be set without interfering with each other.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a tuning amplifier according to a first embodiment to which the present invention is applied.
2 is a circuit diagram showing an extracted configuration of the previous phase shift circuit shown in FIG. 1; FIG.
FIG. 3 is a vector diagram showing a relationship between an input / output voltage of a preceding phase shift circuit and a voltage appearing in a capacitor or the like.
4 is a circuit diagram showing an extracted configuration of a subsequent phase shift circuit shown in FIG. 1. FIG.
FIG. 5 is a vector diagram showing a relationship between an input / output voltage of a phase circuit in the subsequent stage and a voltage appearing in a capacitor or the like.
FIG. 6 is a system diagram in which the entire two phase shift circuits are replaced with a circuit having a predetermined transfer function.
7 is a system diagram obtained by converting the system shown in FIG. 6 by the mirror theorem. FIG.
FIG. 8 is a diagram illustrating tuning characteristics of the tuning amplifier according to the first embodiment.
FIG. 9 is a circuit diagram showing another example of a phase shift circuit.
10 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 9 and voltages appearing in an inductor or the like.
FIG. 11 is a circuit diagram showing another example of the phase shift circuit.
12 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 11 and voltages appearing in an inductor or the like.
FIG. 13 is a circuit diagram showing a configuration of a tuning amplifier according to a second embodiment to which the present invention is applied.
14 is a circuit diagram showing an extracted configuration of the preceding phase shift circuit shown in FIG. 13; FIG.
FIG. 15 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit and the voltage appearing in the inductor or the like.
16 is a circuit diagram showing an extracted configuration of the latter-stage phase shift circuit shown in FIG.
FIG. 17 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit and the voltage appearing in a capacitor or the like.
FIG. 18 is a circuit diagram showing another example of the phase shift circuit.
19 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 18 and voltages appearing in an inductor or the like.
FIG. 20 is a circuit diagram showing another example of the phase shift circuit.
21 is a vector diagram showing a relationship between input / output voltages of the phase shift circuit shown in FIG. 20 and voltages appearing in an inductor or the like.
FIG. 22 is a diagram illustrating a connection form between a phase shift circuit and a phase inversion circuit.
FIG. 23 is a diagram illustrating a configuration of a phase shift circuit in which a variable resistor of the phase shift circuit is replaced with an FET.
FIG. 24 is a diagram showing a configuration of a phase shift circuit in which a capacitor of the phase shift circuit is replaced with a variable capacitance diode.
FIG. 25 is a diagram illustrating a configuration of a phase shift circuit in which the inductor of the phase shift circuit is replaced with a variable inductor.
FIG. 26 is a diagram illustrating an example of a variable inductor.
27 is a diagram showing in more detail the shapes of the inductor conductor and control conductor of the variable inductor shown in FIG. 26. FIG.
28 is an enlarged sectional view taken along line AA in FIG. 27. FIG.
FIG. 29 is a diagram illustrating another example of a variable inductor.
FIG. 30 is a diagram showing a configuration of a capacitance conversion circuit that apparently increases the capacitance actually possessed by a capacitor;
31 is a diagram showing the circuit shown in FIG. 30 using a transfer function.
32 is a diagram obtained by converting the configuration shown in FIG. 31 by the mirror theorem.
FIG. 33 is a diagram showing a configuration of an inductance conversion circuit that apparently increases the inductance that the inductor actually has.
FIG. 34 is a circuit diagram in which a portion necessary for the operation of the phase shift circuit of the present invention is extracted from the configuration of the operational amplifier.
FIG. 35 is a characteristic curve diagram showing an example of the relationship between the tuning frequency, the gain at the tuning frequency, and the maximum attenuation in the conventional tuning amplifier.
[Explanation of symbols]
1 Tuning amplifier
10C, 110C phase shift circuit
12 FET
14, 114 capacitors
16, 116 Variable resistance
18, 20, 118, 120 Resistance
80 Phase inversion circuit
82, 112 operational amplifier
70 Feedback resistance
74 Input resistance

Claims (27)

An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting the input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means through the first capacitor and the other AC signal as the first A first phase shift circuit including a synthesis means for synthesis via a resistor;
A differential input amplifier having one end of a second resistor connected to the inverting input terminal; a third resistor connected between the inverting input terminal and the output terminal of the differential input amplifier; A fourth circuit connected to the other end of the resistor and a series circuit composed of a second capacitor, and a connection portion of the fourth resistor and the second capacitor is connected to a non-inverting input terminal of the differential input amplifier. A second phase shift circuit connected to
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback-side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. Tuning amplifier. An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting the input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means through the first inductor and the other AC signal as the first A first phase shift circuit including a synthesis means for synthesis via a resistor;
A differential input amplifier having one end of a second resistor connected to the inverting input terminal; a third resistor connected between the inverting input terminal and the output terminal of the differential input amplifier; A fourth circuit connected to the other end of the resistor and a series circuit including a second inductor, and a connection part of the fourth resistor and the second inductor is connected to a non-inverting input terminal of the differential input amplifier. A second phase shift circuit connected to
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback-side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. Tuning amplifier. An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting an input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means via a capacitor, and the other AC signal via a first resistor A first phase shift circuit including combining means for combining, a differential input amplifier having one end of a second resistor connected to the inverting input terminal, an inverting input terminal and an output terminal of the differential input amplifier, And a series circuit including a fourth resistor and an inductor connected to the other end of the second resistor, and a connection portion of the fourth resistor and the inductor. A second phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback-side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. Tuning amplifier. An adder circuit that includes an input-side impedance element that receives an input signal at one end and a feedback-side impedance element that receives a feedback signal at one end, and adds the input signal and the feedback signal;
Conversion means for converting an input AC signal into in-phase and reverse-phase AC signals and outputting them, one AC signal converted by the conversion means via an inductor, and the other AC signal via a first resistor A first phase shift circuit including combining means for combining, a differential input amplifier having one end of a second resistor connected to the inverting input terminal, an inverting input terminal and an output terminal of the differential input amplifier, And a series circuit composed of a fourth resistor and a capacitor connected to the other end of the second resistor, and a connection portion of the fourth resistor and the capacitor. A second phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;
A phase inversion circuit that inverts the phase of the input AC signal, amplifies the signal with a predetermined amplification, and outputs the amplified signal;
Each of the first and second phase shift circuits and the phase inversion circuit are cascade-connected, and a signal added by the adder circuit to a first stage circuit among the plurality of cascade-connected circuits And a signal output from a circuit at the final stage is input to the one end of the feedback-side impedance element as the feedback signal, and the output of any of the plurality of circuits is output as a tuning signal. Tuning amplifier. In any one of Claims 1-4,
In the first and second phase shift circuits, the output voltage is both advanced or delayed in phase with respect to the input voltage, and the total phase shift amount of the first and second phase shift circuits is 180 °. A tuning amplifier characterized by performing a tuning operation at a frequency of In any one of Claims 1-5,
The differential amplifier is an operational amplifier. In any one of Claims 1-6,
Each of the input side impedance element and the feedback side impedance element is a resistor. In claim 7,
Forming at least one of the input-side impedance element and the feedback-side impedance element by a variable resistor, and changing a resistance ratio of the input-side impedance element and the feedback-side impedance element to change a maximum attenuation amount; Tuning amplifier. In any one of Claims 1-6,
Each of the input side impedance element and the feedback side impedance element is a capacitor. In claim 9,
At least one of the input side impedance element and the feedback side impedance element is formed by a variable capacitance element, and the maximum attenuation is changed by changing a capacitance ratio of the input side impedance element and the feedback side impedance element. A tuned amplifier. In any one of Claims 1-6,
Tuning is achieved by forming at least one of the first resistor included in the first phase shift circuit and the fourth resistor included in the second phase shift circuit by a variable resistor, and changing the resistance value. A tuning amplifier characterized by changing a frequency. In claim 8 or 11,
A tuning amplifier, wherein the variable resistance is formed by a channel of an FET, and the channel resistance is changed by changing a gate voltage. In claim 8 or 11,
The variable resistor is formed by connecting the source and drain of a p-channel FET and an n-channel FET in parallel, and the channel resistance is changed by changing the magnitude of each gate voltage. amplifier. In any one of Claims 1, 3, and 4,
A tuning amplifier, wherein the capacitor included in at least one of the first and second phase shift circuits is formed by a variable capacitance element, and the tuning frequency is changed by changing the capacitance. In claim 10 or 14,
A tuning amplifier, wherein the variable capacitance element is formed of a variable capacitance diode whose reverse bias voltage can be changed, or an FET whose gate capacitance can be changed by changing the gate voltage. In any one of Claims 2-4,
A tuning amplifier, wherein a tuning frequency is changed by changing an inductance of the inductor included in at least one of the first and second phase shift circuits. In claim 16,
The inductor is formed on a semiconductor substrate and has two spiral electrodes magnetically coupled to each other via a magnetic material, and changes the magnitude of a DC bias current flowing through one of the electrodes. The tuning amplifier characterized by changing the inductance of the other electrode. In claim 16,
The inductor is
An inductor conductor formed in a substantially spiral shape on a substrate;
A control conductor formed on the substrate and substantially concentrically with the inductor conductor, through which a predetermined DC bias current flows;
A magnetic body formed to cover the inductor conductor and the control conductor;
The tuning amplifier is characterized in that the inductance that appears at both ends of the inductor conductor is changed by changing a DC bias current that flows through the control conductor. In claim 16,
The inductor is
An inductor conductor formed in a substantially spiral shape on a substrate;
A control conductor which is formed in a substantially flat spiral shape at a position adjacent to the inductor conductor on the substrate, and a predetermined DC bias current flows;
A magnetic body formed in an annular shape so as to pass through each of the spiral centers of the inductor conductor and the control conductor;
The tuning amplifier is characterized in that the inductance that appears at both ends of the inductor conductor is changed by changing a DC bias current that flows through the control conductor. In any one of Claims 1-6,
Switch at least one of the first resistor included in the first phase shift circuit and the fourth resistor included in the second phase shift circuit with a plurality of resistors having a fixed resistance value. A tuning amplifier characterized in that the tuning frequency is changed by selectively connecting to the tuning amplifier. In any one of Claims 1, 3, and 4,
The capacitor included in at least one of the first and second phase shift circuits is replaced with a plurality of capacitors having a fixed capacitance, and the tuning frequency is changed by selectively connecting the capacitors by switching. A tuned amplifier. In any one of Claims 2-4,
The inductor included in at least one of the first and second phase shift circuits is replaced with a plurality of inductors having fixed inductances, and the tuning frequency is changed by selectively connecting the switches by switching. Tuning amplifier. In any one of Claims 1, 3, and 4,
Replacing the capacitor included in at least one of the first and second phase shift circuits with an amplifier having a negative gain and a capacitor element connected in parallel between the input and output of the amplifier, the amplifier A tuning amplifier characterized in that the capacitance seen from the input side of the capacitor is actually larger than the capacitance of the capacitor element. In claim 23,
A tuning amplifier characterized in that a tuning frequency is changed by changing a gain viewed from the input side of the amplifier by changing a gain of the amplifier. In any one of Claims 2-4,
By replacing the inductor included in at least one of the first and second phase shift circuits with an amplifier having a gain set between 0 and 1 and an inductor element connected in parallel between the input and output of the amplifier A tuning amplifier characterized in that the inductance viewed from the input side of the amplifier is actually made larger than the inductance of the inductor element. In claim 25,
A tuning amplifier, wherein a tuning frequency is changed by changing a gain of the amplifier and changing an inductance viewed from an input side of the amplifier. In any one of Claims 1-26.
A tuning amplifier formed as a semiconductor integrated circuit.

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