JP3251835B2 - Semiconductor device for tuner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for a tuner, and more particularly to an improvement in a control circuit used therein.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional tuner device using a PLL circuit for a synthesizer. Antenna 1
Is input to an RF amplifier (RFAMP) 2 and amplified. The output signal of the RF amplifier 2 is a mixer (MIX)
3 is converted to a low frequency by an output signal (hereinafter, referred to as an OSC signal) 8 of a voltage-controlled oscillator (hereinafter, referred to as a VCO) 4 which is a local oscillator (hereinafter, referred to as an OSC) to become an IF signal. . This IF signal is input to an IF amplifier (IFAMP) 5 and amplified. Amplified I
The F signal is input to a detector (DET) 6, detected and amplified, and output from the tuner device.

In FIG. 3, a VCO 4, a prescaler block (PSB) 9, and a program counter block (P
The CB) 10, the phase comparator (ΦCOMP) 12, and the low-pass filter (hereinafter, referred to as LPF) 13 constitute a PLL circuit for a synthesizer. The prescaler block 9, the program counter block 10, and the phase comparator 1
2 is included in the control circuit 7.

[0004] The OSC signal 8 of the VCO 4 is input to a prescaler block 9 in a control circuit 7 via a buffer (not shown). A voltage signal output from the phase comparator 12 in the control circuit 7 is input to the VCO 4 via the LPF 13.
The output signal of the display drive circuit (DRV) 19 in the control circuit 7 is connected to a display panel (DISP) 21. Further, the IF signal is transmitted to the frequency counter 1 in the control circuit 7.
6 is input.

Next, the control circuit 7 will be described. The input OSC signal 8 is input to a prescaler block 9, and the output is input to a program counter block 10. The divided signal 11 which is the output is input to the phase comparator 12. The phase comparator 12 has a reference signal (REF) 14
And the phase comparator 12 outputs a voltage signal corresponding to the phase difference between the reference signal 14 and the frequency-divided signal 11. Generally, an output signal of a crystal oscillator is used as the reference signal 14, and its frequency does not necessarily need to match the frequency to be tuned, the intermediate frequency, and the frequency of the OSC signal 8.
On the other hand, the controller (CONT) 15 and the frequency counter (fCOUNT) 16 are connected by a bidirectional data bus. Program counter 1 from controller 15
The division ratio setting signal 17 is supplied to 0. Further, a frequency display signal 18 is supplied from the controller 15 to the display drive circuit 19.

The configuration of the prescaler block 9 will be described. The input OSC signal 8 is input to a prescaler (PS) 9a as a fixed frequency divider. The output terminal of the prescaler 9a and one input terminal of the switch 9b, the output terminal of the switch 9b and the P / (P + 1) prescaler (P /
The input terminal of the (P + 1PS) 9c, the input terminal of the prescaler 9a, and the other input terminal of the switch (SW) 9b are connected to each other. The switching control signal 20 for the switch 9b is supplied from the controller 15.

The configuration of the program counter block 10 will be described. A signal from the prescaler block 9 is input to a program counter (PCOUNT) 10a and a swallow counter (SCOUNT) 10b. An output signal of the swallow counter 10b and an output signal of the program counter 10a are input to a flip-flop (hereinafter, referred to as FF) 10c. The selection signal PSC output from the FF 10c is supplied to the P / (P + 1) prescaler 9c.

Next, the operation of the control circuit 7 will be described. At the time of tuning, the frequency division ratio setting signal 17 corresponding to the reception frequency
The count number N of the program counter block 10 is controlled, and the number N of frequency division is determined. Therefore, the oscillation frequency of the OSC signal 8 output from the VCO 4 is controlled according to the number of divisions. The RF signal is frequency-converted into an IF signal by the OSC signal 8, and channel selection is performed. Based on the count output signal 22 obtained by counting the IF signal by the frequency counter 16, it can be determined whether or not the controller 15 has selected the frequency of the broadcasting station. That is, automatic channel selection is performed. In this case, the reception frequency corresponding to the value of the count number N or the frequency after tuning corresponding to the count output signal 22 is displayed on the display panel 21 by the controller 15 and the display drive circuit 19.

While the output signal of the prescaler block 9 is counted up to the number of set values of the swallow counter 10b, the number of divisions P + 1 is selected by the selection signal PSC, and the P / (P + 1) prescaler 9c performs P + 1 frequency division. . Thereafter, the P / (P + 1) prescaler 9c performs P frequency division, and the PLL circuit for the synthesizer is phase-locked.

In the case of a tuner semiconductor device that selects a channel in several frequency bands, it is necessary to greatly change the frequency division ratio. Therefore, the switch 9b is switched by the switching control signal 20 from the controller, and the prescaler 9a Either the input signal or the output signal is selected and input to the P / (P + 1) prescaler 9c.

FIG. 4 shows a conventional tuner device using the control circuit 7, the OSC 23, and a variable capacitor (hereinafter referred to as a variable capacitor) 24. The configuration from the antenna 1 to the output of the detector 6 is the same as in FIG. The output signal of the OSC 23 whose oscillation frequency is variable is input to the mixer 3.
A variable condenser 24 is connected to the OSC 23. Also, O
The OSC signal 8 output from the SC 23 is input to another prescaler 25 via a buffer (not shown). The output signal of the another prescaler 25 is input to the frequency counter 16 in the control circuit 7. The controller 15 in the control circuit 7 and the frequency counter 16 are interconnected by a data bus, and a frequency indication signal 18
Is supplied to the display drive circuit 19 in the control circuit 7. The output signal of the display drive circuit 19 is supplied to the display panel 21. In FIG. 4, parts unnecessary for the operation in this case are omitted.

[0012]

The above tuner device is
The tuning is performed by changing the capacitance value of the variable condenser 24 manually to change the oscillation frequency of the OSC 23. In a tuner device using this variable condenser, it is general to display a tuning frequency by, for example, a bar moving along a scale (not shown),
The control circuit 7 counts the oscillation frequency of the OSC 23, and displays the reception frequency according to the value.
The receiving frequency being selected can be always digitally displayed. However, since the frequency of the OSC signal 8 is high, it cannot be counted by the general-purpose frequency counter 16. Therefore, the frequency is divided by the another prescaler 25, the frequency-divided signal is further divided by the frequency counter 16, and the reception frequency is displayed according to the output signal.

Therefore, in the above configuration, a prescaler is required separately from the control circuit, and there is a problem that it is difficult to reduce the number of parts and reduce the cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost tuner semiconductor device that can be used in both a tuner device using a PLL circuit for a synthesizer and a tuner device using a variable condenser with a small number of components.

[0014]

In order to solve the above problems and achieve the object, the following means are taken in the semiconductor device for a tuner of the present invention. (1) In the semiconductor device for a tuner according to the present invention, the output signal of the local oscillator of the tuner and the selection signal are input, and the output of the local oscillator is determined by the number of divisions selected by the selection signal. A prescaler that divides and outputs a signal; a first input terminal to which an output signal of the prescaler is input; a second input terminal to which a first control signal is input; In the case of the above, the signal of the first input terminal is outputted to the first output terminal, and when the first control signal is at the second level, the signal of the first input terminal is outputted to the second output terminal. And a switching circuit for outputting. An input terminal connected to a first output terminal of the switching circuit, for outputting a signal obtained by counting signals from the input terminal, and outputting the selection signal in accordance with the counted value; A phase detection circuit for detecting a phase difference signal between the output signal and the reference signal. A gate circuit for supplying the selection signal output from the counter to the prescaler when the first control signal is at the first level; an input terminal connected to the second output terminal of the switching circuit; And a frequency counter for outputting a value obtained by counting the frequency of the obtained signal. While displaying the reception frequency according to the output signal of the frequency counter,
When the local oscillator forms a PLL circuit, the first
A controller is provided for bringing the control signal to the first level, and otherwise to the second level.

In the tuner semiconductor device according to the present invention, the output signal of the prescaler is switched and supplied to one of the counter and the frequency counter by the switching circuit in response to the first control signal. . Also, since the number of divisions of the prescaler is fixed by the first control signal, it is shared by both a tuner using a PLL circuit and a tuner using a variable condenser and a local oscillator, and a dedicated reception frequency is displayed. LS
I is configured. Also, the circuit scale is almost the same,
By sharing the dedicated LSI for both, the mass production effect is increased and the cost is reduced. Furthermore, when a variable condenser and a local oscillator are used, a separate prescaler is unnecessary, so that the number of components is reduced as compared with the conventional case, and the cost is further reduced. In this case, since no signal is supplied to the counter, power consumption is reduced.

The switching circuit has a third input terminal to which an IF signal of the tuner is input, and when the first control signal is at a first level, the switching circuit has a third input terminal. A signal at a third input terminal is output to the second output terminal.

In the tuner semiconductor device of the present invention, since the IF signal is input to the frequency counter by the switching circuit and the presence or absence of the broadcast is confirmed, the tuning is reliably and quickly performed. It is also possible to display the reception status.

The switching circuit has a third input terminal to which an IF signal of the tuner is input, and a fourth input terminal to which a second control signal is input. ,
When the second control signal is input, the signal of the third input terminal is output to the second output terminal in preference to the case of the second level of the first control signal. Further, the controller outputs the second control signal when determining that the broadcast has been selected, and determines that the broadcast has been selected based on the IF signal.

In the tuner semiconductor device according to the present invention, the output signal of the prescaler and the IF are controlled in response to the second control signal having priority over the first control signal.
Since the signal and the signal are switched and input to the frequency counter, the reception frequency at that time is displayed during the channel selection, and the presence or absence of the broadcast can be confirmed by the presence or absence of the IF signal. Accordingly, the circuits for displaying the reception frequencies of the tuner using the variable condenser and the tuner using the PLL circuit for the synthesizer have the same configuration, and the circuit scale is relatively small.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 are denoted by the same reference numerals, and only different portions will be described. 1 and 2 show the configuration of the embodiment of the present invention.

FIG. 1 shows the present invention using a variable condenser 24 and an OSC2.
3 is a block diagram when applied to a tuner device using No. 3; FIG. The OSC signal 8 output from the OSC 23 is input to the control circuit 26 according to the present invention. An output signal of the display drive circuit 19 in the control circuit 26 is input to the display panel 21.

In the control circuit 26, the input O
The SC signal 8 is input to a prescaler block 9. The output signal of the prescaler block 9 is supplied to one input terminal of the AND gate G1 and one input terminal 27b of the switch 27. The output signal of the AND gate G1 is supplied to the program counter block 10. The tuning signal P which is the output of the FF 10c in the program counter block 10
SC is supplied to one input terminal of the AND gate G2.
The selection signal PSC1 output from the AND gate G2 is P /
(P + 1) is supplied to the prescaler 9c. The first control signal IFS from the controller (CONT) 28 is input to the inverter G3 and the switch 27c. The output signal of the inverter G3 is supplied to the other input terminals of the AND gates G1 and G2.

The output signal of the switch 27 is supplied to the frequency counter 16. The controller 28 and the frequency counter 16 are interconnected by a data bus. The frequency display signal 18 output from the controller 28
Supplied to

Next, the operation of the control circuit 26 will be described. When setting the control circuit 26 to tuning using a variable condenser,
The controller 28 sets the first control signal IFS to “1”.
Therefore, the output signal of the inverter G3 becomes "0", the AND gates G1 and G2 do not pass the signal, and the program counter block 10 does not operate.
The number of divisions of the P / (P + 1) prescaler 9c is fixed to one of P and P + 1 according to the gated selection signal PSC1. In this case, the first control signal IFS
As a result, the switch 27 is switched to one input terminal 27b, and the output signal of the prescaler block 9 is supplied to the frequency counter 16. The count output signal 22 of the frequency counter 16 is supplied to a controller 28, and display data output from the controller 28 is displayed on a display panel 21 via a display drive circuit 19.

Next, the control circuit 26 is connected to the synthesizer PL.
A case where the present invention is used for an L circuit will be described. Although not particularly shown when using the PLL circuit for the synthesizer, the OSC signal 8 which is the output of the VCO 4 is input to the control circuit 26 as in FIG. Is input to the LPF 13. Also, IF
An IF signal output from the amplifier 5 is input to the other input terminal 27a of the switch 27.

In the case of this configuration, the first control signal IFS is set to "0" by the controller 28. The prescaler block 9 divides the frequency of the OSC signal 8 supplied from the VCO and supplies it to the AND gate G1. In this case, since the output signal of the inverter circuit G3 is "1", the output signal of the prescaler block 9 is supplied to the program counter 10a through the AND gate G1, and further divided by the program counter block 10. Further, the switch 27 is turned on by the first control signal IFS.
Side, and the IF signal is input to the frequency counter 16 to count the frequency. In this case, the controller 15 and the display drive circuit 19 display the reception frequency according to the value of the number N of the frequency division of the counter block or the count output signal 22 for the IF signal on the display panel 21. On the other hand, the presence or absence of the broadcast is determined by the controller 28 using the frequency count value of the IF signal. Further, the result of the determination of the broadcast by the IF signal may be displayed for the user.

The controller 28 controls the first control signal I
A control signal is generated separately from the FS, and the other control signal is supplied to the switching control input terminal 27 c of the switch 27. As shown in FIG. 2, a switch 29 may be used instead of the AND gate G1. In this case, the first control signal I
The output signal of the prescaler block 9 is switched and supplied to one of the program counter block 10 and the frequency counter 16 according to the FS. Note that the prescaler block 9, the program counter block 10,
The frequency counter 16, the controller 28, and the display drive circuit 19 may be interconnected by a data bus.

In the embodiment of the present invention, only the AND gates G1 and G2 and the switch 27 are added to switch the signal and the number of divisions of the prescaler block 9 is fixed. Therefore, a PLL circuit for a synthesizer is used. A dedicated LSI that can be used together with a tuner and a tuner using the variable condenser 24 and the OSC 23 can be configured. Further, the circuit scale is hardly changed, and the sharing of the dedicated LSI for both increases the mass production effect and reduces the cost. Further, even when the variable condenser 24 and the OSC 23 are used, since a separate prescaler is not required, the number of components is reduced as compared with the conventional case, and the cost is further reduced. In this case, since no input signal is supplied to the program counter block 10, power consumption is reduced.

[0029]

As described above, according to the present invention, a low-cost tuner semiconductor which can be used in both a tuner device using a PLL circuit for a synthesizer and a tuner device using a variable condenser with a small number of components. Equipment can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a tuner semiconductor device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a tuner semiconductor device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional tuner semiconductor device.

FIG. 4 is a block diagram showing a configuration of a conventional tuner semiconductor device.

[Explanation of symbols]

 9: Prescaler block, 10: Program counter block, 15, 28: Controller, 16: Frequency counter, 27: Switch, G1, G2: AND gate, G3: Inverter.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 1/26

Claims (3)

(57) [Claims] 1. A prescaler to which an output signal of a local oscillator of a tuner and a selection signal are input, and that divides and outputs the output signal of the local oscillator by the number of divisions selected by the selection signal; An output signal of the prescaler is input to an input terminal of the first scaler, a first control signal is input to a second input terminal of the prescaler,
When the control signal is at a first level, the signal at the first input terminal is output to a first output terminal, and when the first control signal is at a second level, the signal at the first input terminal is output. A switching circuit for outputting to the second output terminal, an input terminal connected to the first output terminal of the switching circuit, for outputting a signal obtained by counting a signal from the input terminal, and according to the counted value; A counter for outputting the selection signal, a phase detection circuit for detecting a phase difference signal between an output signal of the counter and a reference signal, and a counter output when the first control signal is at the first level. A gate circuit for supplying the selection signal to the prescaler; an input terminal connected to the second output terminal of the switching circuit;
A frequency counter that outputs a value obtained by counting the frequency of the input signal; and a display unit that displays a reception frequency in accordance with an output signal of the frequency counter, and, when the local oscillator forms a PLL circuit, outputs the first control signal. A tuner semiconductor device comprising: a controller for setting the first level and setting the second level in other cases. 2. The switching circuit has a third input terminal to which an IF signal of the tuner is input. When the first control signal is at a first level, the switching circuit outputs a signal from the third input terminal. 2. The tuner semiconductor device according to claim 1, wherein the signal is output to the second output terminal. 3. The switching circuit has a third input terminal to which an IF signal of the tuner is input, and a fourth input terminal to which a second control signal is input. When the signal is input, the signal of the third input terminal is output to the second output terminal in preference to the case of the second level of the first control signal, and the controller selects a broadcast station. 2. The tuner semiconductor device according to claim 1, wherein when it is determined that the broadcast has been performed, the second control signal is output and it is also determined that the broadcast is selected by the IF signal.