JPS62277816A - Coding circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of the entire circuit, to facilitate the large scale integration of the titled circuit and to attain the miniaturization by fulfilling a clamp function outputting a base level of an input signal while arranging the levels to a constant value digitally at the post-stage of an A/D conversion means. CONSTITUTION:An analog video signal (a) including periodically a base level signal and a sampling clock (b) having a sufficiently high frequency area inputted. The analog video signal (a) are inputted to an A/D converter 3 via a low pass filer 1 and an amplifier 2 and converted into a digital signal synchronously with the clock (b). A digital value Y latched in a latch circuit 5 in a timing is subtracted from a digital value X from a latch circuit 4, generated one after another, in the subtracter 6, and its result of subtraction Z is a coded digital output. Thus, the clamp function is realized while using a digital circuit offering ease of large scale circuit integration mainly to attain the miniaturization.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to an encoding circuit that digitally encodes an analog signal, and in particular, the present invention relates to an encoding circuit that digitally encodes an analog signal. This invention relates to an encoding circuit that uses an analog signal that fluctuates accordingly.

[Prior Art 1] When digitally encoding analog video signals, etc., conventionally, an encoding circuit as shown in FIG. 3 has been used.

In FIG. 3, the input conditions for the A/D converter (3) are such that the range of the input analog signal is usually determined by the A/D converter used. If the input analog signal is a signal whose average DC component changes depending on the information, such as a video signal, and has already been AC coupled,
First, to prevent aliasing noise after analog demodulation, the input signal is passed through a low-pass filter (1), and then the reference position of the input signal is fixed at a predetermined level in order to match the input range of the A/D converter (3). The DC component is regenerated through the clamp circuit (21), and an amplifier (
2) is used. This low-pass filter (1), clamp circuit (
21>, the order of the amplifiers (2) may be different from that shown in FIG. 3, but they are both formed horizontally by analog circuits.

[Problems to be Solved by the Invention] As described above, in the conventional encoding circuit, the A/D converter (3) is used to adjust the base level signal periodically included in the analog input signal to a constant level. An analog clamp circuit (21) is provided at the front stage of the circuit, and this analog circuit has been a major cause of deterioration of signal quality. When digital transmission of video signals is assumed, the transmission quality depends only on the analog part of the circuit, so a highly accurate and high-performance analog clamp circuit is required. However, it is not easy to make such a high-performance analog clamp circuit inexpensive and implement it as an SI, and it has not been possible to achieve smaller size, lower price, and higher performance.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to provide a compact, high-performance, and inexpensive encoding circuit that also realizes the above-mentioned clamping function mainly using a digital circuit that can be easily integrated into an LSI. It's about doing.

[Means for solving the problem 1] Accordingly, in the present invention, an analog input signal containing a base level signal periodically is A/D converted without passing through an analog clamp circuit. Base level latch means for latching the digitized signal every input period of the base level signal; and digital subtraction means for subtracting the base level value latched by the latch means from the output signal value of the A/D conversion. and has been established.

[Operation] Even if the base level of the analog input signal fluctuates, by subtracting the base level value from the A/D conversion output signal value in the digital subtraction means, the base level of the digital output signal as a result of the subtraction is changed. is always one step ahead. In other words, the function of the above-mentioned clamp circuit is realized through digital processing.

[Example] FIG. 1 shows a circuit configuration of an embodiment of the present invention.

An analog video signal (a) containing a base level signal (synchronization signal) and a numbering clock (b) of a sufficiently high frequency are periodically input to this circuit.

The analog video signal (a) is passed through a low-pass filter (1) and an amplifier (
2) is input to the A/D converter (3>), and the clock (
b) is converted into a digital signal in synchronization with This A/
The input range of the D converter (3) is the AP of the video signal (a).
The width is large enough to cover fluctuations in L (average image level).

The output signal of the A/D converter (3) is successively applied as the minuend input X of the subtracter (6) via a latch circuit (4) synchronized with the clock (b).

In addition, A/D that occurs one after another in synchronization with clock (b)
Of the output signals of the converter (3), the timing (
Base level signal input period) signal or latch circuit (5)
latched to. This latched (IaY is the reducer (
This is the subtraction input for 6>.

In other words, in the subtracter (6), the latch circuits (
At a certain timing, the digital value Y wrapped in the latch circuit (5) is subtracted from the digital value X from 4), and the subtraction result Z becomes the encoded digital output.

Next, the latch circuit (details regarding the latch timing of 5>) will be explained.

FIG. 2 shows an example of the waveform of the video signal g processed by this circuit. Part 8 in the figure is the base level signal (sync signal @), which is the lowest level part of the video signal. Although this base level changes slightly with APL fluctuations, the following clamp function compensates for this fluctuation and keeps it constant.

First, in order to discriminate the base level signal of part 8, the first reference value N is set in the register (7), and the comparator (8) compares this N with the above-mentioned subtraction output Z. It is determined that it is a base level signal, and the comparator (8) outputs a 1 (1J# low signal).

In addition, at the start of operation, etc., the output ItTI of the latch circuit (5)
Y is random, and as a result, there is always a case where Z<N does not hold even in the base level signal.

In order to eliminate malfunctions caused by this, the ``-'' limit of the video signal is set in the M8 register (9), and this M is compared with the subtraction output Z using the comparator (10). When Z>M, the comparator (10) outputs a signal of ``1''.

In normal operation, the comparator (8) detects the input period of the base level 1 where 7<N, and the output (No. 2 is "1°").
'become. At this time, a signal obtained by appropriately dividing the clock (b) with a frequency divider (11) is generated by an AND gate (12) of several pulses.
) and is input as a timing signal to the latch circuit (5) via the OR gate (13). In other words, during the input period of the base level signal of the video signal, the A/D
The conversion signal is latched by the latch circuit (5) and becomes the subtracted value Y. When a regular video signal portion is input following the base level signal, the above-mentioned 1st Y is subtracted from the A/D converted signal X, and a digital output Z is obtained. This means that the base level signal has become zero.

If Z<N does not hold when the base level signal is input, then Z>M when the high level signal is input, and the comparator (1
The 14111 signal from 0) becomes the timing signal for the latch circuit (5), and the large (!') A/D conversion value at this time is latched by the latch circuit (5). As the latched value Y increases, Z=X-Y becomes small, and when a base level signal is input, the state is automatically drawn into a state in which Z is reduced to N, that is, a normal operating state.

Note that the means for operating the latch circuit (5) when the base level signal is input is not limited to the embodiment, and can be implemented in various ways. Further, in the subtracter (6), a constant value may be added to the subtracted value, or other operation r5 processing may be performed as necessary.

Effects of the Invention] As explained above in detail, in the present invention, the clamp function that outputs the base level of the input signal while keeping it constant is the A/D'! Since the processing is done digitally after the A/D conversion means, the analog circuit before the A/D conversion means is simplified, which has the effect of improving the reliability of the entire circuit.
It becomes easy to integrate into I, and small, high-performance encoding circuits can be manufactured at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encoding circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, and FIG. 3 is a block diagram of a conventional encoding circuit. In the figure, (3) is an A/D converter, (5) is a latch circuit, and (6) is a subtracter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent: Masuo Oiwa, patent attorney (and 2 others)

Claims (1)

[Claims] (1) A/D conversion means for periodically converting an analog input signal containing a base level signal into a digital signal; base level latch means for latching the digital signal every input period of the base level signal; and digital subtraction means for subtracting the base level value latched by the latch means from the output signal value of the A/D conversion means.