SPECIFICATION
Method of and apparatus for producing a differential PCM signal The present invention relates to a method of, and apparatus for producing a differential PCM signal.
Ordinary PCM signal processing is performed through digitalcoding of sampled values of an analog signal, and there is also known a OPCM (Differential Pulse Code Modulation) system to process a signal as differences between the sampled values. In the DPCM system, signal compression is achieved because the difference between the current PCM data and the previous PCM data is used. Therefore, though a 16-bit signal processing circuit is generally required for a 16-bit PCM signal processing system, with a DPCM signal processing system the required number of bits can be reduced to correspond to such compressed bit length.
Although the above bit compression effect is valid in a low frequency range, it becomes less effective with increasing signal frequency and this effect disappears from a practical standpoint when the signal frequency becomes as high as 1 /6 the sampling frequency with the level represented by the PCM signal and the level represented by the DPCM signal then becoming equal to each other.
It is an object of the present invention to provide the method and apparatus for producing differential PCM signals capable of achieving the bit compression effect of DPCM over a wide frequency band.
Another object of the present invention is to provide the method and apparatus for converting a digital signal to an analog signal which is capable of achieving the bit compression effect of DPCM over a wide frequency band.
According to a first aspect of the present invention, there is provided a method of producing a differential PCM signal comprising the steps of:
receiving a first PCM data signal which has a sampling frequency of fs; over-sampling said received PCM data signal and generating a second PCM data signal which has a sampling frequency of n x fs (where n is a positive integer greater than 1); and producing a differential PCM data signal from said second PCM data signal.
This aspect of the invention also provides apparatus for producing differential PCM signal comprising:
a first means for receiving a first PCM data signal which has a sampling frequency of fs; a second means arranged to receive the output of said first means and to over-sample said first PCM data signal and generate a second PCM data signal which has a sampling frequency of n x fs (where n is a positive integer greater than 1); and a third means arranged to receive the output of said second means and to produce a differential PCM data signal from said second PCM data signal.
According to a second aspect of the present invention, there is provided a method of converting a digital signal to an analog signal comprising the steps of:
receiving a first PCM data signal which as a sampling frequency of fs; over-sampling said first PCM data signal and generating a second PCM data signal which has a sampling frequency of n x fs (where n is a positive integer greater than 1); producing a differential PCM data signal from said second PCM data signal; and converting said differential PCM data signal to an analog signal.
This aspect of the invention also provides apparatus for converting a digital signal to an analog signal comprising:
a first means for receiving a first PCM data signal which has a sampling frequency of fs; a second means arranged to receive the output of said first means and to over-sample said first PCM data signal and to generate a second PCM data signal which has a sampling frequency of n ' fs (where n is a positive integer greater than 1); a third means arranged to receive the output of said second means and to produce a differential PCM data signal from said second PCM data signal; and a fourth means arranged to receive the output of said third means and to convert said differential PCM data signal to an analog signal.
The invention will be further described with reference to the accompanying drawings, in which: FIG. 1 is a diagram for explaining bit compression in DPCM; FIG. 2 is a diagram illustrating a case where the bit compression effect is non existent; FIG. 3 is a diagram showing the frequency dependency of bit compression; FIG. 4 is a block diagram showing an embodiment of the present invention; FIGS. 5A to 5C are explanatory diagrams for describing the operation performed in the embodiment of FIG. 4; and FIG. 6 is a circuit diagram showing an example of D/A converter for use in the embodiment of FIG. 4.
An embodiment of the present invention will be described below in detail with reference to FIGS. 1 to 6.
First, a description of DPCM will be given with reference to FIGS. 1 to 3.
As shown in FIG. 1, DPCM data D1' (0011) is obtained from the current PCM data D, (1000) and the previous PCM data D2 (0101).
The DPCM data D2' (0010) is obtained from the current PCM data D2 (0101) and the previous PCM data D3 (0011), and so on.
Referring to FIG. 2, the dashed line represents an analog wave-form which has been converted from PCM data, and a signal which has a frequency of 1/6 the sampling frequency. The solid line represents an analog wave from converted from DPCM data corresponding to such PCM data, and it can be observed that the peak values of the DPCM data and the PCM data are equal to each other and the phase difference of sampling points of the samples having the indicated peak values are illustrated. With regard to the bit compression in this case, since the peak values are equal, it follows that the bit compression effect is zero at a signal frequency which is 1/6 the sampling frequency.Accordingly, if, for example, the processing bit length for the DPCM signal is chosen to be 10 bits with a sampling frequency of 44.1 kHz as in the compact disk system, then, as shown in FIG. 3, a resolution of 16 bits is obtained at a signal frequency of 115 Hz and a resolution of 13 bits is obtained at 920 Hz. However, the resolution is lowered to 10 bits at a signal frequency of 7.35 kHz (44.1 kHz/6), and therefore, the quantization error in such high frequency range becomes non-negligible.
FIG. 4 shows the circuit configuration of the present embodiment in which a double oversampling filter 1 which may be, for example, a digital filter supplies its output to a subtraction circuit 2, which may be, for example, a signal processing means which supplies its output to a D/A converter 3.
Prior to application of PCM data having a sampling frequency fs as shown in FIG. 5A to the over-sampling filter 1, the PCM data has inserted "0" data at intervals of 1/2 fs as shown in FIG. 5B. Therefore, this PCM data is considered to have an apparent sampling frequency of 2fs. Then, when such PCM data is passed through the over-sampling filter 1, the portions inserted with "0" data are provided with interpolation. Generally, if filtering is executed with an n-fold over-sampling filter on PCM data with (n - 1) "0" data inserted therein, equivalent output data of n times the sampling frequency can be obtained.
When such data is fed to the subtraction circuit 2 where it is subjected to the DPCM processing as described in FIG. 1, the quantization: error can be reduced and in the case of two-fold over-sampling can be reduced by at least 6 dB as compared with ordinary DPCM. In this embodiment, there is further provided the D/A converter 3. Since a 16-bit D/A converter is usually used in digital audio equipment such as a compact disk system there is the disadvantage in that the production cost is high due to difficulties arising in IC design and manufacture. However, the human aural response is lower for a high frequency signal and also the source medium such as a disk does not include components of frequencies higher than about 10 kHz so the signal principally includes medium and low frequency components.This means that the 16 bits used in the current D/A converter are not necessary for all the components of the pass band.
Thus, it is known that the resolution can be reduced for high frequency signals which do not have so great an amount of information for the human aural response. Accordingly, if a 10-bit D/A converter, for example, is provided as the D/A converter 3 in FIG. 4, resolution of 14 to 16 bits can be obtained in the medium and low frequency ranges (which is approximately 220 to 920 Hz) by driving the apparatus at a two-fold (88.2 kHz) or four-fold (176.4 kHz) sampling frequency as shown in FIG. 3. In addition, the deterioration in the resolution in the high frequency range (approximately 3.7 to, 7.4 kHz) can further be suppressed as compared to a conventional arrangement.For example, as shown in FIG. 3, when the signal frequency is 7.35 kHz, the resolution at a sampling frequency 44.1 kHz is 10 dB, but the resolution is increased to 11 dB at a two-fold sampling frequency of 88.2 kHz or to 12 dB at a four-fold sampling frequency of 176.4 kHz. From this data it is apparent that it is possible to enhance the resolution and achieve a bit compression effect even in a high frequency range by increasing the sampling frequency.
The resolution of a high-accuracy precision D/A converter designed for present MOS processes is 10 bits or so, and a 16-bit converter can be designed only by using the bipolar process which results in a power consumption problem. By employing the present invention, however, it becomes possible to design a highly accurate D/A converter using the MOS process, with no trimming being required.
According to the present invention, as described hereinabove, input PCM data is oversampled to generate n-fold data, which is then processed to obtain differential-PCM data, so that the bit compression effect of differential PCM is achieved over a wide frequency band.
In the case of double over-sampling, for example, the quantization error can be reduced by in excess of 6 dB to allow a corresponding reduction in the hardware required.
For the D/A converter 3, the arrangement shown in FIG. 6, for example, can be used. In this device, DPCM data from the subtraction circuit 2 is converted, to an analog signal having an analog value corresponding to the DPCM data in the digital to analog converter 31. The signal from converter 31 is fed through a resistor 32 to a deglitcher circuit 33 having a gate terminal 34 to which a deglitching pulse is supplied. The output from the deglitcher circuit 33 is integrated in an integration circuit 35, to produce an analog signal corresponding to the original PCM data which is supplied to an output terminal 36. The integration circuit 35 includes an amplifier and a feedback capacitor.
In providing DPCM data, a predictive filter for producing a predicted value from the previous and following few sampled data may be used in place of the subtraction circuit 2.
Although the invention has been described with respect to preferred embodiments, it is not to be so limited as changes and modifications can be made which are within the full intended scope of the invention as defined by