JP2744006B2 - Nonlinear A / D conversion circuit and non-linear A / D conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a non-linear A / D conversion circuit and a non-linear A / D for converting an analog signal into a digital signal by performing logarithmic compression and noise reduction. Regarding the conversion method.

(Prior Art) Generally, in a system that converts an analog signal into a digital signal, performs digital processing, and converts the analog signal back into an analog signal, a companding rule is used in order not to lose the dynamic range of the analog signal. . Thereby, for example, in the case of a transmission system, amplitude information exceeding the dynamic range inherent to the system can be transmitted. For example, according to the logarithmic compression of 1: 2, transmission with a dynamic range of 100 [dB] (= 2 × 50) is possible using a transmission system with a dynamic range of 50 [dB].

Further, in a system for digitally processing an audio signal of an audio device or the like, noise components can be prevented from being mixed into the digital signal after A / D conversion by the companding.

As a method of converting an analog signal into a digital signal by noise reduction, the following two methods can be considered. That is, as shown in FIG. 3, a method in which a noise reduction circuit 31 is provided before the A / D converter 32, and as shown in FIG. 4, a noise reduction circuit 42 is provided after the A / D converter 41. Method. The noise reduction circuit 31 in the former case is configured by an analog circuit, and the noise reduction circuit 42 in the latter case is configured by a digital circuit.

The analog noise reduction circuit in the system shown in FIG. 3 is configured as shown in FIG. 5, for example.
In FIG. 5, reference numeral 51 denotes an operational amplifier called a main operational amplifier; 52, a gain control amplifier (GCA) whose gain is controlled in accordance with the level of an input signal;
Constitutes a feedback circuit 53 and supplies its output to the inverting input terminal of the operational amplifier 51 so that an analog input signal entering the non-inverting input terminal of the operational amplifier 51 obtains an output in which the analog input signal is logarithmically compressed. I have. The feedback circuit 53 includes an emphasis circuit 54, a weighting circuit 55, a level sensor 56, and the gain control amplifier 52. Emphasis circuit 54
Is a filter circuit having a low-pass characteristic, and outputs an output to an inverting input terminal of the operational amplifier 51 via a gain control amplifier 52. The weighting circuit 55 has a characteristic substantially opposite to that of the emphasis circuit 54, and generates a level signal that varies the gain of the gain control amplifier 52 in accordance with the proportion of the output of the operational amplifier 51 occupying the high frequency range. Level sensor 56
Converts the level signal from the weighting circuit 55 to logarithmic conversion and outputs the result through the capacitor 57. As a result, the gain control amplifier 52 performs logarithmic expansion of the signal from the emphasis circuit 63 and feeds back the signal to the operational amplifier 51.

In the above circuit configuration, the transfer function between input and output is H (s),
The transfer function of the noise reduction signal forming unit 53 is represented by F
(S), assuming that the gain of the operational amplifier 51 is A, Is represented by If A is sufficiently larger than 1, H (s)
Is represented by the reciprocal of F (s), Becomes Since F (s) has a logarithmic expansion characteristic, a signal having a magnitude of, for example, 10 [dB] is supplied to the gain control amplifier 52 for 10 [d].
B] If it did, the output level would have increased by 20 [dB] and would have been a logarithmic extension of 1: 2. From the formula, H (s) is the reciprocal of F (s), so that it exhibits logarithmic compression characteristics as output characteristics. It would be nice if there was a range. If an analog signal having such characteristics is converted into a digital signal by the A / D converter 32, a noise-reduced digital signal can be obtained. In this case, the A / D converter 32 does not need to be highly accurate because the analog signal is subjected to noise reduction processing.
A normal one such as an integral type can be used. For example
The A / D conversion accuracy required to obtain a dynamic range of 80 [dB] (corresponding to 14-bit accuracy) is only required to be 40 [dB] (corresponding to 7 bits). Also, as shown in FIGS. 8 and 9, a feedback type using a Δ-Σ modulator may be used.

However, the circuit shown in FIG.
In particular, since the time constants of the emphasis circuit 54 and the weighting circuit 55 are made of CR, it is conceivable that the performance may be deteriorated due to variations in characteristics or changes over time.

FIG. 6 shows an A / D conversion circuit configured based on FIG. In FIG. 6, the A / D converter 41
Analog input signals are directly converted to digital signals,
The conversion output is a digital circuit noise reduction circuit.
At 65, the same noise reduction processing as in FIG. 5 is performed. That is, the digital noise reduction circuit 65 includes a divider 61, a level sensor 62, an emphasis circuit 63, and a weighting circuit 64. The output of the A / D converter 41 is supplied to a divider 61, and the noise reduction output is divided by a signal passed through a feedback path by a weighting circuit 64 and a level sensor 62. The output that has been subjected to the division processing is an output that has undergone noise reduction via the emphasis circuit 63.

The emphasis circuit 63 and the weighting circuit 64
It can be configured by an IIR (Infinite Impulse Response) type digital filter as shown in the figure. FIG. 7 is composed of adders 71 and 72 connected in series, a delay circuit 73 and coefficient units 74 and 75. The delay circuit 73 outputs the output of the adder 71 to the adder 71 via the coefficient unit 74. The signal is fed back to the adder 72 via a coefficient unit 75. By setting the coefficients of the coefficient units 74 and 75 to predetermined values, such digital filters can easily realize emphasis characteristics and weighting characteristics, and are optimally designed compared to analog circuits. As long as the characteristics are not deteriorated over time, excellent characteristics can be obtained without variation in initial characteristics.
However, before performing the noise reduction encoding process
Since AD conversion is performed, the accuracy required for AD conversion becomes severe. For example, in order to obtain a dynamic range of 80 [dB], naturally 14-bit accuracy is required. Further, the same calculation accuracy is required for the noise reduction circuit 65 (digital signal processing unit), and the circuit scale of the digital signal processing unit is increased in addition to the necessity of the divider.

In FIGS. 5 and 6, the A / D converters 32 and 41 are of successive approximation type, flash type, integral type, or Δ−
AA / D converter using a modulator can be used.

FIGS. 8 and 9 show feedback type A / D converters called oversampling types using the above-mentioned Δ-Σ modulator. More specifically, FIG. 8 shows a double integral type having two integrators, 81 is a subtractor for calculating a difference between an analog input signal and an output signal which is a feedback signal, and 82 is a subtractor.
An integrator that integrates the signal from 81, 83 is a subtractor that calculates the difference between the signal from the integrator 82 and the output signal, and 84 is a subtractor 83
Integrator that integrates the signal from, 85 is the sampling signal fs
Is a comparator that performs a comparison operation, and the comparator 85 feeds back the output to the subtracters 81 and 83. The output of the comparator 85 is thinned out by a thinning filter 86 to eliminate aliasing noise. FIG. 9 shows a single integrator composed of a subtractor 91 for subtracting an input signal and an output signal, an integrator 92, a comparator 93 and a thinning filter 94. These circuits use a comparator 85 encoded with the sampling signal fs.
Since the difference between the output of (93) and the input signal is integrated,
The pulse frequency of the obtained digital signal changes according to the amplitude of the input signal, and since the integrator is not in the feedback path but in the input / output path, it must accumulate quantization noise due to noise as in the Δ modulation method. There is an advantage that there is no.

Note that such a Δ-Δ modulator is described in, for example, the document “A Us
e of Double Integration in Sigma Delta Modulation "
JCCandy, IEEE Trans.COM-33, No.3P.P.249-258 Mar.
Shown in 1985.

(Problems to be Solved by the Invention) The conventional nonlinear A / D conversion circuit has two methods of performing noise reduction processing before A / D conversion or performing noise reduction processing after A / D conversion. In the former, noise reduction processing is performed by an analog circuit, so characteristic variations unique to the analog circuit occur in the emphasis circuit 54 and the weighting circuit 55. In the latter, the number of A / D conversion bits increases, and the digital signal processing unit However, there is a disadvantage that the circuit scale becomes large.

An object of the present invention is to provide a non-linear A / D conversion circuit and a non-linear A / D conversion method capable of eliminating the above problems, reducing the number of bits of A / D conversion, and reducing variations in characteristics. .

[Constitution of the Invention] (Means for Solving the Problems) A non-linear A / D conversion circuit according to the present invention comprises an arithmetic unit, an integrator, and a comparator, and Δ- ア ナ ロ グ modulates an analog signal to obtain an amplitude of the analog signal. A / D conversion means of a feedback type for obtaining a digital signal whose pulse frequency changes proportionally,
A gain control amplifier connected to the feedback loop of the / D conversion means,
The digital signal from the A / D converter is digitally processed and output, and an analog voltage for logarithmically converting the feedback signal fed back in the feedback loop is generated from the result of calculating the output characteristic, and this voltage is used to generate the analog voltage. Digital signal processing means for performing a logarithmic expansion operation on the gain control amplifier.The nonlinear A / D conversion method according to the present invention integrates a difference between an input analog signal and a feedback signal, and calculates an integration result. By performing a comparison, a digital signal whose pulse frequency changes in proportion to the amplitude of the analog signal is obtained, a predetermined gain is given to the obtained digital signal, and the digital signal is fed back as the feedback signal. An output procedure for digitally processing the obtained digital signal and outputting the digital signal, and calculating an output characteristic, based on a calculation result of the output procedure. Then, a step of generating an analog voltage for logarithmically converting the feedback signal in the conversion procedure, and a step of logarithmically extending the gain of the feedback signal by the analog voltage generated by this procedure are provided.

(Operation) Since the present invention has a configuration in which a gain control amplifier whose gain is controlled by a logarithmic expansion characteristic is provided in the feedback path of the Δ-Σ modulator, the logarithmically compressed analog signal is Δ-Σ modulated. That is, variation in noise reduction characteristics is small, and the number of A / D conversion bits is small.

Hereinafter, the present invention will be described with reference to the illustrated embodiments.

FIG. 1 is a circuit diagram showing one embodiment of a nonlinear A / D conversion circuit according to the present invention.

First, a terminal 1 is a terminal for introducing an analog signal 1a, and a signal 1a from this terminal 1 is input to a subtractor 2. The subtractor 2, the integrator 3, the subtractor 4, the integrator 5, and the comparator 6 constitute the double integral type Δ-Σ modulator described with reference to FIG. The present embodiment is characterized in that a gain control amplifier 7 is provided in the feedback path of this modulator.

That is, the subtracter 2 supplies a subtraction signal of the signal 1a and the feedback signal 7a from the gain control amplifier 7 to the next-stage integrator 3, and the subtractor 4 outputs the signal from the integrator 3 and the gain control amplifier 7 Is supplied to the next-stage integrator 5. The comparator 6 that performs a comparison operation based on the sampling signal fs feeds the modulation output 6a back to the gain control amplifier 7 and supplies the data to a thinning filter 8 that thins out data. The thinning-out filter 8 thins out data from the modulation output 6a by sampling the modulation output 6a with a signal whose sampling frequency fs has been reduced to an integral number. The output of the decimation filter 8 is
A digital output signal 9a whose band is limited by a low-pass characteristic is derived from a terminal 13 via an emphasis circuit 9 composed of a digital filter.

The digital output signal 9a is a pulse train signal whose pulse density changes according to the amplitude of the analog input signal. Thus, the digital output signal 9a is also supplied to a weighting circuit 10 having a digital filter configuration, and is subjected to band limitation by high-pass characteristics. The weighting circuit 10
When the input digital output signal 9a contains many high-frequency components, it outputs a digital signal that indicates the level of the high-frequency components and suppresses the gain of the gain control amplifier 7.
The next-stage level sensor 11 detects the level indicated by the digital signal from the weighting circuit 10, logarithmically converts it, and outputs the result. This logarithmic conversion output is also a pulse train signal in which the pulse train density changes according to the weighting level.
The level sensor 11 smoothes out the pulse train signal by providing a smoothing capacitor 12 on the output side. The voltage from the smoothing capacitor 12 is supplied to the gain control amplifier 7 as a gain control signal 11a, and the gain is controlled so that the gain control amplifier 7 performs logarithmic expansion.

In the above configuration, the input / output characteristics of the Δ-Σ modulator
Assuming that the input (1a) is x and the output (modulation output 6a) is y, they are related by the following equation: y = x + (1 + Z ⁻¹ ) ² E. Here, E is quantization noise.
This equation is generally called a noise shape characteristic. If the second term on the right side is sufficiently small, y = x, and the input and the output are equal. In other words, the feedback is applied so that the input and the output are equal.

When such a property is utilized, by providing the gain control amplifier 7 in the feedback path as in the present embodiment, a characteristic opposite to the characteristic of the gain control amplifier 7, that is, a Δ-Σ modulator having a logarithmic compression characteristic can be obtained. Be composed.

If the modulation output 6a obtained from the comparator 6 is a logarithmically compressed signal, the digital signal processing circuit constituted by the thinning filter 8, the emphasis circuit 9 and the like is different from the digital system having the configuration as shown in FIG. , Half the number of bits. For example, 80 [d
Conventionally, a 14-bit division process was required to obtain a dynamic range of [B] (14 bits), but according to the present embodiment, an accuracy of 40 [dB] (7 bits) is sufficient. In addition, since a division circuit is unnecessary, the number of circuits can be greatly reduced. In addition, since the wetting circuit 10 and the emphasis circuit 9 can be constituted by digital filters, a temporal change and initial variation in filter characteristics are removed in principle.

 Next, another embodiment will be described.

FIG. 2 is a block diagram showing another embodiment of the present invention.
In the present embodiment, a single integration method is adopted instead of the double integration method. In FIG. 2, the same circuit elements as those in FIG. 1 are denoted by the same reference numerals and described. A subtracter 12, an integrator 13, and a comparator 14 constitute a single integral Δ-Σ modulator. The gain control amplifier 7 is connected to the feedback path between the output terminal of the comparator 14 and the subtractor 12.
The gain control amplifier 7 is controlled by a gain control signal 11a based on a level signal from a digital signal processing circuit having the same configuration as that of FIG. This gain control signal 11a is also a signal that has undergone logarithmic conversion by the level sensor 11.

The input / output relational expression of the single integral type Δ-Σ modulator is as follows: y = x + (1−Z ⁻¹ ) E. Although the second term on the right-hand side is different from the equation in that the second term is primary rather than quadratic, the input / output characteristics exhibit logarithmic compression characteristics and reduce the number of operation bits of the digital signal processing circuit, as in the embodiment of FIG. can do. However, since the second term on the right side of the equation is linear, it is necessary to perform sampling at a higher operating frequency to obtain the same S / N as in the embodiment of FIG. For example, if the band is 15 [KHz] and the S / N is 80 [d
In order to obtain the signal of [B], the sampling frequency of 2 [MHz] is sufficient in the double integral type, but 12 [MH] in the single integral type.
z] is required. However, according to this embodiment, since the accuracy of A / D conversion can be 7-bit accuracy, S / N is 40
[DB] is fine. In order to obtain an S / N of 40 [dB] in the single integration type, a sampling frequency of 1 [MHz] is sufficient, and the circuit of FIG. The scale can be reduced.

[Effects of the Invention] As described above, according to the present invention, A / D conversion with good noise reduction characteristics can be performed without increasing the circuit scale of signal processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a nonlinear A / D conversion circuit according to the present invention, FIG. 2 is a block diagram illustrating another embodiment of the present invention, and FIG. 3 and FIG. FIG. 5 is an explanatory diagram illustrating an A / D conversion method, FIG. 5 is a configuration diagram illustrating a conventional A / D conversion circuit, FIG. 6 and FIG. 7 are configuration diagrams illustrating another conventional configuration, FIG. FIG. 9 is a configuration diagram illustrating a Δ-Σ modulator. 2,4 ... Subtractor, 3,5 ... Integrator, 6 ... Comparator,
7: gain control amplifier, 8: thinning filter, 9:
... Emphasis circuit, 10 ... Weighting circuit, 11 ...
... level sensor.

Claims (2)

(57) [Claims] A feedback A / D converter comprising an arithmetic unit, an integrator, and a comparator for Δ-Σ modulating an analog signal to obtain a digital signal whose pulse frequency changes in proportion to the amplitude of the analog signal. A gain control amplifier connected to a feedback loop of the A / D converter, digitally processing and outputting a digital signal from the A / D converter, and performing feedback in the feedback loop based on a result of calculating the output characteristic. A digital signal processing means for generating an analog voltage for logarithmically converting the feedback signal to be applied and performing logarithmic expansion of the gain control amplifier with the voltage. 2. A digital signal whose pulse frequency changes in proportion to the amplitude of the analog signal by integrating the difference between the input analog signal and the feedback signal and comparing the integration results. A conversion procedure for giving a predetermined gain to the signal and feeding it back as the feedback signal; an output procedure for digitally processing and outputting the digital signal obtained by the conversion procedure and calculating an output characteristic; A step of generating an analog voltage for logarithmically converting the feedback signal of the conversion procedure based on the calculation result; anda step of logarithmically extending the gain of the feedback signal by the analog voltage generated by the procedure. Characteristic nonlinear A / D conversion method.