JPS6039924A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain a high S/N with a low quantized accuracy by forming a quantized output into a tri-state level and spreading a DC converted error with a pulse signal so as to change over the full scale of a D/A converting circuit depending on the magnitude of the input signal level. CONSTITUTION:An input analog signal is added to an output from a pulse generator 10 at an adder 2, subtracted with a velue D/A-converting (6) an output of a quantizer Q4 sampling signals in a frequency higher than an input frequency, and the result is inputted to an integration device 3. An integrated output signal is quantized into three levels, a reference voltage VREF1 or over, a middle value between VREF1 and VREF2, and the VREF2 or below by two voltage comparators 12A, 12B of a quantizer 4 and outputted to a digital filter DF7 and the D/A converter 6. The DF7 eliminates a pulse signal spreading a DC converting error from the generator 10 and outputs a digital signal corresponding to the input analog signal. The output signal is detected by a signal amplitude detecting circuit 11 and the full scale of the D/A and the DF7 is changed over into two stages depending on the magnitude of the signal amplitude so as to improve the S/N ratio to a low input level signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention is an auto-transformer that achieves high S/N characteristics with low quantization accuracy by sampling at a very high frequency compared to the input signal frequency band. It relates to sampled analog-to-digital (A/D) converters.

(Prior art) Figure 1 is a block diagram showing the configuration of a conventional auto-sample A/D converter, in which 1 is an analog signal input terminal, 2 is an analog adder, 3 is an integrator, and 4 is a quantizer. 5 is a quantized signal output terminal, 6 is a D/A conversion circuit, 7 is a digital filter, 8 is a digital signal output terminal, and 9 is a clock input terminal.

In such an A/D converter, if the feedback loop that integrates the difference between the input signal and the quantized signal and quantizes this integral value is operated at a very high frequency period with respect to the input signal frequency band, the quantum The noise components of the signal are distributed in a higher frequency band than the input signal frequency band. This is because the quantized signal is determined so that when the difference between the human signal and one quantizer number is averaged at a constant period, the average value is close to zero.

If the high frequency components of the %2 quantizer are removed by the digital filter 7, most of the tones can be removed by quantization, so even if the accuracy of the quantizer is low, a digital signal output with an inferior S/N can be obtained. At this time, as the sampling frequency (operating clock frequency) is made higher than the I/O frequency, the higher the frequency range, the more the sound is distributed, so the S/N in the station wave number band will be lowered.

Generally, the accuracy of a successive approximation type A/D converter that can be realized in an integrated circuit is limited to a resolution of 10 to 12 bits. However, in the configuration shown in Figure 1, even a 1- to 2-bit quantizer
If the sampling frequency is set high, 12 bits or more
It is possible to obtain a conversion accuracy of -. In this case D/A
The conversion circuit 6 may also have a resolution of 1 to 2 bits.

FIG. 2 shows the S/N characteristics of the auto-sample A/D converter shown in FIG. Here, the S/N was calculated under the following conditions.

Condition sampling frequency 2.048M
Hz signal frequency −・・・−・−・・・・・・・・−1
kHz.

S/N evaluation band ・・・・・・・・・・・・・・・
・0~4kH7 quantizer resolution ・・・・・・・・・・・・
...1-bit D/A conversion circuit resolution ...
...If we normalize the 1-bit analog signal input range from -1 to -1, the quantizer 4 is a 1-bit device that determines whether the integrator output is positive or negative, but as shown in Fig. 2. As shown in the figure, the digital output shows a high S/N ratio of 1%. However, as the input level increases, the S/N ratio increases, and signals of −58 dB or lower cannot be distinguished. From this, the Guinamino Cleanse is 58 d.
B is equivalent to an ideal linear 9-bit A/D converter.

FIG. 3 shows the DC conversion error characteristics of the conventional auto-sampled A/D converter shown in FIG. 1 under the above conditions. Since this shows similar error characteristics for positive and negative human inputs, only -positive inputs are shown here. As is clear from 121, it is at zero level.
Large errors occur at close range.

For this reason, an alternating current signal at a low human power level is converted using a large portion of this error, so that the S/N is greatly reduced to 1 at a low input level.

Figure 4 shows the conventional Oha sample A/T) converter.
This is the S/N clarity when having a DC offset I of 45.

If the analog signal input or l)/A conversion circuit is provided with an offset and the input signal is converted around the DC level of 01, for example, S can be greatly improved at a low human power level. Here too, the S/N characteristic at a low human power level is ideally linear 1.
It is equivalent to a 2 to 13 bit A/D conversion circuit. but,
If the DC off-sensor (.) varies, the S/N damage will change greatly.
) When manufacturing converters, integrators, quantizers,
The I)/A conversion circuit has a limit in operating speed, and the horn pre-knob frequency cannot be made even higher. Therefore, high S/N characteristics can be obtained with as low a number of sampling cycles as possible.In the conventional type, the S/N is low without DC offset, and even with DC offset, it is stable because the offset amount fluctuates due to manufacturing variations. However, there was a drawback that a high S/N ratio could not be obtained.

Furthermore, when inputting a 7-bit audio signal, it is difficult to ensure the ideal linear 13-bit A/D converter. This cannot be achieved without increasing the clock further. Furthermore, there is a drawback that a circuit that operates at a frequency of 2.048 MHz or more cannot be easily realized using current integrated circuit technology.

(Purpose of the Invention) In order to solve the above-mentioned conventional drawbacks, the present invention sets the quantization output to three levels to increase the resolution, diffuses the DC conversion error with a pulse signal, and converts the quantization output into three levels by using a pulse signal to spread the DC conversion error. ]) /A converter circuit full scale and can stably obtain high S/N characteristics even with manufacturing variations. It is something.

(Structure and operation of the invention) FIG. 5 is a block diagram showing the structure of an embodiment of the Ohaza Nosol A/l) converter of the present invention, in which 1d is an analog signal input terminal, 2 is an analog converter, 3 is an integrator, 4 is a quantizer, 5 is a quantized signal output terminal, 6 &:t D/A conversion circuit, 7 is a digital filter, 8-digit digital signal output terminal, 9 is a clock input terminal, 10 is a The pulse generator 11 is a signal amplitude detection circuit.

Here, the quantizer 4 is composed of two voltage comparators 12A and 12B and two D-type flip-flops 13A and ]313, as shown in FIG. The comparison reference voltage of 12B is VR Yu]
, is set to the value of VYF2, and the output of integrator 3 is set to +1 to
VREF1. vR11~VREF2IVRU2~-1
It quantizes into three areas and outputs values of +], , O, and -1, respectively. Two D-type flip-frogs 13A and 13B are for latching the outputs of comparators 2A and 1213, and operate at the sampler cycle. When the resolution of the quantizer 4 is set to three levels, a D/A conversion circuit is required to output analog values corresponding to +1°0, -1. The I)/A conversion circuit 6 feeds back the same input as the digital filter 7, and the quantized output +1 and O that can be input to the digital filter: 3 values and the analog value of the output of the D/A conversion circuit 6. If the values are not exactly equal, an error will occur in the digital output obtained at the digital signal output terminal 8.

A D/A conversion circuit that outputs a plurality of analog levels is often configured with a circuit that divides a reference voltage by the ratio of the elements using capacitive elements or resistive elements.

In this case, since the relative accuracy of the element is limited by the manufacturing precision, the analog output value has an error determined by the relative accuracy of the element. However, in order to output a 3-value analog level,
A possible generation method is to switch between three charging methods: charging one capacitive element with the base voltage in the positive direction, charging it in the negative direction, or charging it with the d-ground voltage. In this case, since multiple capacitive elements are not used, the accuracy of the elements is less of a problem. Regardless of the accuracy of ``cutting and manufacturing'', +
D/ that outputs analog levels corresponding to three values of 1°0.
A conversion circuit can be easily realized.

In FIG. 5, by setting the resolution of the quantizer 4 and the D/A converter circuit 0 to three values, it is possible to reduce the noise generated by quantization to 1F or less in the case of two values.

FIG. 7 shows the integrator 3 of FIG. 5 and the analog adder 2 that constitutes its peripheral circuit. A detailed circuit example of each circuit of the D/A converter 6 and the pulse generator 10 is shown. If the integrator 3 is configured using switched capacitor technology, the function of the analog adder 2 can also be realized at the same time. In Fig. 7, ]4 is an amplifier, 15 is an integrating capacitor (CI), 16 is a Zumbling capacitor (C6), and 17 is an I)/A conversion capacitor (
CDA), 1 s is pulse voltage generation capacity (CI)
), SWI~5W12 is a switch, ]9°20,2]
(Cl switch control section, 22 is a frequency divider, 23
The fd signal output terminal is shown. The Suinocito-Gamenta type integrator uses a switch to charge the input terminal into a capacitor, and uses an amplifier (Amp) ]4 to transfer the charge to an integral capacitor (CI).
) 15. Switch SWI~4 and capacitor (C8) 16 are circuits that sample the voltage of analog signal input terminal 1. SWI~4 alternately performs sampling of the input terminal and integration to integral capacitor (CI) ]5 in the sampling period. Let's do it.

SW5 to SW8 and the D/A conversion capacitor (CI) A)]7 are controlled by the switch control unit 20, and the charging direction of the R voltage is changed according to the quantized output to charge the capacitor 17, and the D/A conversion capacitor (CI) A) is
Operates as an A conversion circuit. SW9 to SW12 and the pulse voltage generating capacitor fk (cp) +s are for generating pulse voltages, and charge the vRF and F voltages to the capacitor]8 at the sampling period, and integrate the charges to the integrating capacitor 15. Capacity 18
By switching the charging polarity to the frequency divided by the frequency divider 22, it becomes equivalent to adding a pulse waveform with strong positive and negative amplitudes to the input signal.

If the frequency of this pulse is selected in a band that can be removed by the digital filter 7, no pulse waveform is transmitted to the digital signal output terminal 8, and only a signal corresponding to the analog signal is obtained. Pulse amplitude”XVR
It will be decided by EI"beCP/CI).

The circuit according to the embodiment of the present invention shown in FIG.
This can be realized using analog circuits. The purpose of adding the pulse waveform to the input signal is to diffuse the zero DC level error shown in FIG. When pulse waveforms are added, the DC level that causes an error that is large by the pulse amplitude moves and is dispersed in positive and negative directions, so the width of the error also decreases. As a result, the DC conversion error near the zero DC level becomes small.

The signal amplitude detection circuit 11 detects the amplitude level of the input signal, and switches the full scale of the D/A conversion circuit 6 and the digital filter in two stages depending on the magnitude of the human input signal amplitude to detect low input levels. "S/N direction for signals"
I'm trying to do two things. Switching the full scale of the D/A conversion circuit essentially increases the number of output levels of the conversion circuit.

Therefore, since the accuracy of each output level greatly affects the S/N characteristic, the accuracy of full scale switching is important.

FIG. 88 is a diagram showing a full-scale switching method of the D/A conversion circuit ( ).

This is shown in Figure 7. D/A conversion capacity (ODA) 1
7 capacitance value, 2 capacitance values! 24-1 and 24-2 are connected in parallel using switches 5W13 to SWI5, or connected in series, and switched at a ratio of 40:25. However, the capacitance values of capacitors 24-1 and 24-2 are assumed to be equal. Also, if there are variations in the capacitance values, the accuracy ratio of 1:0.25 mentioned above becomes a problem.
Let the capacitance values of 4-1 and 24-2 be CDI and CD2,
If there is a variation between both capacitance values and that value is ΔC, then C
D2-CDl-ΔC1 Capacitance value when connected in parallel (d(2・
CDI+ΔC), and the capacitance value when connected in series is (CDI・(c
+n+ac))/(2.CDI+ΔC), so the error for the series/parallel ratio ]:025 is as follows.

Therefore, the error El7R is ERR−F −(−R−)2 ・・・・・・−・ (])
2.CDI CI) When manufacturing CD2 as an integrated circuit, it is generally possible to achieve a relative accuracy of about 0.2%. However, as shown in equation (1), the error when switching between series and parallel is 0.2% accuracy CD1. CD2
If this is used, it will be extremely small at 0.0001%.

Conversely, for ERR = 0.2%, CDI, CD2
The relative accuracy of 89% or less is sufficient. This accuracy d is a value that can be easily realized on an integrated circuit.

Switching the full scale of the D/A converter is the eighth step.
It has been explained that high accuracy can be easily realized by using the series/parallel switching circuit shown in the figure, but on the other hand, switching the full scale in a digital filter can be done in capacitance regardless of accuracy. When the series-parallel switching circuit shown in FIG. 8 is used, full scale ('i]: 0.
Since the ratio changes by a factor of 25, it is sufficient to provide a circuit that shifts the input data of the digital filter by 2 bits.

Figure 9 shows a signal level diagram, which shows the relationship between the analog human input signal range A, the integrator output range 3, the comparator judgment level c, and the D/A converter output Pel D1 amplitude detection 144 level E. In the figure, (a
) and (b) show the first and second full scales, respectively.

The output level D of the D/A converter outputs one of three values of ±0.25.0 in a low full scale state, and outputs one of three values of ±1.0 in a high full scale state, depending on the comparator judgment result.
Output one of the values as well.

The full scale of the D/A converter is determined by the amplitude detection circuit.If the input signal amplitude exceeds either VRI or VB2, it is switched to the higher one. When switching the full scale, the comparator judgment level C can be fixed.At a low full scale, the comparator judgment level vRF, F]
, if you set vRyu2 (set "REF' to a value between o and 025 and V□yu2 to a value between 0 and -0.25),
Even at high full scale, VRF, F].

The relationship between vREF2 and the ])/A converter output level is the same as in the case of a low full scale, and normal quantization operation can be performed. ■RIi, F], VR91,,2 value settings are
2. It is effective for SZN at a low human power level because it can be optimized for a low full scale.

FIG. 10 shows the relationship between input signals and full scale switching.

The output period of the digital filter in Fig. 5 is t.
. Then, in FIG. 10, fci L, , L2 . t,・
The output of the amplitude detection circuit changes at the time . In the figure, the range indicated by the broken line is the amplitude detection level VR], VB
2 to 0.25. This is the quantizable range (output range of the D/A conversion circuit) when set to -0.25. At this time,
The full scale switching is delayed with respect to the amplitude change of the input signal 25, and in the portions indicated by A and B, the human input signal amplitude exceeds the quantizable range. On the other hand, the solid line indicates VRI and VB2 of 0.125. When set to -0.125, the full scale switching timing is early within the quantizable range, and does not exceed the quantizable range.

In this way, if VRI and 1VR21 are set smaller than 025, the pupil filter delay can be corrected,
Full-scale switching can follow signal amplitude changes.

The higher the frequency of the human input signal and the longer the output period of the digital filter, the more unreasonable the absolute value of the values of VRI and VB2 must be set.

FIG. 1 shows another embodiment of the oversampled A/D converter of the present invention, and each reference numeral is the same as that shown in FIG. This feature is that the human power of the amplitude detection circuit 11 is obtained directly from the analog signal input terminal 1. In this configuration, the delay in amplitude detection is small i < , VRI, vlt
The absolute value of 2 can be set large.

FIG. 12 shows an example of a signal amplitude detection circuit H used in the A/]) converter shown in FIG. In the figure, 26 is a signal input terminal, 27 and 28 are OR circuits, 29 is a D type flip-flop, and 30 is a /7 clock input terminal. The signal input terminal 726 has a digital signal output terminal 8 shown in FIG.
The upper three bits of the output signal are manually input, and if the signal amplitude is within the range of 0125 to -0125, 00n is output, and if it is outside the range, 11'1 is output. D type, the amplitude detection result of the previous cycle is held by a flip-flop even at a large input level.
It can be a value in the range of 5, so 0.125 to -(
The purpose is to prevent malfunction by outputting II o II when the signal amplitude continues to be within the range 1, ]25.

FIG. 13 shows a signal amplitude detection circuit of the A/D converter shown in FIG.
is an EX-OR circuit, 33 is a signal input terminal, 3/IA and 34B are base thread level terminals.

This circuit receives an analog signal from the analog signal input terminal at the signal input terminal, and adjusts the base thread level VRI.

Two comparators 31A and 3]B with VB2 directly detect the analog input signal amplitude. Compared to FIG. 12, this circuit is not affected by noise because it is a digital circuit, but it is susceptible to noise because it is an analog circuit.

Figure 14 shows the DC conversion error characteristics of the A/D converter in Figure 5, where the pulse amplitude is -0,045, VREF1 = I
VREF21 = 0.0625. ■R] = 1VR
21=0.125, and at a DC level of 0.125 or higher, the error is small because it operates at a low full scale.

15th Figure 11 shows the DC conversion error characteristics of the female converter, pulse amplitude -0,045, VREFI -
1vREF21 = 0.0625. VRI=l
When vR21 is set to 0.2, the range of operation at low full scale is expanded.

Comparing the characteristics shown in FIGS. 14 and 15 with the characteristics of the conventional circuit shown in FIG. 3, it is clear that the error near the zero DC level has been significantly reduced. Moreover, since the error near zero DC level E' is uniform, the variation in the S/N characteristic is small even if there is some DC offset.

The DC conversion error characteristics of the A/l) converter of the present invention shown in FIGS. 14 and 15 show a tendency for the error to become larger as the DC level becomes thicker. The DC conversion error characteristics include the amplitude of the pulse generated by the signal amplitude detection circuit 11, the judgment level VREF"vR" of the quantizer 4, and the amplitude detection level VRI, v of the signal amplitude detection circuit 11.
It changes depending on the magnitude of the value of R2.

Fig. 16 shows the DC conversion error characteristics of the A/D converter shown in Fig. 11 when the above parameter values are not set properly. 0,
045, VR1=l vR21=0.25 so that the DC conversion error characteristics over the entire quantizable range at a low full scale can be seen.

Here, (a) is V ] = l vREF2 l =
0.0625, EF (b) is 0.0625, and when changed to -0125, vREF”
This shows that the error characteristics change depending on the value of vREF2. In both (a) and (b), a relatively large error occurs in the DC input range of 02 to 025, but this is because the pulse amplitude is set to 0.045. This is because the input voltage exceeds the output range of the l)/A conversion circuit 6 during this period. In (b), 0045
In (a), this part is in the DC input range of 02 or higher and cannot be seen.

Threading, pulse amplitude and ■REF1. VR], By optimizing the magnitude of F2, the level that causes a large DC conversion error is concentrated in the range of 02 to 025, and the VR
The purpose of the present invention is to avoid using the low full scale DC input range of 02 to 025 by setting VR21 to 02 or less.

Figure 17 shows the S/N characteristics of the A/D converter shown in Figure 5, with a sampling frequency of -2,048 MHz.
.

Signal frequency = 1 klly, ,S evaluation band -〇
This is when the frequency is set to -4kHz. As shown in the DC conversion error characteristics of No. 1401, for full scale, as the human power level increases, the β difference in DC conversion increases, and the S/N becomes saturated, but at low human power levels, On the other hand, since A/D conversion can be completed using only the near zero DC level with small DC conversion error, it shows a good S/N ratio. Input level -130dB or more
So what is the ideal linear 15 bit? l! Equivalent S/N
%, and Guinamino Cleanse is also about 92 d.
B and large. Similar to the conventional circuit characteristics shown in FIG. 4, this figure is for a sampling frequency of 2.048 MHz, and if the sampling frequency is further increased, the elasticity characteristics will be improved. Also, the a/N% of the conventional circuit shown in Figure 4
Compared to the performance, there is a significant improvement of approximately 1.2 dB in the low human power level region.

Next, when comparing the circuit scales of the double conversion circuit of the present invention shown in FIG. 5 and the conventional circuit shown in FIG. 1, in the quantizer configuration shown in FIG. The conventional circuit uses only one comparator, and in the integrator peripheral circuit shown in FIG.
SW9 to SW12 and their control section are not present in the conventional circuit.

In addition, the D/A conversion circuit 17 (C
DA) and SW5 to SW8 have the same configuration, and only the switch control method is different. The amplitude detection circuit is the first
As shown in FIG. 2, the present invention can be realized with a small-scale logic circuit.

In this way, the A/]) conversion circuit of the present invention has one comparator and one circuit in the analog circuit section, compared to the conventional one circuit.
There is only an increase in the number of switched capacitor circuits.

(Effects) As explained above, the A/b converter of the present invention has the advantage of being able to significantly improve the efficiency at low input levels with a small circuit scale without using high-precision elements. This is achieved by reducing conversion errors near zero DC level A, and is suitable for inputting AC signals such as audio. Furthermore, the fact that high-precision elements are not required and the circuit can be realized on a small scale has a significant economical effect when manufactured using an integrated circuit. In addition, by removing noise distributed in the high frequency band with a filter, external sounds from the power supply etc. can be removed at the same time, so noise resistance is high and analog circuits and logic circuits can be completely separated. It also has the advantage that high S/N ratio can be easily achieved even if it is installed in the second device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional oversampling A/1) converter, and Fig. 2 is a block diagram showing the configuration of a conventional oversampling A/1) converter.
Figure 3 shows the S/N characteristics of a D converter. Figure 3 shows the DC conversion error characteristics of a conventional oversampling converter. Figure 4 shows the DC conversion error characteristics of a conventional oversampling converter.
The figure shows the S/N characteristics when a conventional Oha sample A/D converter has a DC offset, FIG. 5 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 6 is a diagram of the present invention. Figure 7 shows the integrator and its peripheral circuits, Figure 8 shows the full-scale switching method of the +4 D/A conversion circuit, Figure 1 shows the signal level・A diagram showing a diadarram, FIG. 10 is a diagram showing the relationship between human input signals and full-scale switching, FIG. 11 is a diagram showing another embodiment of the present invention, and FIG. 12 is a signal amplitude detection circuit used in the present invention. FIG. 13 is a diagram showing an example of a signal amplitude detection circuit according to another embodiment of the present invention, and FIG. 4 is a diagram showing a signal amplitude detection circuit according to another embodiment of the present invention.
]) Figure 15 is a diagram showing DC conversion error characteristics of a converter, Figure 15 is a diagram showing DC conversion error characteristics of another embodiment of the present invention, and Figure 1 (
) is a diagram showing the DC conversion error characteristic of another embodiment of the present invention with poor parameter settings, and FIG. 17 is a diagram showing the VN characteristic of one embodiment of the present invention. l...Analog signal input terminal, 2...
・Mountain...analog adder, 3...song/integrator,
4...Song...Quantizer, 5...Quantized signal output terminal, 6...Song D/A converter, 7
° Hit music digital filter, 8...Digital signal output terminal, 9...Tune/clock input terminal, 1o...Pulse generator, 11...
... Signal amplitude detection circuit, 12A, 12B...
・Comparator, 13A, 13B...D flip-flop, ]4......Amplifier, 15 ・
... Integrator @ (CI), ]6 ... Sampling capacity (C8), 17. Track D/A conversion capacity (CD
A), 18... Pulse voltage generation capacity (C
P), 19-21--Switch control section, 22... Frequency divider, 23...° signal output terminal 124-1.24-2... ...capacity, 250106.109. Input signal, 26°°
°゛°°signal input terminal, 27.28...OR circuit, 29...D type flip-flop, 3
0/1 song shift clock input terminal \31A, 31B
, , , , , , Comparator, 32 songs---E
X-□R circuit, 33... Signal input terminal,
34A, 34B...Reference level terminal. Patent Applicant Nippon Telegraph and Telephone Public Corporation Figure 1 Figure 2 Figure 4 Power output IL (dB) Figure 11 Figure 12 Figure 7 to 6 Figure 13 Figure 14 Figure 0 0, 2 0.4 0.6 0.8 1.0 IL to the slope entering Boan ())L cut-IL-=±1)

Claims (1)

[Scope of Claims] A signal obtained by converting the quantum R% output of the previous sampling period into an analog quantity is subtracted from the sum of the outputs of the Young Ring circuit that samples the input at a constant frequency higher than the input signal frequency and the /Clueless generation circuit. An integrator that integrates the adder output, a quantizer that quantizes the integrator output, and converts the quantizer output signal into an analog quantity and returns it to the adder and feeds it back. forming a loop l)/A
a conversion circuit, a digital filter that takes the quantizer output signal as an input and removes high frequency components to obtain a converter output signal; and a digital filter that takes the input signal or the converter output signal as an input and converts the D/ A conversion circuit and digital
In an analog-to-digital converter having an amplitude detection circuit that controls the full scale of the filter, the pulse generation circuit has a frequency obtained by dividing the Sanogring frequency and a frequency included in the stopband of the digital filter, and the pulse generation circuit generates a human input signal. 1 to 1 of the input signal range centered on the midpoint of the range
The quantizer generates a pulse waveform with an amplitude of about 0 coefficient, and the quantizer is composed of two voltage comparators that determine the magnitude of the integrator output with respect to the first and second reference voltages, and It has a function of quantizing into a first region above the first reference voltage, a second region below the first reference voltage and above the second reference voltage, and a third region below the second reference voltage. The D/A converter circuit has a first output range and a second output range, and the first output range has a range of output signals corresponding to the first, second and third ranges represented by the output signal of the quantizer. Each output range outputs 3 direct analog levels of the maximum value, center value, and minimum value, and the second output range similarly outputs the analog levels of the maximum value, center value, and minimum value of the output range. The center values of the first and second output ranges are equal, the maximum value of the second output range is a value that is more unfavorable than that of the first, and the amplitude of the input signal is directly derived from the input signal or from the converted output signal. The amplitude detection circuit determines whether the input signal amplitude is larger or smaller than a certain level, and selects the first output range when the input amplitude is large and the second output range when the input amplitude is small. and an input circuit that controls the output range of the D/A converter and simultaneously converts the quantizer output signal that can be input to the digital filter into a value corresponding to the output range of the D/A converter. An analog-to-digital converter featuring: