JPH08172360A - A/d converter - Google Patents

Abstract

PURPOSE: To improve the characteristics of a dynamic range, linearity, higher harmonic distortion, etc., by A/D converting an input analog signal by plural ΣΔconverters, adding respective converted outputs and passing the added output through a decimation filter (digital filter). CONSTITUTION: An analog signal is inputted from an input terminal 1 to N ΣΔconverters 21 to 2N, respective outputs are A/D converted into normal digital data consisting of one to several bits, the digital data are added by a digital adder 5, a quantized noise included in a digital output from the adder 5 is removed through a decimation filter 3, and a final digital output is obtained from an output terminal 4. When the ΣΔ converters 21 to 2N are connected in parallel, the signal level of the adder 5 becomes N times because the same signal is inputted from respective ΣΔ converters to the adder 5. When it is assumed that the conversion error of the ΣΔ converter is normally distributed, a conversion error becomes N<1/2> based upon the correlation function. Thereby the characteristics of the dynamic range, linearity and higher harmonic distortion, etc., can be improved.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an A / D converter using a ΔΣ modulator.

[0002]

2. Description of the Related Art FIG. 4 shows a block diagram of a conventional ΔΣ modulation type A / D converter. The ΔΣ modulation type A / D converter obtains a digital signal modulated by the ΔΣ modulator 2 to which an analog signal is input from the input terminal 1, and decimations the quantization noise driven to the high frequency range by the ΔΣ modulator 2. The digital signal after conversion after removal by the filter (digital filter) 3 is output to the output terminal 4, and is characterized in that a theoretically large dynamic range and resolution can be obtained.

[0003]

However, in an actual circuit, the theoretically calculated accuracy is reduced due to the conversion accuracy of the A / D converter used in the ΔΣ modulator and the inherent noise of the integrator. The current situation is that they cannot get it. The purpose of the present invention is to
An object of the present invention is to provide an A / D converter using a ΔΣ modulator that solves the above conventional drawbacks.

[0004]

A / A according to the present invention
The D converter is, in the A / D converter using the ΔΣ modulator, a plurality of ΔΣ modulators to which an analog signal is input, an adder circuit that adds each output of the plurality of ΔΣ modulators, and the adder circuit. And a digital filter to which the output of is input, and the digital output after conversion is obtained from the digital filter.

An A / D converter according to the present invention is an A / D converter using a ΔΣ modulator, in which a plurality of ΔΣ modulators to which an analog signal is input and respective outputs of the plurality of ΔΣ modulators are provided. It is composed of a plurality of digital filters to be input and an adder circuit to which outputs of the plurality of digital filters are input, and a digital output after conversion is obtained from the adder circuit. Also, the digital filter is a decimation filter.

[0006]

The input analog signal is A / D by N ΔΣ modulators.
After the conversion, each conversion output is added by the adder circuit. The output of each ΔΣ modulator is passed through a decimation filter (digital filter). Therefore, the conversion error of the finally output digital signal becomes 1 / N ^1/2 ,
The characteristics such as the dynamic range, linearity, and harmonic distortion of the A / D converter as a whole are improved.

[0007]

1 is a block diagram of an embodiment of an A / D converter of the present invention.
It is a lock figure. In the figure, analog from input terminal 1
ΔΣ modulator 2 with N signals (N is an integer of 2 or more)₁  , 2
₂ ,. . . , 2_NEntered in. Each ΔΣ modulator 2₁, 2
₂,. . . , 2_NOutput is A / D converted, usually 1 to several
It becomes digital data of bit and is added by the digital adder 5.
Adder 5 is added and passed through decimation filter 3
After the quantization noise contained in the digital output of is removed,
The final digital output is obtained at the output terminal 4.

By the way, N ΔΣ modulators 2₁, 2
₂ ,. . . , 2_N If the are connected in parallel, digital adder
The signal level of 5 is exactly the same signal from each ΔΣ modulator.
Is input, it becomes N times. On the other hand, in A / D conversion
Conversion error (in this case, noise is also considered as part of the conversion error).
, The conversion error of N ΔΣ modulators is normal.
Assuming distribution, take the correlation function to obtain N^1/2 Double
become.

Therefore, the signal at the output of the adder 5
The ratio of the level and the conversion error is N^1/2/ N = 1 / N^1/2
 Becomes That is, the conversion error in the output of the adder 5
1 / N^1/2 Therefore, the die for the A / D converter as a whole
Characteristics such as dynamic range, linearity, and harmonic distortion
Be improved.

FIG. 3 is a graph showing total harmonic distortion + noise vs. input signal frequency characteristic measured by the actual circuit of the A / D converter of the present invention shown in FIG. The measurement conditions are as follows. ΔΣ modulator has a sampling frequency of 3.072 MH
z, 5th order ΔΣ, digital adder is 1 bit 2 input, 2 bit 1 output, decimation filter is 1/64 decimation, 3.072 MH
It has a z / 2 bit input and a 48 kHz / 20 bit output.

As shown in FIG. 3, N = 1 (when only one ΔΣ modulator is used in FIG. 1) and N = 2 (FIG. 1).
In the case of using two ΔΣ modulators in the above), the characteristic curve in the case of N = 2 is compared with the case of N = 1.
It can be seen that the theoretical improvement is 1/2 ^1/2, that is, 3 dB, but the actually measured value is also improved by about 3 dB as in theory.

FIG. 2 is a block diagram of another embodiment of the A / D converter of the present invention. In the figure, N analog signals from the input terminal 1 (N is an integer of 2 or more) ΔΣ modulator 2
₁ , 2 ₂ ,. ． ． , 2 _N. Each ΔΣ modulator 2
₁ , 2 ₂ ,. ． ． , 2 _N outputs the decimation filters 3 ₁ , 3 ₂ ,. ． ． , 3 _N in the adder 5 to obtain the final digital output at the output terminal 4.

The A / D converter having the configuration shown in FIG. 2 is also a conventional A / D converter.
An improvement in performance is obtained compared to the converter. However, the limit performance that can be achieved is the decimation filter 3 ₁ , 3
₂ ,. ． ． , 3 _N output bits. In other words, although the number of bits of the digital output of the entire system increases by adding with the adder 5, the theoretical limit performance reached when the number N in parallel is increased is the number of output bits of each decimation filter. Up to Therefore, the number of output bits of all decimation filters must be increased in order to improve the marginal performance. Also, the scale of hardware is
N filter parts are required. The configuration shown in FIG.
Since only a plurality of Σ modulators are used, the conversion accuracy can be easily increased by increasing the number of output bits of the decimation filter unit in the subsequent stage only at one place.

[0014]

According to the A / D converter of the present invention, A
The characteristics such as dynamic range, linearity, and harmonic distortion of the entire / D converter are improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an A / D converter of the present invention.

FIG. 2 is a block diagram of another embodiment of the A / D converter of the present invention.

FIG. 3 is a graph showing total harmonic distortion + noise versus input signal frequency characteristics measured by an actual circuit of the A / D converter of the present invention shown in FIG.

FIG. 4 is a block diagram of an example of an A / D converter using a conventional ΔΣ modulator.

[Explanation of symbols]

1 input terminals 2,21,22 ,. ． ． , 2n ΔΣ modulators 3,31, 32 ,. ． ． , 3n decimation filter 4 output terminals 5 adder

Claims (3)

[Claims] 1. In an A / D converter using a ΔΣ modulator, a plurality of ΔΣ modulators to which analog signals are input, an adder circuit for adding respective outputs of the plurality of ΔΣ modulators, and the adder circuit. An A / D converter comprising a digital filter to which the output of is input, and a digital output after conversion is obtained from the digital filter. 2. In an A / D converter using a ΔΣ modulator, a plurality of ΔΣ modulators to which analog signals are input, and a plurality of digital filters to which respective outputs of the plurality of ΔΣ modulators are input, A / C, wherein an output of the plurality of digital filters is input, and a digital output after conversion is obtained from the addition circuit.
D converter. 3. The A / D converter according to claim 1, wherein the digital filter is a decimation filter.