JPH08154058A - Selector and radio equipment using the same - Google Patents

Abstract

PURPOSE: To suppress operating speed low, to reduce error and further, to reduce error at a prescribed frequency by integrating data showing the state of using a selecting object more than once, and selecting the selecting object corresponding to an input result according to the integrated result. CONSTITUTION: When a digital input signal is inputted to a selector 13, corresponding to its signal value, the selector 13 outputs a select signal. This select signal is integrated by an integrator 141 and next integrated by an integrator 142 on the next stage. The integrated signals of the integrators 141 and 142 are respectively inputted to multipliers 16 and 17 of the selector 13 and multiplied with a prescribed coefficient. The result signals from the multipliers 16 and 17 are added by an adder 18 and an added signal is compared with a former added signal by a comparator 19 corresponding to the input signal. According to this compared result, a selector 20 outputs signals for selecting current cells in order of the low use frequency. Namely, the select signals are outputted from the selecting part 13 so that dispersed current cells can be equally used. Thus, even when each current cell is equipped with error, error in the outputs of the entire current cells can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selecting device, and more particularly to a selecting device for selecting the output of, for example, a current source in a D / A converter and a device using this selecting device.

[0002]

2. Description of the Related Art Conventionally, digital / analog (D
/ A) When configuring a converter, input digital signal Din
To obtain the current output corresponding to (Din is an integer), Di
n unit current cells are selected. As a result, the output current Io becomes Io = Icell × Din, and digital-analog conversion is performed.

However, the current cells generally have an error due to the influence of variations. If the error of each current cell is εi, the error contained in Io is expressed by the following equation (1).

[0004]

[Equation 1]

Therefore, the differential linear error DNL becomes the value of the following expression (2), and the process variation, that is, the variation in the manufacturing apparatus and the manufacturing process is directly reflected in the error of the D / A conversion, and the conversion accuracy is determined. .

[0006]

[Equation 2]

For this reason, in this method, an expensive high-precision process is used to perform high-precision conversion, or adjustment by trimming or the like is required, resulting in an increase in cost.

A dynamic element matching method [1] is an improved method. In this method, when the conversion time is Ts and the number of bits is n _DA , Ts / 2 ^nD _A
The current cell used for each is switched so that all cells are used evenly in each conversion. In this way, the output charge Qout is expressed by the following equation (3).

[0009]

(Equation 3)

Here, Ii is the output current of the i-th cell as shown in the following equation.

[0011]

[Equation 4]

However,

(Equation 5)

Is a constant.

As a result, the error of each current cell affects only the gain error, and high conversion accuracy can be realized even if there is a variation. That is, the error of each cell is time averaged to improve the accuracy.

However, in the dynamic element matching method, it is necessary to select each cell within 1/2 ^nD _A of the conversion time, and the element is required to operate at high speed.

[0016]

As described above, the conventional method has a drawback that the performance is significantly deteriorated due to variations in elements, for example, current cells. Further, when the dynamic element matching method is used, it is necessary to switch at high speed, and it is difficult to realize high speed conversion operation.

[0017]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a selecting device which can keep the operating speed low, reduce the error, and further reduce the error at a predetermined frequency.

According to the present invention, an integrator that integrates data indicating the usage states of the selection objects having mutual errors one or more times, and the selection object according to the input signal according to the integration result of the integrator. A selection device comprising a selector for selecting is provided.

Integrating means for integrating the number of times of use of each selection object having an error with each other in a predetermined period, and selecting means for selecting a selection object having a small number of times of use in accordance with an integration result of the integrator and an input signal. There is provided a selection device configured by.

According to the invention: The selection device has a table showing a state in which selection objects having mutually different errors are selected, and the integrating means integrates the selection times of each selection object shown in the table one or more times in a predetermined period. Will be provided.

According to the present invention, a plurality of current sources connected in parallel, a plurality of switches for selecting the current sources, a table showing a selection state of each of the current sources, and a predetermined period shown in the table. A digital analog constituted by integrating means for integrating the data representing the selection state of each current source at least once, and selecting means for selectively activating the switch according to an integration result of the integrating means and an input signal. A converter is provided.

According to the invention: The current source is selected by the switch, and a digital-analog converter configured by a plurality of capacitors connected in parallel is provided.

According to the present invention, there is provided a digital-analog converter in which the switch circuit selectively connects a plurality of current sources to the adder.

According to the present invention, a plurality of delay time means for inputting the selection signal, a plurality of coefficient means respectively connected to the plurality of delay time means, and a feedback means for feeding back an output of the coefficient means. There is provided a selection device including a filter unit configured by a feed-forward unit that feed-forwards the output of the coefficient unit, and a selector configured to select a selection target according to the output of the filter unit.

According to the present invention, there is provided a selection device in which the zero point of the filter means is arranged at a point other than DC.

According to the present invention, the data indicating the usage state in the predetermined period of each of the selection objects having mutual error is set to 1
By an integrator that integrates more than one time, an adder that adds a dither signal to an input signal and outputs an addition signal, and a selector that selects the selection target according to the integration result of the integrator and the addition signal. A selection device configured is provided.

According to the present invention, feedback means including one or more integrators, quantizers, and coefficient means, an integrator that integrates data indicating the usage state of each of the objects to be selected in a predetermined period, A multi-bi equipped with a selector for selecting the selection object according to an integration result of the integrator and an input signal.
There is provided a Δ-Σ modulation type digital-analog converter configured by an internal D / A converter.

According to the present invention, there is provided a cascade type Δ-Σ modulator in which a Δ-Σ modulator is cascade-connected, which is composed of feedback means including one or more integrators, quantizers, and coefficient means. An integrator that is connected to the cascade type Δ-Σ modulator and that integrates data indicating the usage state of each of the selection targets, and a selector that selects the selection targets according to an integration result of the integrator and an input signal. B with
There is provided a Δ-Σ modulation type digital-analog converter constituted by an it internal D / A converter.

According to the present invention, feedback means having one or more integrators, quantizers, and coefficient means, an integrator for integrating data on whether or not each of the selection targets is used, and the integrator There is provided a Δ-Σ modulation type analog-digital converter configured by a multi-bit internal D / A converter including a selector that selects the selection target according to an integration result.

According to the present invention, a cascade type Δ-Σ modulator in which a Δ-Σ modulator is cascade-connected, which is composed of feedback means including one or more integrators, quantizers, and coefficient means, An integrator connected to the cascade type Δ-Σ modulator and integrating data indicating a usage state of each selection target, and a selector for selecting the selection target according to an integration result of the integrator are provided. Multi-bit internal D /
There is provided a Δ-Σ modulation type analog-digital converter including an A converter.

According to the present invention, a plurality of duplicators for duplicating a carrier wave, a switch circuit for selecting the output of the duplicator, and data indicating the usage state of each of the duplicators to be selected are integrated once or more. There is provided a modulator configured by an integrator and a selector driving the switch circuit to select the duplicator according to an integration result of the integrator and an input signal.

According to the present invention, a plurality of speakers, a switch circuit for selecting the output of the speaker, and data indicating whether or not each of the speakers to be selected are used are set as one.
There is provided an electroacoustic transducer including an integrator that integrates more than once and a selector that drives the switch circuit to select the speaker according to an integration result of the integrator and an input signal.

According to the present invention, the frequency conversion means for converting the frequency of the received signal and the A / D for converting the received signal converted from the frequency conversion means into a digital signal are output.
A wireless device including a D converter and a demodulator for demodulating a digital signal of the A / D converter,
The D converter includes a plurality of current sources connected in parallel, a plurality of switches that select the current source, an integrator that integrates the number of selections of each of the current sources, an integration result of the integrator, and a reception signal. And a selector for selectively activating the switch in response to the wireless device.

According to the present invention, an A / D converter for converting an input signal into an analog signal, a quadrature modulator for quadrature modulating the analog signal and outputting a quadrature modulated signal, and the quadrature modulated signal for converting into a transmission signal. A plurality of current sources connected in parallel, a plurality of switches for selecting the current sources, and each of the current sources. There is provided a wireless device configured by an integrator that integrates the number of selections of 1. and a selector that selectively operates the switch according to an integration result of the integrator and an input signal.

According to the present invention, there is provided a radio apparatus comprising a signal source for generating a digital signal and a transmitting means for converting the digital signal into a transmission signal and transmitting the transmission signal, wherein the transmitting means selects a current source. A plurality of switches, an integrator that integrates the number of times each of the current sources is selected, and a selector that selectively operates the switches according to a local oscillation signal selected according to an input signal and an integration result of the integrator. There is provided a wireless device configured by.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a block circuit of a selector of the first embodiment of the present invention, and FIG. 2 shows a selector of the selector of FIG. The selection device of FIG. 1 is connected to the current cell circuit as shown in FIG.

As shown in FIG. 1, the selection device includes a selector 13 connected between an input terminal 11 and an output terminal 12.
And a two-stage integrator connected to the output terminal of the selector 13, that is, first and second integrators 14 ₁ and 14 ₂ . The output terminals of the two-stage integrators 14 ₁ and 14 ₂ are connected to the control terminal of the selector 13, which selects the linear sum of the first and second integrators 14 ₁ and 14 ₂ according to the input signal. The selection signal selected in ascending order is output. This selection signal is a signal for selecting selection objects, that is, current cells, from selectable selection objects according to the number of inputs. This selection signal is supplied to integrators 14 ₁ and 14 ₂ and integrated.

That is, as shown in FIG. 2, the output terminals of the integrators 14 ₁ and 14 ₂ are connected to the multipliers 16 and 17 of the selector 13, respectively. These multipliers 16 and 17 multiply the integrated outputs of the integrators 14 ₁ and 14 _{2 by} a predetermined coefficient.
The outputs of the multipliers 16 and 17 are added by the adder 18, and the added outputs are compared with each other by the comparator 19 according to the inputs, and the magnitude relationship is detected. The selector 20 selects the addition output of the small value obtained in the comparator 19 and outputs it as a selection signal.

A selection signal from the selector 20 of the selector 13 selectively opens and closes the switches 21 _{1 to} 21 _n of the current cell circuit shown in FIG. 3 to selectively connect the current cells 22 _{1 to} 22 _n .

That is, when the digital input signal is input to the selector 13, the selector 13 outputs the selection signal according to the value of the digital input signal. 1 if the signal component of the digital input signal represents one level of the analog signal
It outputs a selection signal that selects one current cell. With this selection signal, for example, one of the switches 21 _{1 to} 21 _n of the circuit of FIG. 2 is selected and closed. As a result, the current of the corresponding current cell, for example, the current cell 21 ₁ , becomes equal to the output current Io.
Is output as If the digital input signal indicates two levels of the analog signal, for example, a selection signal for selecting the _two switches 21 ₁ and 21 ₂ , for example, 1100.
.. 0 is output from the selector 13. As a result, the added current of the _two current cells 22 ₁ and 22 ₂ corresponding to the switch is output as the output current Io. Thus, the currents of the current cells 22 _{1 to} 22 _n are selectively added according to the value of the digital input signal and output as the output current Io. That is, the digital signal is converted into an analog signal.

The selection signal output from the selector 13 is input to the integrator 14 ₁ and integrated. The integrated signal is input to the integrator 14 ₂ in the next stage and further integrated. Integrator 14
The integrated signals ₁ and 14 ₂ are input to the multipliers 16 and 17 of the selector 13, respectively, and are multiplied by a predetermined coefficient. The result signals from the multipliers 16 and 17 are added by the adder 18. The added signal is compared by the comparator 19 with the previous added signal according to the input signal. By this comparison, it is possible to detect the magnitude relationship of the added signals. The addition signal is the current cell 21.
_Since each of _{1 to} 21 _n indicates a value corresponding to the frequency of use (number of times of use) within the predetermined period, the frequency of use of the current cells within the predetermined period can be compared depending on the magnitude relationship of the added signal. According to the result of this comparison, the selector 20 outputs a signal for selecting a current cell in the order of low usage frequency. That is, the selector 13 outputs a selection signal such that the current cells 21 _{1 to} 21 _n with variations are evenly used. Thereby, even if each current cell has an error, it is possible to reduce the error in the output of the entire current cell. In addition, as in the conventional dynamic element matching method, each cell is selected by 1/2 ^nD _{A of the} conversion time.
Therefore, it is not necessary to operate the device at high speed. It should be noted that the current cells are selected according to the number of times of use within a predetermined period so that they are used evenly within the predetermined period.

In this embodiment, the current cell is used as the selection target, but the present invention is effective for a device that generally obtains an output by adding values having an error. For example, it can be applied to a capacitor array as shown in FIG. According to this example, the switches sw1 _{1 to} sw1 are driven by the clock ck1.
_n is closed and the capacitors c1 _{1 to} c1 _n are charged. The switch selected by the clock ck2, for example, the switch sw2 ₁ is closed, the selected capacitor c1 ₁ is connected to the output side, and the charge corresponding to the capacitor c2 is transferred to obtain the output. The selection device of the present invention shown in FIGS. 1 and 2 is used for the selection of the capacitors c1 _{1 to} c1 _n .
If the converter is configured, even if there is an error in the capacitor, the effect can be reduced.

Next, with reference to FIG. 5, a specific example of the selection device of the present invention will be described as a second embodiment. In this embodiment, integrators 14 ₁ and 14 ₂ are constituted by the delay element and adder indicated by z-1, and the output of the integrator 14 ₂ is input to the selector 13. Here, the selection signal that is the output of the selector 13 is composed of a plurality of signal components as shown in FIG. 6, and each signal component is 0, 1
Can take two values. If the signal component is 1, the corresponding current cell is selected, and if it is 0, it is not selected. Also,
The integrators 14 ₁ and 14 ₂ integrate these selection signal components, respectively. Therefore, it may be considered that a plurality of integrators are connected in parallel.

Here, the current I of the current cell shown in FIG.
i is expressed by the following equations (4) and (5).

[0046]

(Equation 6)

The vector representing the selection signal at time k is expressed by the following equation (6).

[0048]

(Equation 7)

The input signal is U (k), and U (k) is from 0 to n.
It is an integer that takes values up to.

The selector 13 operates so as to set the selection signal to 1 by the number corresponding to the input in the ascending order of the values of the outputs In (k) of the integrators 14 ₁ and 14 ₂ .

X (k) indicates the selected current cell, and the current output Iout is obtained by the following equations (7) and (8).

[0052]

(Equation 8)

However, <·, ·> represents the inner product of the vectors.

Now, although X is a vector representing cell selection as described above, the error Iouterr is included in the current actually output as shown in equation (7). This can be expressed by the following equations (9) and (10).

[0055]

[Equation 9]

[0056]

[Equation 10]

Therefore, X (k) also determines the error contained in the output. Further, the following expression (11) is obtained from the expressions (4) and (5).

[0058]

[Equation 11]

Therefore, the selector 13 causes the integrators 14 ₁ and 1
The operation of setting the selection signal to 1 by the number corresponding to the input in the ascending order of the value of the output In (k) of 4 ₂ means that the elements in the number of inputs are used in the direction opposite to the In (k) vector. It is equivalent to selecting the vector X (k) that is closest to the vector.

The error vector at this time is expressed by the following equation (12).

[0061]

(Equation 12)

In this case, if the conversion is written as Q (z), the equivalent circuit relating to the error of this embodiment can be expressed as shown in FIG. In this equivalent circuit, errors Q to X
The transfer function to is calculated by the following equation (13).

[0063]

(Equation 13)

If α1 = 1 and α2 = 1, the following equation (1
4) is established.

[0065]

[Equation 14]

From this, it is understood that the noise shaping term (1-z ^-1 ) ² is applied to Q (z), and Q (z) is subjected to the second-order shaping. The simulation result of the error signal at this output is shown in FIG. It can be seen from this figure that the error is suppressed in the low frequency region.

As the actual output, the output Io shown in FIG. 3 may be used as a current output or a voltage output may be obtained by current-voltage conversion.

As described above, by using the present embodiment, the current cells are selected so that they can be used evenly within the predetermined period, so that the influence of each error of the current cells is significantly increased near DC. It is possible to configure a highly accurate D / A converter that is reduced and has variations in elements. Moreover, since a highly accurate process is not required, it is possible to reduce the cost.

Next, a third embodiment will be described with reference to FIG. In this embodiment, one integrator 14 is used to simplify the configuration. Since the noise shaping characteristic becomes first-order and becomes gentle, it is effective when a large oversampling ratio cannot be obtained. Further, the characteristics of the filter placed afterward can be relaxed.

Further, the frequency at which noise is suppressed by shaping can be set by α2. For example, if α2 = -1, then 1/2 the sampling frequency
Can be set to.

The fourth embodiment is shown in FIG.
According to this embodiment, three integrators 14 ₁ , 14 ₂ and 14 ₃ are connected to realize a third-order shaping characteristic. By using a high-order shaping characteristic, noise near DC can be further reduced, and highly accurate conversion can be performed.

The transfer characteristic relating to the error at this time can be expressed by the following equation (15).

[0073]

(Equation 15)

Generally, in a third-order or higher-order Δ-Σ modulator, when the pole of the above-mentioned transfer function is arranged at the origin, the operation becomes unstable, so that the pole is set at a stable point inside the unit circle. Need to be placed.

Similarly, higher-order shaping characteristics can be realized. A fifth embodiment for the nth order is shown in FIG. According to this embodiment, n stages of integrators 14 _{1 to} 14 _n are provided. In this way, the accuracy can be further improved by increasing the order.

Next, a sixth embodiment using another construction method for the n-th order will be described with reference to FIG.

In this embodiment, the digital filter 15 is provided between the selection signal output terminal 12 and the control terminal of the selector 13.
Is connected. The digital filter 15 has a plurality of delay circuits DL _{1 to} DL to which selection signals are input.
_n , a plurality of coefficient circuits α _{1 to} α _n , which are respectively connected to the plurality of delay circuits and are connected to the selector 13, and delay circuits DL _{1 to} DL _n, and are connected to the selection signal output terminal 12. And a plurality of coefficient circuits β _{1 to} β _n .

With this configuration, it becomes possible to arrange the zero point and the pole of the noise transfer characteristic at arbitrary points. Therefore, it is possible not only to reduce the error near DC, but also to reduce the error at high frequencies. For example, in the case of the 4th order, two zero points at the origin, fs /
To set two zeros in m, the transfer function from Fin to Fout in the part shown by the dotted line in the figure is F (z) = [z (z)] /
When [P (z)] is set, βi may be determined as shown in the following expression (16).

[0079]

[Equation 16]

At this time, the pole is set by αi. By using this method, it becomes possible to directly convert a bandpass signal such as an intermediate frequency signal in the super heterodyne method.

As an example, a zero point is placed at fs / 4 in the quadratic and fs
FIG. 13 shows an example in which the accuracy at / 4 is improved. In this embodiment, the coefficient of the digital filter 15 is α
It is assumed that 1 = 0, α2 = -1, α3 = 0, β1 = 0, and β2 = 2. Further, FIG. 14 shows a simulation result of the frequency characteristic of the error at this time. From this simulation result, it can be seen that the error component near fs / 4 is reduced by noise shaping.

Further, FIG. 15 shows an embodiment of a transmitter according to the present invention. According to this, an input digital signal is converted into an analog signal by the D / A converter 25 according to the present invention. The signal is converted into a signal, an unnecessary signal is attenuated by the filter 26, frequency-converted, and then amplified by an amplifier 27 to obtain an output.

Here, as the input digital signal, the IF signal subjected to necessary modulation is used. This eliminates the need for a high-precision analog modulator, and the D / A converter 25 using the selection device of the present invention realizes high-precision digital-analog conversion, and a high-precision IF signal can be obtained.
Therefore, it is possible to easily configure a highly accurate transmitter.

When the IF frequency is low, the frequency converter can be omitted by directly modifying the signal of the carrier frequency by digital modulation.

Next, a seventh embodiment using the dither signal in the present invention will be described with reference to FIG.

In the above embodiment, the input signal is DC
When a signal is given, the current cells are selected periodically, and there is a drawback that noise components concentrate at a specific frequency.

In this embodiment, the dither signal of the dither signal generator 28 is added to the input signal by the adder 29, so that the input is changed even at the DC input,
The concentration of noise components is reduced. The added dither signal is removed by being subtracted by the adder 31 on the output side via the D / A converter 30. Also, when connecting the output signal to a low-pass filter and obtaining the final output,
This can be removed by setting the frequency of the dither signal to a frequency higher than the cutoff frequency of the low pass filter.

Next, an eighth embodiment in which the present invention is applied to an internal D / A converter of a Δ-Σ modulation type D / A converter is shown in FIG.
This will be described with reference to FIG.

According to this embodiment, integrators 31 ₁ and 3
The feedback circuit including 1 ₂ , the quantizer 32, the coefficient units 33 ₁ and 33 _2, and the delay circuit 34 is a D / A converter 3
Connected to 5. The D / A converter 35 is provided with the selection device of the present invention.

As the internal D / A converter of the Δ-Σ modulation type D / A converter, in most cases, a 1-bit internal D / A converter that does not cause a relative error is used. In this case, if the D / A converter using the selection device of the present invention is used, not only the relative error but also the absolute error can be reduced. As described above, generally generated reference voltages and currents include errors. This error is distributed around the true value,
When the average is 0, the error of the absolute accuracy can be reduced.

Further, the internal A of the Δ-Σ modulation type D / A converter is
When a multi-bit type is used for the / D and D / A converters, the S / N can be improved by 6 dB every time the data length of the A / D and D / A is increased by 1 bit. However, the noise generated by the internal D / A converter appears in the output as it is. Conventionally, when a multi-bit type internal D / A converter is used, the conversion accuracy of the internal D / A converter is generally lower than the target conversion accuracy. It was not possible to achieve high conversion accuracy, which was determined by the accuracy of the container. In addition, trimming or the like has to be performed in order to realize high conversion accuracy, which has a drawback of increasing cost.

If a D / A converter using the selection device of the present invention is used as the internal D / A converter of the Δ-Σ modulation type D / A converter, the current cells forming the internal D / A converter, etc. The influence of the element accuracy of is greatly reduced in the vicinity of DC. Therefore, when the present invention is used, it is possible to improve the overall conversion accuracy even if a process with poor element accuracy is used.

Generally, a third-order or higher-order Δ-Σ modulator becomes unstable in operation, but it is stable when a multi-bit type internal A / D and D / A converter is used. It is possible to operate. If the order of the Δ-Σ modulator can be increased, the oversampling ratio can be decreased, and it is not necessary to use a high speed element. Further, when operated at the same oversampling ratio, it becomes possible to realize more highly accurate conversion.

Here, if the band-pass type is used for the Δ-Σ modulator and the selection device of the present invention, the band-pass type, that is, the conversion accuracy at an arbitrary frequency is improved.
A / A converter can also be realized. As an example, fs
An embodiment in which a zero point is placed at / 4 to improve the accuracy at fs / 4 is the bandpass type selector shown in FIG. 13 in the internal D / A converter 35 of the bandpass type Δ-Σ modulator shown in FIG. A D / A converter using is used.

In the embodiment of FIG. 18, the delay circuit 34
The delay signals from the nodes ₁ and 34 ₂ are inverted by the inversion circuit 37, input to the quantization circuit 32, and quantized. Further, in the embodiment shown in FIG. 17, the input of the selection device, that is, the input of the internal D / A converter 35 becomes the output of the Δ-Σ modulator. Therefore, even when DC is applied to the input signal, the input of the selection device is a signal subjected to Δ-Σ modulation. In addition, the D / A converter 35 of the Δ-Σ modulator
Is a multi-bit type, the concentration of noise components in the modulator itself is reduced. Therefore, when a DC signal is directly input to the selection device of the present invention, there is a drawback that noise components are concentrated on a specific frequency, but in the case of this embodiment, this effect can be reduced.

Next, a ninth embodiment in which the present invention is applied to the internal D / A converter 35 of the cascade type Δ-Σ modulation D / A converter will be described with reference to FIG.

The cascade type Δ-Σ modulator has an integrator 31
It is a modulator that realizes a higher-order modulator by cascade-connecting a Δ-Σ modulator including a. It can be stable even when a third-order or higher-order modulator is configured, and is also called a MASH type. There is.

The disadvantage of the MASH type is that even if the output of each Δ-Σ modulator is 1 bit, the final output is multi-bit, and a multi-bit D / A converter is required. is there. The performance of the entire modulator depends on this multi-bit D
It is limited by the performance of the / A modulator.
The / A converter has been realized by using PWM or the like. PW
When M is used, it is necessary to use a pulse for a time that is a fraction of the D / A conversion time, which requires a very high clock frequency. Therefore, a high-speed element is required to realize high conversion accuracy, and power consumption is large.

If the D / A converter using the selection device of the present invention is used as the internal converter 35 of the MASH type D / A converter, a high-speed clock is not required and high-precision conversion is realized. It becomes possible. In addition, the clock frequency can be lowered and power consumption can be reduced.

In the present embodiment, each of the cascaded Δ-Σ modulators is a first-order modulator having one integrator, but an n-th order type in which n integrators are connected is shown. May be

Next, a tenth embodiment in which the present invention is applied to the internal D / A converter of the Δ-Σ modulation type A / D converter will be described with reference to FIG.

Internal A / D converter 3 of the Δ-Σ D / A converter
When a multi-bit type is used for the 5 and D / A converters 36, the S / N can be improved by 6 dB every time the data length of the A / D and D / A converters is increased by 1 bit. However, the noise generated by the internal D / A converter 35 appears in the output as it is. Conventionally, the internal D / A converter has many bi
When the t type is used, the conversion accuracy of the internal D / A converter is generally lower than the target conversion accuracy, so the overall conversion accuracy is determined by the accuracy of this internal D / A converter.
It was not possible to achieve high conversion accuracy. In addition, it is necessary to perform trimming or the like in order to realize high conversion accuracy, which has a drawback of increasing cost.

If the D / A converter using the selection device of the present invention is used as the internal D / A converter 35 of the Δ-Σ modulation type D / A converter, an internal D / A converter such as a current cell can be used. The influence of the accuracy of the constituent elements is greatly reduced in the vicinity of DC. Therefore, when the present invention is used, it is possible to improve the overall conversion accuracy even if a process with poor element accuracy is used.

Generally, a third-order or higher-order Δ-Σ modulator becomes unstable, but stable operation can be achieved when multi-bit type internal A / D and D / A converters are used. It is possible. If the order of the Δ-Σ modulator can be increased,
It is possible to reduce the oversampling ratio, and it becomes unnecessary to use a high-speed element. Further, when operated at the same oversampling ratio, it becomes possible to realize more highly accurate conversion.

The output of the internal D / A converter 36 shown in FIG. 20 is connected to the inputs of integrators 31 ₁ and 31 ₂ , respectively. Since the influence of the error of the D / A converter 36 in the Δ-Σ modulator is greatest in the first stage, even if the D / A converter using the selection device of the present invention is used for the D / A conversion in the first stage, a great effect is obtained. It is possible to obtain

Although the Δ-Σ modulator having a zero point at DC has been described here, if a band-pass type is used as the Δ-Σ modulator and the selection device of the present invention, a band-pass type, that is, It is also possible to realize a D / A converter with improved conversion accuracy at an arbitrary frequency.

As an example, a zero point is placed at fs / 4 and fs /
An embodiment with improved accuracy in No. 4 is shown in FIG. As the internal D / A converter 36 of the bandpass type Δ-Σ modulator shown in FIG. 21, the D / A converter 36 using the bandpass type selection device shown in FIG. 13 is used.

Further, in the embodiment shown in FIG. 20,
The input of the selection device, that is, the input of the internal D / A converter is Δ-Σ
It is the output of the modulator. Therefore, even when DC is applied to the input signal, the input of the selection device is a signal subjected to Δ-Σ modulation. Further, if the D / A converter of the Δ-Σ modulator is a multi-bit type, the concentration of noise components in the modulator itself is reduced. Therefore, when a DC signal is directly input to the selection device of the present invention, there is a drawback that noise components are concentrated on a specific frequency, but in the case of this embodiment, this effect can be reduced.

Next, referring to FIG. 22, an eleventh embodiment of the present invention in which the selection device of the present invention is used for the internal D / A converter 36 of the cascade type Δ-Σ modulation A / D converter. Will be explained.

The cascade type Δ-Σ modulator realizes a high-order modulator by connecting the Δ-Σ modulators in cascade, and can be stable even when a third-order or higher-order modulator is constructed. It is possible and is also called MASH type.

The disadvantage of the MASH type is that since the quantization noise mixed in each Δ-Σ modulator is digitally canceled, the difference between the transfer characteristic of each Δ-Σ modulator and the ideal value becomes a cancellation error. Since it directly appears, the demand for element accuracy is severe.

Therefore, if a multi-bit internal A / D and D / A converter is used in each stage, the quantization noise itself can be reduced and the influence of the canceller can be reduced.

Therefore, the D / A using the selection device of the present invention
If a converter is used, the influence of the accuracy of the elements such as the current cells that form the internal D / A converter 36 is greatly reduced in the vicinity of DC, so that a highly accurate converter can be realized.

Here, since the influence of the above-mentioned cancel error is reduced by the noise shaving after the second stage, the influence is smaller than that in the first stage. Therefore, a great effect can be obtained even when the internal D / A converter 36 of the present invention is used only in the first stage.

Further, the twelfth embodiment will be described with reference to FIG.

As a method for reducing the cancellation error in the first stage, there is a method in which the Δ-Σ modulator in the first stage is of the second order or higher. For example, in the case of the second order, the effect of the difference between the transfer characteristic in the first stage and the ideal value on the cancellation error is
Receives first-order noise shaping. Therefore, the influence of element accuracy can be reduced.

Furthermore, if a D / A converter using the selection device of the present invention is used as the internal D / A converter 36, the influence of the accuracy of the elements such as the current cells constituting the internal D / A converter will be in the vicinity of DC. It is possible to realize a converter with higher accuracy because the power consumption is greatly reduced.

FIG. 24 shows a thirteenth embodiment using the present invention in an amplitude modulator.

In this embodiment, the output terminal of the carrier wave oscillator OSC is connected to each base terminal of the transistors TR _{1 to} TR _n connected in parallel, and the voltage output is obtained from the resistor R connected to the collector terminal. Here, switches SW ₁ to SW are provided between the resistor R and the collectors of the transistors TR _{1 to} TR _n.
By inserting _n and controlling according to the switch signal input, the amplitude of the carrier wave is varied to obtain an amplitude modulation output.
By using the selection device of the present invention for controlling this switch, it is possible to reduce the influence of an error caused by the incompleteness of each transistor or switch, and to realize a highly accurate modulator. Furthermore, when a square wave is used as the carrier wave, the transistor operates as a switch, so the modulator can be configured with only the switch, and the effect of transistor non-linearity can be minimized. Can be configured.

Further, a fourteenth embodiment using the present invention in a speaker system will be described with reference to FIG.

A large number of groups of a plurality of speaker SPs are arranged, and each speaker SP is represented by D shown in the eighth embodiment.
A / A converter is connected instead of the A / A converter to convert the input signal of the eighth embodiment into an audio signal. The speaker SP is selected by using the selection device of the present invention according to the input signal of the D / A converter,
It is driven by a 0, 1 or -1 signal. As a result, the speaker can be driven only by the switch. For this reason, it is possible to reduce the deterioration due to the performance of the amplifier that is conventionally driven by the analog amplifier.

FIG. 26 shows a more specific selection device of the present invention. According to this selection device, a plurality of signal components X
Register 41 for storing selection signals represented by _{1 to} X _n
Is an integrator 42 including an adder 42a and a delay element 42b.
It is connected to the register 43 via _{1 to} 42 _n . The register 43 holds the integral value of the selection signal components X ₁ to X _n respectively. The plurality of output terminals of the register 43 are integrators 4
4 _{1 to} 44 _n are connected to the coefficient multipliers 46 _{1 to} 46 _n , respectively. The output terminals of the coefficient units 46 _{1 to} 46 _n are added together with the output terminals of the coefficient units 47 _{1 to} 47 _n whose input terminals are connected to the integrators 42 _{1 to} 42 _n , and the adders 48 _{1 to} 48.
connected to _n respectively. That is, the coefficient units 46 _{1 to} 46 _n
Multiplies the integrated cumulative signals from the integrators 44 _{1 to} 44 _n by a coefficient β, and the coefficient multipliers 47 _{1 to} 47 _n define the integrators 42 _{1 to} 42 _n.
The integral selection signal component from is multiplied by a coefficient α. The output signals of the coefficient multipliers 46 ₁ -46 _n and 47 ₁ to 47 _n are respectively added by adders 48 ₁ to 48 _n. The added signals from the adders 48 _{1 to} 48 _n are input to the classification circuit 49. The classification circuit 49 classifies the added signals in ascending order of the values, and stores the selection signal component in the register 50 according to the frequency of use within a predetermined period. The selection signal of the register 50 is sent to the D / A conversion circuit shown in FIG. At this time, the register 41 is updated with a new selection signal.

Next, the internal D using the selection device of the present invention
A transmitter equipped with the / A converter will be described.

According to the transmitter shown in FIG. 27, the received signal from the antenna 61 is input to the bandpass filter 62, attenuated outside the signal band, and then the low noise amplifier (LN).
A) Amplified by 63. The amplified reception signal is input to the mixers 65 ₁ and 65 ₂ via the bandpass filter 64. In the mixers 65 ₁ and 65 ₂ , the received signal is multiplied by the local frequency signal from the local oscillator 69 and the local frequency signal phase-shifted by the π / 2 shifter 68, and frequency converted. The frequency-converted received signals are input to the low-pass filters 66 ₁ and 66 ₂ , respectively, and the channels are selected. The channel-selected reception signals are input to A / D converters (ADC) 67 ₁ and 67 ₂ , respectively, and converted into digital signals. The digital signals from the A / D converters 67 ₁ and 67 ₂ are demodulated by the demodulator 7
It is input to 0, demodulated, and output.

The A / D converters 67 ₁ and 67 ₂ are shown in FIG.
1 and FIG. 2 are configured by a ΔΣ modulation type A / D converter having two stages of integrators 31 ₁ and 31 ₂ and an internal D / A converter 36 as shown in FIG. Two
The selection device of the present invention shown in FIG. In this embodiment, internal D is used to increase the dynamic range.
As the / A converter 36, a multi-bit D / A converter is used. If a multi-bit D / A converter is used, D / A
The non-linearity of the converter determines the performance of the overall A / D conversion characteristic of the A / D converter shown in FIG. Therefore, the internal D / A converter 36 needs to have a high accuracy. In the present embodiment, as the D / A conversion circuit of the D / A converter 36, the circuit shown in FIG. 3 or 4 which is selectively controlled by the selection device shown in FIGS. 1 and 2 is used. In the conversion circuit of FIG. 3, the current cells 22 _{1 to} 22 _n are selected by the selection device according to the number of input signals. in this case,
An addition signal smaller than the comparison reference input or a larger addition signal is selected from the addition signals of the adder 18 of FIG. 2, and the current cells 22 _{1 to} 22 _n are uniformly selected according to the selection addition signal. Therefore, noise due to variations in elements in a specific frequency band can be reduced.

As described above, by using the selection device as shown in FIGS. 1 and 2 for the internal D / A converter of the A / D converter, there are variations in the elements constituting the internal D / A converter. However, a highly accurate A / D converter can be realized. Therefore, an A / D converter having a wide dynamic range can be easily configured, and accordingly, the gain controller (AGC) is not required, and the cost can be reduced. However, if the dynamic range is insufficient even with the A / D converter having the configuration of the present invention, the AGC may be inserted in the preceding stage of the A / D converter. In this case, since the dynamic range of the A / D converter is greatly expanded, the AGC gain variable width may be narrow.

In this embodiment, the low-pass filters 66 ₁ and 66 ₂ are used to perform channel selection, so that a sharp cutoff characteristic is required. However, A /
Since the dynamic range of the D conversion 67 can be widened, the A / D converter can convert a wide band signal, the low-pass filters 66 ₁ and 66 ₂ are uncertain filters, the cutoff characteristics are made gentle, and the channel selection is It can be performed by the digital demodulator 70.

Low-pass filters 66 ₁ and 66 ₂ are required to have low distortion. However, when a filter having a gentle cutoff characteristic may be used, it is possible to form the filter by only passive elements that can be incorporated in the IC. Therefore, a low-distortion low-pass filter can be easily realized.

FIG. 28 shows a transmitter to which the present invention is applied. According to this receiving device, a voice input signal from a voice source, for example, a microphone 82 is digitally encoded by a codec (CODEC) 81, and mapped by a serial / parallel converter 80 into I and Q quadrature signals. The I / Q digital data from the serial / parallel converter 80 is converted into a D / A converter (DAC) 79 ₁
And 79 ₂ convert into an analog signal, and adder 7
5, the multipliers 761 and 762, the local oscillator 77, and the π / 2 transporter 78 perform quadrature modulation. The quadrature modulation signal is sent to the bandpass filter 7
After the unnecessary frequency signal is attenuated by 4, the power amplifier (PA) 73 amplifies the signal, and the band pass filter 72
Is input to The amplified signal is transmitted through the antenna 71 after the unnecessary frequency component is attenuated by the bandpass filter 72.

In this transmitter, the D / A converter 7
Since the selectors shown in FIGS. 1 and 2 and the D / A conversion circuit shown in FIG. 3 or 4 are used for 9 ₁ and 79R ₂ , there are variations in the D / A converters 79 ₁ and 79 _2. Even if it is composed of elements, a highly accurate signal can be obtained, and a transmitter with good modulation accuracy can be realized.

FIG. 29 shows the element 7 of the transmitter of FIG.
A portion configured by 5 to 79 is configured by a QMOD (quadrature modulator) 83. This QMOD83 is shown in FIG.
0 is shown. According to the QMOD 83 shown in FIG. 30, a plurality of transistor circuits 90 and 93 are connected to the output terminal OUT. The transistor circuit 90 includes a pair of transistors 91 whose emitters are connected to each other and a pair of transistors 92 whose emitters are connected to each other and whose collector is connected to the emitter of the transistor 91. The transistor circuit 93 includes a pair of transistors 94 having emitters connected to each other and a pair of transistors having emitters connected to each other.
4 and a pair of transistors 95 each having the collector of one transistor connected to the emitter.

In the QMOD 83, the selection signal (select) output from the selection device shown in FIG. 1 and FIG. Is input). Transistor pair 92 and 95
Local frequency signals φ1, / φ1 and φ1b, / φ1b are input to the base of. Thus, the selection signal
select and / select are supplied to the bases of the transistors 91 and 94, and the local frequency signals φ1, / φ1 and φ1
By inputting b and / φ1b to the bases of the transistor pairs 92 and 95, the current cell I is selected, and the output amplitude is modulated according to the number of the selected current cells I.

Local frequency signals φ1, / φ1 and φ1b, / φ1b are generated from the signal generating circuit shown in FIG. This signal generation circuit includes a local oscillator 101 that generates a local frequency signal φ, an inverter 102 that inverts the oscillation signal of the local oscillator 101 and outputs an inverted signal φ, and a phase shift of the local frequency signal φ by π / 2. π / 2 transfer device 103 that outputs φ1b
And an inverter 104 that inverts the signal φ1b and outputs an inverted signal φ1b.

As described above, since the transistor 95 is supplied with the signal obtained by phase-shifting the local frequency signal by π / 2, it is possible to obtain the amplitude-phase-modulated current output at the output terminal OUT. Of course, when a voltage output is required, a voltage output can be obtained by connecting a resistor to this output terminal OUT.

In this embodiment, the amplitude is the selection signal se
Depending on the number of lects, this selection signal is generated by the selection device shown in FIG. 1 or FIG. 2, so that it is possible to reduce the influence of the error due to the transistor size or the like at a specific frequency as in the reception device of FIG. You can As a result, the analog-digital conversion and the frequency conversion can be performed with high accuracy even if an element with low accuracy is used.
Therefore, the high-accuracy D / A converter and the high-accuracy quadrature modulator, which are conventionally required, are not required. In addition, it is not necessary to use a process with high element accuracy, so that cost reduction can be achieved.

[0136]

As described above, by using the present invention, it is possible to reduce the influence of analog element precision on the conversion precision, and it is possible to perform high precision conversion without increasing the operating speed. Further, since the element accuracy is not required, an expensive process, trimming, etc. are not required, so that the cost can be reduced and the size can be reduced, and further, the power consumption can be reduced by reducing the operation speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a selection device according to a first embodiment of the present invention,

2 is a block diagram of the selector shown in FIG. 1,

3 is a circuit diagram of a current cell connected to the selection device of FIG. 1;

FIG. 4 is a diagram showing a capacitor array circuit;

FIG. 5 is a block diagram of a selection device according to a second embodiment,

FIG. 6 is a diagram showing a format of a selection signal,

FIG. 7 is a diagram showing an equivalent circuit relating to errors of the second embodiment;

FIG. 8 is a diagram showing a simulation result regarding errors of the second embodiment;

9 a block diagram of a selection device according to a third embodiment, FIG.

FIG. 10 is a block diagram of a selection device according to a fourth embodiment,

FIG. 11 is a block diagram of a selection device according to a fifth embodiment,

FIG. 12 is a block diagram of a selection device according to a sixth embodiment,

FIG. 13 is a block diagram of a selection device according to a seventh embodiment,

FIG. 14 is a diagram showing simulation results regarding errors of the seventh embodiment;

FIG. 15 is a block diagram of a transmitter using the selection device of the present invention;

FIG. 16 is a block diagram of a selection device according to an eighth embodiment,

FIG. 17 is a block diagram of a selection device according to a ninth embodiment,

FIG. 18 is a block diagram of a selection device according to a tenth embodiment,

FIG. 19 is a block diagram of a selection device according to an eleventh embodiment,

FIG. 20 is a block diagram of a selection device according to a twelfth embodiment,

FIG. 21 is a block diagram of a selection device according to a thirteenth embodiment,

FIG. 22 is a block diagram of a selection device according to a fourteenth embodiment,

FIG. 23 is a block diagram of a selection device according to a fifteenth embodiment,

FIG. 24 is a block diagram of a selection device according to a sixteenth embodiment,

FIG. 25 is a block diagram of a selection device according to a seventeenth embodiment,

FIG. 26 is a block diagram of a selection device according to a seventeenth embodiment,

FIG. 27 is a block diagram of a receiver using a D / A converter using the selection device of the present invention;

FIG. 28 is a block diagram of a transmitter using a D / A converter using the selection device of the present invention;

FIG. 29 is a block diagram of a transmitter using a D / A converter using the selection device of the present invention;

30 is a circuit diagram of the QMOD used in the transmitter of FIG.

31 is a circuit diagram of a clock generator that generates a clock signal supplied to the QMOD of FIG.

[Explanation of symbols]

13 ... Selector, 14, 14 _{1 to} 14 _n ... Integrator, 21 ₁
~ 21 _n ... switch, 22 ₁ ~ 22 _n ... current cell, 25
... D / A converter, 28 ... Dither signal generator, 30 ... D /
A converter.

Claims (7)

[Claims] 1. An integration means for integrating the number of times of use of selection objects having mutual errors, and a selection means for selecting a selection object that is used less depending on an integration result of the integrator and an input signal. Selection device. 2. A table showing a state in which selection objects having mutually different errors are selected, and the integrating means integrates the selection times of each selection object shown in the table one or more times. Selection device. 3. A plurality of delay time means for inputting a selection signal, a plurality of coefficient means respectively connected to the plurality of delay time means, a feedback means for feeding back an output of the coefficient means, and the coefficient means. A selection device configured by a filter unit configured by a feed-forward unit that feed-forwards the output of the above, and a selector configured to select a selection target according to the output of the filter unit. 4. The selection device according to claim 3, wherein the zero point of said filter means is arranged at a point other than DC. 5. An integrator that integrates data indicating a usage state in a predetermined period of each of selection objects having mutual errors at least once, and an addition that adds a dither signal to an input signal and outputs an addition signal. And a selector that selects the selection target according to the integration result of the integrator and the addition signal. 6. A frequency conversion means for converting the frequency of the received signal, and an A / D for converting the converted received signal from the frequency conversion means.
A wireless device including an A / D converter for converting and outputting a digital signal and a demodulator for demodulating the digital signal of the A / D converter, wherein the A / D converter is connected in parallel. A plurality of current sources, a plurality of switches that select the current sources, an integrator that integrates the number of selections of each of the current sources in a predetermined period, and the switches according to an integration result of the integrator and a received signal And a selector for selectively operating the wireless device. 7. A / A for converting an input signal into an analog signal
A wireless device including a D converter, a quadrature modulator that quadrature modulates an analog signal and outputs a quadrature modulated signal, and a transmission circuit that converts the quadrature modulated signal into a transmission signal and transmits the transmission signal. The / D converter includes a plurality of current sources connected in parallel, a plurality of switches that select the current source, an integrator that integrates the number of selections of each of the current sources in a predetermined period, and an integrator of the integrator. A radio apparatus comprising a selector that selectively operates the switch according to an integration result and an input signal.