JP3226660B2 - Digital ΔΣ modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital delta-sigma (.DELTA..SIGMA.) Modulation for realizing an inexpensive high-performance digital-to-analog (D / A) converter mainly used in the fields of audio and voice communication. More particularly, the present invention relates to a digital ΔΣ modulator suitable for forming a 1-bit type D / A converter of an oversampling noise shaping method.

[0002]

2. Description of the Related Art In the fields of audio and communication,
With the recent progress in digitization, there has been a demand for an A / D converter for sampling an analog signal at fixed time intervals and converting its amplitude value to a multi-bit digital signal.
On the contrary, the demand for D / A converters for converting digital signals into analog signals is increasing, and the development of inexpensive and high-performance products is desired.

A typical D / A converter up to several years ago is:
The digital signal having the sampling frequency F _S is directly subjected to D / A conversion. For example, in the audio field, a 16-bit digital signal of F _S = 48 kHz is directly D / A converted to generate 2 ¹⁶ = 65536 amplitude values, which are then converted to a 10th or higher order analog filter (analog / analog) at the subsequent stage. (Referred to as a post filter) to reproduce an analog signal. However, this approach, it is difficult to realize on precise LSI amplitude levels are 2 ¹⁶ (large scale integrated circuit), frequently large harmonics and distortion, also increases the circuit scale, even 10 The cutoff of the analog filter
At the point (around 22 kHz), the phase was turned, so that the auditory characteristics (audibility characteristics) were also poor.

[0004] Therefore, in order to improve the hearing characteristics and to reduce the order of the analog post filter, the frequency is doubled to 8 times.
FIR (finite impulse) for double oversampling
response) type digital interpolation
Filter (digital interpolation filter)
16-bit D /
An A-converter was developed. By these, analog ・
The order of the post filter is reduced to the fourth to sixth order, so that the phase rotation at the cutoff point is kept low,
Hearing characteristics were slightly improved. However, D / point A converter is not reproduced Senebanara analog amplitude level are two ¹⁶ is intact, characteristic deterioration due to inter-element variation on LSI is inevitable, yet even more expensive to system cost It has become.

In comparison with the conventional 16-bit D / A converter described above, the oversampling ratio is set higher (32 to 256 times) and the quantization noise in the base band (0 to 22 kHz) is kept low. A so-called oversampling type noise shaping technique of converting (requantizing) multi-bit data such as 16 bits into a digital signal of 1 to several bits has begun to be developed.

In this type of D / A converter,
Since the actual digital data to be D / A-converted is one to several bits, the D / A converter only needs to represent two to several amplitude values, and the number of elements on the LSI is greatly reduced. Therefore, there is an advantage that it is possible to suppress the variation between the elements and thereby to improve the performance.

As a noise shaping technique for suppressing the requantization noise, a technique generally called ΔΣ modulation has been used, and various concrete techniques have been developed. The noise generated when re-quantization is canceled over time by a method such as feedback. The S / N ratio (signal-to-noise ratio) of the quantization noise in the baseband is the S / N ratio of the input digital signal in audio applications.
An N limit near 97.8 dB is required and is determined by the choice of (i) the oversampling ratio, (ii) the number of requantized bits, and (iii) the ΔΣ order (noise shaping order). In these selections, there are two types of conventional large flows: (a) The ΔΣ order is a stable second order, the number of requantization bits is 1 bit, and the oversampling ratio is 256 times (256F _s = 12.288M).
Hz), (b) The number of quantization bits is 2 to 4 bits, and the ΔΣ order is 3rd order (however, not 1
There is a case where the oversampling ratio is set to 64 times (64F _S = 3.072 MHz) as a device that obtains a third-order noise shaping characteristic while combining three order ΔΣ modulators. was there.

[0008] In the above (a), the operation speed is 1
Due to the high speed of 2.288 MHz, mass production with LSI is difficult. In particular, it is difficult to increase the speed of an analog circuit that performs 1-bit D / A conversion, and it is difficult to obtain good analog characteristics.

In the case of (b), although the number of quantization bits is small, the number of bits is large (2 bits or more). After all, it is difficult to obtain good analog characteristics. Specifically, the linearity of the D / A conversion is easily lost due to the variation between the elements.

In view of the above, the above problem has been solved and a good D / A
In order to obtain the conversion characteristic, a high-order ΔΣ modulator that can be configured with a lower oversampling ratio by setting the number of quantization bits to 1 is required.

An A / D for achieving this purpose has already been described.
As a converter, a fourth-order ΔΣ modulator in which the number of quantization bits is 1 as shown in FIG. 1 has been developed by the present applicant, which has an oversampling ratio of 64F _S =
This achieves an S / N ratio of 98 dB at 3.072 MHz. The fourth-order ΔΣ constituting the A / D converter
The modulator circuit is composed of an analog switched capacitor circuit, the integrators 1 to 4 are composed of an analog operational amplifier and an integrating capacitor, the 1-bit quantizer 11 is an analog comparator, and a feedforward
Paths, feedback loops, and the like are composed of a switched capacitor network, and each of the weighting factors a _{1 to} a
₄ , g ₀ and b ₁ are realized by the capacitance ratio of the capacitors in the adders 10, 14 and 15.

More specifically, as shown in FIG. 1, four integrators 1 to 4 are connected in cascade, and their outputs are weighted via four feedforward paths 5 to 8 respectively. After being multiplied by the coefficients a _{1 to} a _4, they are added by the feedforward adder 10, the addition result is quantized by the 1-bit quantizer 11 into 1-bit output data, and the quantized value is The feedback is fed back to the input of the integrator 1 at the first stage via the feedback paths 12 and 13. In other words, this feedback path includes a delay unit 12 for one sample time and a gain setting unit 13
The output of this path is added to a new input signal by the first-stage adder 14 and input to the first-stage integrator 1.

The input X in the ΔΣ modulator having the above configuration
The relationship between _(Z) and the output Y _(Z) is as follows. The quantization noise of the 1-bit quantizer 11 is Q _N , and the transfer function of the fourth-order loop 15 including all the circuits from 1 to 10 is H _{(Z). )}

[0014]

(Equation 1)

## EQU1 ## Baseband (0Hz-2
2 kHz)

[0016]

(Equation 2)

From

[0018]

[Outside 1]

Since H _(Z) basically has a fourth-order integration characteristic, H _(Z) ≫1. Therefore, the above equation (1) becomes

[0020]

(Equation 3)

Approximate expression In other words, the quantization noise Q _N is 1 / H _(Z) multiplied by the noise shaping characteristics with 1 bit ΔΣ modulated output Y _(Z) are obtained in baseband.

From the above equation (2), as H _(Z) increases,
It can be seen that Q _N / H _(Z) is reduced and the S / N ratio is improved as a result. Therefore, the transfer function H of the fourth-order loop 15
_The higher the order of _(Z), the better the S / N ratio. The value of the S / N ratio is determined by the weighting factor values a ₁ -a _{4 of the} feedforward paths 5-8 and the local feedback path 9. It is determined by the weight coefficients b _1. The local feedback path 9 inserts a double root zero point in the quantization noise spectrum of ΔΣ modulation, and is effective for improving the S / N ratio. Not a mandatory requirement.

[0023]

However, in the conventional example shown in FIG. 1, since the fourth-order loop 15 is constituted by an analog integrator or the like, the order of the transfer function is increased to further improve the S / N ratio. It is difficult to achieve this, and it is not suitable for mass production in LSI.

In view of this point, the present invention solves the above-mentioned problems (a) and (b) of the related art by realizing a high-order digital Δ 、 modulator, and achieves an LSI having good analog characteristics and good LSI characteristics. An object of the present invention is to provide a D / A converter that can be easily mass-produced. However, if the digital Δ 応 用 modulator based on the architecture is to be realized by simple digitization by applying the ΔΣ modulator of FIG. 1, each weighting factor which is easily realized by the analog switched capacitor network in FIG. Calculations of a _{1 to} a ₄ , g ₀ , b _{1, and the} like require multi-bit multiplication, causing a new problem that the circuit scale becomes enormous. In the audio field, a multi-channel D / A converter of 2 to 4 channels is required, and the operation rate is 64F _S =
Since the number of bits to be calculated is as large as 16 bits or more in contrast to the high speed of 3.072 MHz, problems to be solved in terms of circuit scale and high-speed operation are required to achieve the intended purpose. There is.

In view of the above, an object of the present invention is to provide a digital .DELTA.
ΣTo provide a modulator.

[0026]

[0027]

To achieve the above object, a digital Δ 目的 modulator according to the present invention comprises a plurality of m cascaded accumulators for accumulating a multi-bit input digital signal X _(Z). If, multiplied by the weight coefficient of each of a ₁ ~a _m against accumulation result output from the m accumulators means, feedforward adder means for summing the multiplication results, the feedforward adder The addition result of the input digital signal X
Digital output Y having fewer bits than _(Z)
(Z) and a predetermined feedback value corresponding to the requantized value Y _(Z) of the requantization means together with the input digital signal X _(Z).
And a feedback means for inputting to the first stage of the accumulation means of the number of accumulation means, the feedforward adder means is a power of two weighting factors of the a ₁ ~a _m, the multiplication of the polymerization viewed coefficient This is realized by a bit shift, the requantized value Y _{(Z) of the} requantizing means is 1-bit data, and the predetermined feedback value to the first-stage accumulating means is the input digital signal X _{(Z )} , And the addition of the feedback value and the input digital signal X _(Z) is realized by using an accumulator in the accumulator in the first stage. And

[0028]

[0029]

[0030]

[0031]

According to the present invention, in a single-loop 1-bit digital sigma, feedforward coefficients (a1 to a1) are set.
a4) is a power of 2, the 1-bit feedback coefficient (g0) is an integer, and an adder with the input signal (X) that causes an operation delay is eliminated. In particular, a delta-sigma modulator having a plurality of channels can be realized at low cost. In the present invention, the actual layout is reduced by half only with the delta sigma part.

[0032]

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Here, as a specific example, F _S = 48 kHz
64F _S = 3.072 MHz obtained by oversampling a digital audio signal of z, 16 bits by 64 times,
The 16-bit digital signal as input, the baseband while providing kept small noise shaping quantization Noiizu in (0Hz~22kHz), outputs the digital data of 64F _S re quantized to fewer bits than the input A case where the present invention is applied to a high-order ΔΣ modulator will be described below.

In the following embodiment, the case where the number of requantization bits is 1 will be described. However, this is for the sake of simplicity. Even when the number of bits is plural, the present invention can be applied as it is. As the order of the ΔΣ modulator, S / D which can be included in a 16-bit digital input signal is used.
In order to realize the limit value 97.8 dB of the N ratio by 64 times oversampling and realizing it by 1-bit quantization ΔΣ modulation, the case of the fourth order (m = 4) is selected as an actual example. The present invention is applicable to various orders and configurations of oversampling ratios according to the target to be obtained.

The basic operation of the fourth-order 1-bit ΔΣ modulator in the following description is the same as that of the conventional example shown in FIG.

(First Embodiment) FIG. 2 shows a circuit configuration of the first embodiment of the present invention when the weighting factors a _{1 to} a ₄ of the feedforward path are set to powers of two. The input signal X _(Z) is 16 bits, 64F _S = 3.072 MHz
Each integrating circuit is composed of 21 to 24 digital accumulators, that is, a multi-bit adder (accumulator) and an accumulation register. Each of the accumulators 21 to 24 has K _{1 to} K ₄ times the operation space for its input. That is, the integration gains of the accumulators 21 to 24 are 1 / K ₁ to 1 / K ₄ , and the values of these gains are set to powers of 2, so that multiplication is unnecessary and the accumulation of each stage is not required. The output of the arithmetic unit is directly connected to the input unit of the next stage by a bit shift of a wiring between blocks.

The feed-forward signal shown in FIG.
Passes 5-8 and feedforward adders 10 and 1
In the embodiment of FIG. 2, the bit quantizer 11
It consists of 28 feedforward paths and 29 additive quantizers. As an example, the values of the weighting coefficients a _{1 to} a ₄ are

[0039]

(Equation 4)

When the power is set to a power of two, each of the accumulators 21 to
A specific multiplication circuit such as a multiplier is provided by directly sending the output of 24 to the adder / quantizer 29 via the inter-block wiring in which the bit is shifted to the LSB side by 4 bits, 3 bits, 2 bits, and 1 bit. Substantially without a _{1 to} a ₄
Can be multiplied.

The adder / quantizer 29 is actually composed of three multi-bit adders 29a to 29c. The multi-bit adder 29a adds the data from the feed-forward paths 25 and 26, and the multi-bit adder 29b adds the data from the feed-forward paths 27 and 28. Are added by the multi-bit adder 29c at the subsequent stage, whereby the sum of the data from the four paths can be obtained. In 1-bit quantization, it is only necessary to determine whether the sum is positive or negative and output the result. Therefore, the sign bit of the addition result of the adder 29c is output as this determination result, that is, a 1-bit quantized output.

The 1-bit quantized output is multiplied by a gain g ₀ through a feedback path 33 and fed back to an input adder 34, and the new input output data X _(Z) output from the input register 31 is added to the output. Multi-bit adder 34
And sent to the first-stage accumulator 21.

Here, assuming that the positive and negative full scale values of the input data X _(Z) are x _max and −x _max , the value Y _(Z) of the 1-bit quantized output is positive or negative full scale. Expresses scale values x _max , −x _max , which are represented by g ₀
Doubled and fed back. So this is Y
_{When (Z)} = 1 (positive), −g ₀ · x _max is changed to Y _(Z) =
When it is 0 (negative), it means that + g ₀ · x _max is added to new input data X _(Z) . Where 1 and 0
Is used to represent positive and negative in 1-bit data, and 0 represents negative. When the data format is a two's complement format, the sign bit of the addition result of the adder 29c is represented by 0 when the determination result is positive, and is represented by 1 when the determination result is negative. This is inverted by the inverter 30 and output as Y _(Z) .

Further, in the present embodiment, the gain g ₀ is provided in the feedback loop 33. This shows the relative relationship with the input X _(Z), and a gain of 1 / g _{0 is applied} between the inputs. This is completely equivalent to the case where the gain of the feedback system is set to 1. Further, the effect of the delay Z ^-1 of the feedback system described above in the above equation (1) is the same regardless of where it is placed in the closed loop of the entire system. In the present embodiment, the accumulation in each accumulator 21 to 24 is performed. Automatically built into register operation.

With the above configuration, the fourth-order 1-bit ΔΣ modulator is constituted by a digitized circuit, and no weighting device is required, and each weight coefficient is constituted only by the bit shift of the inter-block wiring. Therefore, according to the present embodiment, a ΔΣ modulator having a small circuit size and capable of high-speed operation is realized.

FIG. 3 is a diagram for further understanding the bit shift of the inter-block wiring described above. In particular, the outputs of the two 20-bit accumulators 35 and 36 are each 4 bits,
A bit shift is performed by three bits, and a 17-bit adder 37 is used.
5 shows the state of the inter-block wiring when transferring to the block. That is, the outputs QA5 to QA2 of the 20-bit accumulator 35
0 is shifted by 4 bits in the lower direction and input to the input ports A1 to A16 of the 17-bit adder 37, and the outputs QB4 to QB20 of the 20-bit accumulator 36 are shifted by 3 bits in the lower direction and output by the 17-bit adder. 37 are input to the other input ports B1 to B17. As a result, a power-of-two operation can be realized without the need for a multiplier or the like, and an operation process for requantization with a simple circuit scale and high-speed operation can be performed. The accumulator 35 is the accumulator 2 in FIG.
1, 23, and the accumulator 36 is the accumulators 22, 24,
The adder 37 corresponds to the adders 29a and 29b in FIG.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention in which the present invention is applied in order to realize a digital Δ 行 う modulator for a plurality of channels which performs each operation processing in a time-division manner for each channel. 2 shows a circuit configuration of a second embodiment. here,
A case of two channels will be described as a specific example.
It is apparent from the following description that the configuration of the present example can be similarly applied to the case of three or more channels.

In FIG. 4, the input register and the accumulation register of each accumulator are two-word shift registers REG1 (45, 41 to 44) and REG2 for two channels.
(50, 46 to 49), and inputs X _{1 (Z)} and X _{2 (Z)} for two channels are stored in shift registers 45 and 5.
Each time the signal Y is alternately input via 0, outputs Y _{1 (Z)} and Y _{2 (Z)} for two channels are alternately generated and output using the same arithmetic circuit. An operation clock M commonly supplied from the clock supply circuit 40 to each of the shift registers
CK, the operation rate of each channel is 64F _S = 3.0
Assuming that the frequency is 72 MHz, twice that, 128F _S =
6.144 MHz. This operation clock MCK 1
Clock calculation period 1/6.144MHz@163ns
In this, the operation for one of the two channels, the 1-bit output, and the preparation for the operation for the next channel are performed.

That is, each second shift register REG
2 (46-49), the accumulated data of one channel up to the previous time is supplied to the self-loop path in each accumulator, the path to the next-stage accumulator, and the feedforward adder. A series of operations, such as passing the 1-bit output through the feedback path and adding the new input through the feedback path, to the first-stage accumulator, etc., are performed, and each first shift register R
EG1 (41-44). At the same time, each first
The accumulated data of the other channel stored in the shift register REG1 (41-44) is moved to each second shift register REG2 (46-49) so that it can be used for the operation in the next cycle. Become. By repeating the above operation, a simple two-channel time-sharing digital ΔΣ modulator can be realized without increasing the number of arithmetic circuits having a large circuit scale.

In this embodiment, shift registers REG1 and REG2 are used as registers for two channels.
That (i) eliminates the need for a multiplexer for selecting between channels, and (ii) eliminates the delay time caused by the multiplexer from the main operation path.
(iii) Since the same clock can be supplied to each register,
This is because advantages such as simplification of control and the like can contribute to a reduction in circuit scale and an increase in speed of operation.

Further, in this embodiment, the circuit 5 for setting the initial operation state and resetting at the time of abnormal operation is provided.
1 to 54 in the first shift register REG1 of each accumulator.
And the second shift register REG2.
The circuits 51 to 54 have a function of initializing the accumulation register REG2 at the start of the operation of the ΔΣ modulator of the present example, and of setting the value of the register REG2 to a predetermined value at the time of abnormality during operation, that is, at the time of oscillation. These circuits 51 to 54
May be placed anywhere in the entire system, but especially when the same arithmetic circuit is shared by a plurality of channels in a time-sharing manner as in the present embodiment, the circuits 51 to 52 may be connected to registers requiring high-speed operation. It is very disadvantageous to increase the delay time by inserting it in the operation path from REG2 to register REG1. Therefore, in this embodiment, the circuits 51 to 51 are provided on the path between the shift transfer from the register REG1 to the register REG2.
By arranging 54, it is possible to contribute to speeding up the operation path from the register REG2 to the register REG1.

The above-mentioned abnormality during operation is typically caused by an overflow due to the fact that the accumulator has a finite number of bits. In order to avoid this overflow, the circuits 51 to 54 must be The accumulated result of each time taken into the register REG1 is always checked, and if the accumulated result is equal to or more than a predetermined value (threshold), it is determined that oscillation has occurred, and a predetermined value for returning to the normal state is stored in the register REG2. The reset data is sent to a value (for example, all zeros). As a result, the register REG2 changes to the register REG.
A stable digital ΔΣ modulator can be provided with a simple circuit configuration without deteriorating the speeding up of the operation path to 1.

FIG. 5 shows the structure of one of the above accumulators in FIG. 4 in more detail. The register 62 is the registers 41 to 44 of FIG. 4, and the register 63 is the register 46 of FIG.
To 49 and the circuit 64 correspond to the circuits 51 to 54 in FIG. In FIG. 5, 62 registers REG1 and 63 registers RE are used as accumulation shift registers for two channels.
G2 and 61 accumulators for accumulation are each composed of 20 bits, and 64 initial setting and abnormality reset circuits are inserted and connected between the registers REG1 and REG2. Since the accumulation gain of this accumulator is １ ／, the input data is 19 bits D1 to D19. The adder 61 is composed of 20 ordinary full adders (full adders).
Connected carry ripple adders (Carry-Ripple-A
dder), and its data format is a two's complement format. 20-bit first accumulation shift register REG1
(62), the second cumulative shift register REG2 (63), and the register for storing the previous 2-bit data in the initial setting / abnormal reset circuit 64 are the same 128F _S = 12.28 MHz from the clock supply circuit 40. Of the clock MCK.
Data is shifted and transferred between registers in each cycle.
The registers REG1 and REG2 store data of different channels.

2 in the initial setting / error reset circuit 64
The register of bits is the first accumulation shift register REG1
Top 2 of the previous data of the channel stored in (62)
The bits (J19, J20) are stored. In this example, the purpose is to detect the occurrence of overflow as abnormal time.

[0055]

[Outside 2]

[0056]

[Outside 3]

This indicates that the above-mentioned (a) has occurred.
Or in case of (b)

[0058]

[Outside 4]

Second accumulation shift register REG2 (63)
Is reset to all zeros. In the initial setting, at the beginning of operation,

[0060]

[Outside 5]

The contents of the second accumulation shift register REG2 are set to all zeros.

In the above judgment (a) or (b), the input is 19 bits, that is, the operation space of the accumulator is at least one bit larger than the number of bits of the input data (19 bits). , But normal higher order Δ
In Σ modulation, the accumulated gain is often set to 以下 or less, so this overall condition can be a very effective determination condition. If the above (a) and (b) are further supplemented,

[0063]

[Outside 6]

This indicates that the accumulated result up to the previous time was a value of +0.5 or more when normalized in a 20-bit space. Therefore, the result of adding a new 19-bit input is a positive value. There should be. Therefore, register REG1
Q20 ', which is the sign bit of, must be 0 at this time. Therefore, if Q20 '= 1, it is recognized that a positive overflow has occurred and the sign bit has been determined.

[0065]

[Outside 7]

Since the accumulated result up to the previous time was a value of -0.5 or less when normalized in a 20-bit space, the value obtained by adding a new 19-bit input remains a negative value. There should be. Therefore, the sign bit Q20 'of the register REG1 must be 1 at this time. Therefore, if Q20 '= 0, it is recognized that a negative overflow has occurred and the sign bit has been inverted.

The configuration of the embodiment shown in FIG. 5 is such that the overflow detection can be realized by checking only 3 bits without checking all 20 bits, and it is possible to simply detect the overflow by using a new control circuit. A very simple circuit in that one clock supply circuit 40 can be used, the initial setting and the reset at the time of abnormality are shared by the same reset circuit, and a single circuit can be shared for two channels. Can be realized. Moreover,
Since the delay of reset and abnormality detection can be omitted from the operation path from the register REG2 to the register REG1, including the carry propagation delay, etc., a simple and high-speed
A digital ΔΣ modulator for a channel can be realized.

In the circuit of FIG. 5, the initial set value and the reset value at the time of abnormality are all zero, but this is for the purpose of simplifying the circuit description. It is needless to say that the use of the initial setting value and the reset value at the time of abnormality are different from each other with a similar circuit configuration.

(Third Embodiment) Next, referring to FIGS. 6 and 7, one multi-bit adder is omitted from the ΔΣ modulators of the first and second embodiments described above, and A third embodiment of the present invention for simplification will be described. This example is
The gain g ₀ of the feedback path shown in FIG. 2 or FIG.
Is omitted. Below, g ₀ =
The present embodiment will be described with reference to FIGS. 6 and 7 showing the accumulation adder in the first-stage accumulator for the case of 2 and the case of g ₀ = 3. This is equivalent to the case where the feedback gain is set to 1 with a gain of / g ₀ . In addition, the case where g ₀ ≧ 4 can be easily analogized by extending the method described below.

FIG. 6 shows that the gain g ₀ = 2 and the integral coefficient K ₁ =
This shows the case where 2 ³ = 8 (see FIG. 1), the first-stage adder (34) shown in FIGS. 2 and 4 is eliminated, and the input terminals D1 to D16 of the 19-bit accumulator are added. 16-bit data x ₁ ~x ₁₆ input X _(Z) is input directly,
To adder input terminal D17

[0071]

[Outside 8]

Are input to the adder input terminals D18 and D18.
19 is supplied with a 1-bit output value Y _(Z) as a quantization result. In the following description, the output value Y _(Z) is represented by Y _(Z) = 1 when the quantization result is positive, Y _(Z) = 0 when the quantization result is negative, and It is assumed that the data format used for all operations including the data X _(Z) is expressed on the left side as the MSB side in the two's complement format.

When the input data X _{(Z) in} FIG. 6 is represented by 19 bits, the upper 3 bits are sign bit-extended, and

[0074]

[Equation 5] x ₁₆ x ₁₆ x ₁₆ x ₁₆ x ₁₅ x ₁₄ x ₁₃ x ₁₂ x ₁₁ x ₁₀ x ₉ x ₈ x ₇ x ₆ x ₅ x ₄ x ₃ x ₂ x ₁ ... (3), and Y _{( When Z)} = 1 (the quantization result is positive), the feedback value is −2 · FS (FS is the maximum value of the input 16 bits),

[0075]

(1) 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0... (4) must be added. (3) and (4) result of data obtained by adding the formula in _the case of _{x 16} = 0 (input _{X (Z)}
Is positive)

[0076]

[Equation 7] 1 1 1 x ₁₆ x ₁₅ · · · · · · · · · · · · · x ₂ x ₁ ... (5) If x ₁₆ = 1 (input X _(Z) is a negative value), 1 1 0 x ₁₆ x ₁₅ · · · · · · · · · · · · x ₂ x ₁ ... (6), and the data of formulas (5) and (6) are

[0077]

(Equation 8)

Is expressed as follows.

Next, when Y _(Z) = 0 (the quantization result is negative), the feedback value is + 2FS,

[0080]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (8) is added to the input data of the expression (1), and the result of the addition is x ₁₆ = When it is 0,

[0081]

[Number 10] at the time of the _{0 0 1 x 16 x 15 ·} · · · · · · · · · · · x 2 x 1 ... (9) x 16 is,

[0082]

[Equation 11] 0 0 x ₁₆ x ₁₅ · · · · · · · · · · · · · x ₂ x ₁ ... (10), and the data of equations (9) and (10) are also expressed by equation (7). Is expressed.

As described above, according to the circuit configuration shown in FIG.
It is understood that the input x _(z) and the feedback amount ± g ₀ · FS are automatically added to the first stage accumulator (first stage accumulation register) while eliminating the first stage adder. it can.

Next, FIG. 7 shows the case where g ₀ = 3 and K ₁ = 8. Also, the first-stage adder is eliminated, and the adder for accumulation is 19 bits. In this zero, the value of g ₀ is an odd number, the lower 15-bit data x ₁ ~x ₁₅ is to input terminals of the 19-bit accumulator adder D1~D15 excluding the sign bit of X _(Z) is directly input, the the D16 of the input terminal of the adder is input inverted x ₁₆ is the inverted value of the sign bit x _16, 1-bit output value inputted to the terminal D17 is the quantization result of the adder Y _(Z) the inverted value a is inverted Y _(Z) is the input terminal of the adder to D18~D19 its Y _(Z) is input.

When Y _(Z) = 1, the feedback value is −3 · FS from g ₀ = 3.

[0086]

(11) 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (11) is added to the data of the above equation (3). The result of the addition is, when x ₁₆ = 0,

[0087]

[Equation 13] 1 1 0 1 x ₁₅ x ₁₄ · · · · · · · · · · · x ₂ x ₁ ... (12) When x ₁₆ = 1,

[0088]

[Equation 14] 1 11 0 x ₁₅ x ₁₄・ ・ ・ ・ ・ ・ ・ ・ ・ ・ x ₂ x ₁ … (13)

[0089]

(Equation 15)

Are expressed as follows.

On the other hand, when Y _(Z) = 0, the feedback value is + 3 · FS,

[0092]

(15) is added to the data of the above equation (3), and the result of the addition is expressed as x ₁₆ = 0. in case of,

[0093]

[Formula 17] 0 0 1 1 x ₁₅ x ₁₄・ ・ ・ ・ ・ ・ ・ ・ ・ ・ x ₂ x ₁ … (16), and when x ₁₆ = 1,

[0094]

Equation 18] _{0 0 1 0 x 15 x 14} · · · · · · · · · · · x 2 x 1 ... (17) next to and also together represent the above (14).

As described above, when g ₀ = 3, the input X _(Z) and the feedback amount ± g ₀ · FS are automatically set by the circuit configuration shown in FIG. 7 while eliminating the first-stage adder. Is added to the first stage accumulator (first stage accumulation register)
It can be understood that it has been entered.

It is apparent that the configuration described above can be naturally extended by a similar method when g ₀ = 4 or more. One of the main parts of the method is that when g ₀ = n, the sign bit x of the input X _(Z) when n is an even number
₁₆ was inputted directly into the D16, when n is odd inversion x ₁₆ of the sign bit is to input to D17. In any case, according to this embodiment, since the 19-bit first-stage adder can be eliminated, the circuit scale can be greatly reduced, and the delay of the path where the operation delay is the largest can be reduced. The effect can be expected to be enormous in realizing a digital ΔΣ modulator of a plurality of channels as in the second embodiment which requires the following.

[0097]

As described above, according to the present invention,
In single-loop 1-bit digital sigma,
The feedforward coefficients (a1 to a4) are set to powers of 2 and the 1-bit feedback coefficient (g0) is set to an integer.
Since the adder with the input signal (X), which causes the operation delay, is eliminated, the operation at the maximum delay point is halved, and in particular, the effect of realizing a multi-channel delta-sigma modulator at low cost can be achieved. can get. Further, according to the present invention, the actual layout is reduced by half only in the delta sigma portion.

[0098]

[Brief description of the drawings]

FIG. 1 shows a conventional fourth-order 1-bit Δ constituted by analog elements.
FIG. 3 is a block diagram illustrating a configuration of a modulator.

FIG. 2 shows the configuration of a first embodiment of the present invention, in which weighting coefficients a _{1 to} a ₄ of the feedforward path are set to powers of 2 and multiplication of each coefficient is performed by bit shifting of inter-block wiring. FIG. 3 is a block diagram showing a configuration of a digital ΔΣ modulator for fourth-order 1-bit quantization when it is realized.

FIG. 3 is a block diagram showing details of a bit shift by an inter-block wiring in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a two-channel time-sharing digital ΔΣ modulator according to a second embodiment of the present invention.

5 is a diagram showing two stages of the initial stage setting and abnormal reset circuit of FIG.
FIG. 9 is a circuit diagram showing a detailed configuration example in the case where the digital ΔΣ modulator for channels is arranged between accumulation registers.

FIG. 6 is a diagram showing a third embodiment of the present invention, in which an adder circuit for input X _(Z) and feedback −g ₀ Y _(Z) in a first-stage accumulator when the feedback gain g ₀ is 2; FIG. 3 is a circuit diagram illustrating a configuration.

FIG. 7 is a circuit diagram showing a configuration when g ₀ is 3.

[Explanation of symbols]

 1-4 Integrator 5-8, 25-28, 33 Feedforward path 10, 14, 15, 29a-29c, 37 Adder 11 1-bit quantizer 13 Gain setter 21-24, 35, 36 Accumulation Device 29 adder quantizer 30 inverter 34 first stage adder 40 clock supply circuit 41-45,62 first shift register REG1 46-50,63 second shift register REG2 51-54,64 initialization / error reset circuit 61 Adder for accumulation

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02

Claims (1)

(57) [Claims] 1. A multi-bit input digital signal X _(Z)
A plurality m accumulators means connected in cascade to accumulate, is multiplied by a weighting factor for each of a ₁ ~a _m against accumulation result output from the m accumulators means, the multiplication Feedforward adding means for summing the results; and adding the addition result of the feedforward adding means to a digital output Y _(Z) having a smaller number of bits than the input digital signal X _(Z) based on a predetermined criterion. Re-quantizing means for quantizing, and a predetermined feedback value corresponding to a re-quantized value Y _(Z) of the re-quantizing means, the input digital signal X _(Z)
Wherein and a feedback means for inputting to the first stage of the accumulation means of the m accumulators means, the feedforward adder means and power weighting factors 2 of the a ₁ ~a _m with, heavy viewed coefficient Is realized by a bit shift, the requantized value Y _{(Z) of the} requantizing means is 1-bit data, and the predetermined feedback value to the first stage accumulating means is the input digital signal. X _(Z) is an integral multiple of the maximum value, and the feedback value and the input digital signal X
_(Z) is realized by using an accumulating adder in the accumulating means of the first stage.
Modulator.