JPH0722952A - Digital deltasigma modulator - Google Patents

Abstract

PURPOSE:To provide a small circuit scale high-order digital DELTASIGMA modulator by setting weighting factors (a)1-(a)m to be powers of two, and performing the multiplication by the bit shift of inter-block wiring, in a feed forward adding means. CONSTITUTION:A feed forward path, adder, and one bit quantizer are constituted of feed forward paths 25-28 and an adding quantizer 29. Then, for example, the values of weighting factors (a)1-(a)4 are set as a power of two, that is, (a)1=1/16=2<-4>, (a)2=2/16=2<-3>, (a)3=4/16=2<-2>, and (a)4=8/16=2<-1>. In this case, the output of each accumulator 21-24 is directly transmitted through the feed forward paths 25-28 to the adding quantizer 29 by inter-each block wiring in which the data are bit-shifted to an LSB side by each 4bit, 3bit, 2bit, and 1bit. Thus, the weighting factors (a)1-(a)4 can be substantially multiplied without providing a concrete multiplying circuit such as a multiplier, and the small circuit scale and high speed high-order digital DELTASIGMA modulator can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital delta sigma (ΔΣ) modulation for inexpensively realizing a high performance digital analog (D / A) converter mainly used in the fields of audio and voice communication. In particular, the present invention relates to a digital ΔΣ modulator suitable for constructing a 1-bit type D / A converter of an oversampling noise shaping system.

[0002]

2. Description of the Related Art In the fields of audio and communication,
The demand for an A / D converter for sampling an analog signal at regular time intervals and converting the amplitude value into a multi-bit digital signal with the progress of digitization in recent years,
On the contrary, the demand for a D / A converter for converting a digital signal into an analog signal has increased, and development of these inexpensive and high-performance products has been desired.

Conventional D / A converters up to several years ago,
The digital signal having the sampling frequency F _S is directly D / A converted. For example, in the audio field, a 16-bit digital signal with F _S = 48 kHz is D / A converted as it is to generate 2 ¹⁶ = 65536 amplitude values, and this is used as an analog filter (analog The analog signal was reproduced through a post filter). However, with this method, it is difficult to accurately realize 2 ¹⁶ amplitude levels on an LSI (Large Scale Integrated Circuit), a large number of harmonics and distortions occur frequently, and the circuit scale becomes large. Cutoff of analog filter that is sharper than
At the point (near 22 kHz), since the phase turns, the auditory characteristics (audibility characteristics) were also poor.

Therefore, first, in order to improve the hearing characteristics and reduce the order of the analog post filter, double to 8 times.
FIR (finite impulse) for double oversampling
response) type digital interpolation
Same as filter (digital interpolation filter)
16-bit D / for speedup so that it can operate at 8 times
The A converter was developed. With these, analog
The post filter order is reduced to the 4th to 6th order, thus keeping the phase rotation at the cutoff point low.
The auditory characteristics were slightly improved. However, the point that the D / A converter has to reproduce 2 ¹⁶ kinds of analog amplitude levels remains as it is, the characteristic deterioration due to the variation between elements on the LSI cannot be avoided, and the system cost is more expensive. Has become.

Compared with the conventional 16-bit D / A converter described above, the oversampling ratio is made higher (32 times to 256 times) and the quantization noise in the base band (0 to 22 kHz) is kept low, A so-called over-sampling noise shaping technique of converting (re-quantizing) multi-bit data such as 16 bits into a digital signal of 1 to several bits has begun to be developed.

In this type of D / A converter,
Since the actual digital data to be D / A converted is one to several bits, the D / A converter only needs to express two to several different amplitude values, and the number of elements on the LSI is significantly large. Therefore, there is an advantage that it is possible to suppress the variation between the elements and improve the performance.

As the above noise shaping technique for suppressing requantization noise, a technique generally called ΔΣ modulation has been used, and various concrete techniques have been developed. The noise generated at the time of requantization to is canceled with time by a method such as feedback. The S / N ratio (signal-to-noise ratio) of the quantization noise in the baseband is the S / N ratio of the input digital signal for audio applications.
A near N limit value of 97.8 dB is required and is determined by the selection of (i) oversampling ratio (ii) requantization bit number (iii) ΔΣ order (noise shaping order). In these selected two as a conventional large flow, (a) .DELTA..SIGMA order was a stable secondary, the number of re-quantization bits as one bit, 256-fold oversampling ratio (256F _S = 12.288M
Hz), (b) The number of quantization bits is 2 to 4 bits, and the ΔΣ order is the third order (however, 1 is used instead of the cascade connection).
There are three types of third-order noise shaping characteristics obtained by combining three next-order ΔΣ modulators) with an oversampling ratio of 64 times (64F _S = 3.072 MHz). was there.

In the case of the above (a), the operation speed is 1
The high speed of 2.288 MHz makes it difficult to mass-produce LSI. In particular, it is difficult to increase the speed of an analog circuit that performs 1-bit D / A conversion, and it is difficult to obtain good analog characteristics.

In the case of the above (b), although the number of quantization bits is small, it is multi-bit (2 bits or more). Therefore, due to the influence of variations between analog elements when D / A converting this. After all it is difficult to obtain good analog characteristics. Specifically, the linearity of D / A conversion is likely to be lost due to variations between elements.

Therefore, the above problem is solved and a good D / A is obtained.
In order to obtain the conversion characteristic, a high-order ΔΣ modulator that requires a quantization bit number of 1 and can be configured with a lower oversampling ratio is required.

Already, A / D for achieving this purpose
As a converter, a 4th-order ΔΣ modulator having a quantization bit number of 1 bit as shown in FIG. 1 has been developed by the present applicant, which has an oversampling ratio of 64F _S =
This achieved an S / N ratio of 98 dB at 3.072 MHz. The 4th order ΔΣ that constitutes the A / D converter
The modulator circuit is composed of an analog switched capacitor circuit, the integrators 1 to 4 are composed of an analog operational amplifier and an integrating capacitor, and the 1-bit quantizer 11 is an analog comparator.
The paths, feedback loops, etc. are composed of switched capacitor networks, and each weighting factor a _{1 to} a
₄ , g ₀ and b ₁ are realized by the capacitance ratio of the capacitors in the adders 10, 14 and 15.

More specifically, as shown in FIG. 1, four integrators 1 to 4 are connected in series, and each output of these integrators is connected to each weight via four feedforward paths 5 to 8. After being multiplied by the coefficients a _{1 to} a _4, they are added by the feedforward adder 10, the addition result is quantized by the 1-bit quantizer 11 into 1-bit output data, and the quantized value is It is fed back to the input section of the first-stage integrator 1 via the feedback paths 12 and 13. That is, this feedback path includes a delay unit 12 for one sample time and a gain setter 13
The output of this path is added to a new input signal by the first-stage adder 14 and input to the first-stage integrator 1.

Input X in the ΔΣ modulator having the above configuration
The relationship between _(Z) and the output Y _(Z) is that the transfer function of the fourth-order loop 15 including all the circuits from 1 to 10 is Q _N , the quantization noise by the 1-bit quantizer 11 is H _{(Z )} ,

[0014]

[Equation 1]

It is expressed as Baseband (0Hz ~ 2
2 kHz),

[0016]

[Equation 2]

From

[0018]

[Outer 1]

Since H _(Z) basically has a fourth-order integral characteristic, H _(Z) >> 1. Therefore, the above equation (1) becomes

[0020]

[Equation 3]

It is represented by the approximate expression In other words, the quantization noise Q _N is 1 / H _(Z) multiplied by the noise shaping characteristics with 1 bit ΔΣ modulated output Y _(Z) are obtained in baseband.

From the above equation (2), the larger H _(Z) is,
It can be seen that Q _N / H _(Z) is reduced, and as a result, the S / N ratio is improved. Therefore, the transfer function H of the fourth-order loop 15
_The higher the order of _(Z), the better the S / N ratio, and the value of the S / N ratio is the weighting coefficient values a _{1 to} a _{4 of the} feedforward paths 5 to 8 and the local feedback path 9. It is determined by the weighting factor value b ₁ . The local feedback path 9 inserts a double root zero point in the quantization noise spectrum of ΔΣ modulation, and is effective for improving the S / N ratio, but as a ΔΣ modulator. It is not a mandatory requirement.

[0023]

However, in the conventional example of FIG. 1, since the fourth-order loop 15 is composed of an analog integrator or the like, the order of the transfer function is increased to further improve the S / N ratio. It was difficult to do so, and it was not suitable for mass production in LSI.

In view of this point, the present invention solves the problems of the conventional types (a) and (b) by realizing a high-order digital ΔΣ modulator, and the LSI has good analog characteristics. The present invention aims to provide a D / A converter that can be easily mass-produced in. However, if an attempt is made to implement a digital delta-sigma modulator based on the architecture by applying the delta-sigma modulator shown in FIG. 1 by simple digitization, the weighting factors easily realized by the analog switched capacitor network shown in FIG. The calculation of a _{1 to} a ₄ , g ₀ , b _1, etc. requires multi-bit multiplication, which causes a new problem that the circuit scale becomes huge. Also, in the audio field, a multi-channel D / A converter of 2 to 4 channels is required, and the operation rate is 64F _S =
Although it is as fast as 3.072 MHz, the number of bits to be operated is as large as 16 bits or more. Therefore, in order to achieve the intended purpose, there are problems to be solved in terms of circuit scale and high-speed operation. There is.

Therefore, in view of the above points, an object of the present invention is a digital Δ which has a small circuit scale and can operate at high speed.
It is to provide a Σ modulator.

It is another object of the present invention to provide a multi-channel digital ΔΣ modulator having a small circuit scale for time-division operation.

[0027]

To achieve the above object, the present invention provides a plurality of m accumulation means connected in cascade for accumulating multi-bit input digital signals X _(Z) , and the m accumulation means. each of a ₁ with respect to the accumulation result output from the accumulating means
Is multiplied by a weighting factor of ~a _m, feedforward adder means for summing the multiplication results, the addition result of the feedforward adder means based on predetermined criteria, than the input digital signal X _(Z) Requantization means for requantizing the digital output Y _(Z) having a small number of bits, and a predetermined feedback value corresponding to the requantization value Y _(Z) of the requantization means are applied to the input digital signal X _{(Z ) With} m
And a feedback means for inputting to the first stage of the accumulation means of the number of accumulation means, and said feedforward adder means and power weighting factors 2 of the a ₁ ~a _m, multiplication of the polymerization viewed coefficient Is realized by bit shift.

In the present invention, preferably, the m accumulation means are a plurality of n-channel input digital signals X.
_{1 (Z) to Xn (Z)} can be sequentially input in the order of channels, and each accumulating means has one multi-bit adder and an n-word shift register, and the n-word shift register The output of the multi-bit adder is input to the first word of the above, the output of the n-th word is fed back as the accumulation data of the multi-bit adder, and The requantized values Y _{1 (Z) to} Y _{n (Z)} are sequentially output as a result of all the calculations being performed at an operation rate that is n times the output rate of the channel. it can.

Further, according to the present invention, preferably, either one or both of the initial setting means and the abnormal resetting means are provided during the shift transfer from the first word to the nth word of the n-word shift register. It can be characterized by being arranged.

Further, in the present invention, preferably, each of the requantized values Y _(Z) or Y1 _{(Z) to} Yn _(Z) of the requantization means is 1-bit data, and the first stage The predetermined feedback value to the accumulator means of the input digital signal X
_(Z) or an integer multiple of the maximum value of X _{1 (Z) to} X _{n (Z)} ,
And the feedback value and the input digital signal X
_{The addition with (Z)} or X _{1 (Z) to} X _{n (Z)} is realized by using the accumulator adder in the accumulator at the first stage.

[0031]

According to the present invention, the cumulative result output from the m cumulative means of 2 or more m cascaded to which the sampled multi-bit digital signal X _(Z) is input is a.
In feedforward adder means for summing it is multiplied by ₁ ~a _m becomes the weighting factor, the a ₁ ~a _m becomes the weighting factor 2
Since it is a power of 10 and the multiplication is realized by bit shifting of the wiring between blocks, a multiplier is not required. Therefore, the circuit scale is small, and high-order operation that enables high-speed operation and multi-channel time sharing can be used. A digital ΔΣ modulator can be realized. Moreover, since the requantized output can be converted into 1-bit data that is slower than before, it is easy to mass-produce an analog circuit for D / A converting this 1-bit data, and to improve analog characteristics. I can contribute.

Further, in another aspect of the present invention, each of the m accumulating means capable of sequentially inputting two or more n-channel digital signals X _{1 (Z) to} X _{n (Z)} is one. It consists of a multi-bit adder and an n-word shift register.
The output from the adder is connected to the first word of the words, and the output of the nth word is fed back as the accumulation data of the adder. All the calculations are performed at the double operation rate, and the outputs Y _{1 (Z) to} Y _{n (Z)} are sequentially output, so that the calculation processing is performed in a time-division manner, so that the circuit scale is small. A digital ΔΣ modulator for a channel can be provided.

[0033]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Here, as a specific example, F _S = 48 kHz
64F _S = 3.072MHz obtained by oversampling a z, 16-bit digital audio signal by 64 times,
Inputs a 16-bit digital signal and outputs 64F _S digital data requantized to a smaller number of bits than the input while realizing noise shaping with a small quantization noise in the baseband (0 Hz to 22 kHz). A case in which the present invention is applied to a high-order ΔΣ modulator that does this will be described below.

In the following embodiments, the case where the number of requantization bits is 1 will be described, but this is for the purpose of simplifying the description, and the contents of the present invention described below are requantization. Even when the number of bits is plural, it can be applied as it is. In addition, as the order of the ΔΣ modulator, S / S that a 16-bit digital input signal can have
In order to realize the N ratio limit value of 97.8 dB by 64 times oversampling and 1-bit quantization ΔΣ modulation, the case of the 4th order (m = 4) is selected as an example. The present invention can be applied to configurations of various orders and oversampling ratios depending on the target to be obtained.

Since the basic operation of the 4th-order 1-bit ΔΣ modulator in the following description is the same as that of the conventional example shown in FIG. 1, the description thereof will be omitted.

(First Embodiment) FIG. 2 shows the circuit configuration of the first embodiment of the present invention when the weighting factors a _{1 to} a ₄ of the feedforward path are set to powers of 2. Input signal X _(Z) is 16 bits, 64F _S = 3.072 MHz
, And each integration circuit is composed of 21 to 24 digital accumulators, that is, multi-bit adders (accumulators) and accumulation registers. Each of the accumulators 21 to 24 has K _{1 to} K ₄ times the operation space with respect to its input. That is, the integration gains of the accumulators 21 to 24 are 1 / K ₁ to 1 / K ₄ , and the values of these gains are set to the powers of 2, so multiplication is not necessary and the accumulation of each stage is performed. The output of the calculator is directly connected to the input section of the next stage by bit shifting of the inter-block wiring.

The feedforward
Paths 5-8 and feedforward adder 10, and 1
The bit quantizer 11 has a capacity of 25 to 25 in the embodiment of FIG.
It consists of 28 feedforward paths and 29 adder quantizers. As an example, the values of the weighting factors a _{1 to} a ₄ are

[0039]

[Equation 4]

When set to a power of 2, the respective feedforward paths 25 to 28 have respective accumulators 21 to 21.
A specific multiplication circuit such as a multiplier is provided by directly sending the output of 24 to the adder / quantizer 29 through the inter-block wiring that is bit-shifted by 4 bits, 3 bits, 2 bits, and 1 bit to the LSB side. Substantially without a _{1 to} a ₄
It is possible to multiply by the weighting factor of

The addition quantizer 29 is actually composed of three multi-bit adders 29a to 29c. Multi-bit adder 29a adds the data from feedforward paths 25 and 26, multi-bit adder 29b adds the data from feedforward paths 27 and 28, and the two addition results of these multi-bit adders Are added by the multi-bit adder 29c in the subsequent stage, whereby the sum of the data from the four paths can be obtained. For 1-bit quantization, it suffices to determine whether the total sum is positive or negative and output the result. Therefore, the sign bit of the addition result of the adder 29c is output as this determination result, that is, the 1-bit quantized output.

The 1-bit quantized output is multiplied by a gain g ₀ via a feedback path 33 and fed back to the input adder 34, and is fed to the new input / output data X _(Z) output from the input register 31. Multi-bit adder 34
Is added to the first stage accumulator 21.

Here, assuming that the positive and negative full-scale values of the input data X _(Z) are x _max and -x _max , the value Y _(Z) of the 1-bit quantized output is positive or negative full. The scale values x _max and −x _max are expressed, and this is g _0.
Doubled and fed back. Therefore, this is Y
_{When (Z)} = 1 (positive), -g ₀ · x _max is changed to Y _(Z) =
When 0 (negative), it means that + g ₀ · x _max is added to new input data X _(Z) . Where 1 and 0
Is used to represent positive and negative in 1-bit data, and 0 represents negative. When the data format is 2's complement format, the sign bit of the addition result of the adder 29c is represented by 0 when the determination result is positive and by 1 when the determination result is negative. This is inverted by the inverter 30 and output as Y _(Z) .

Further, in this embodiment, the feedback loop 33 is provided with the gain g _0. This shows the relative relationship with the input X _(Z), and a gain of 1 / g _{0 is applied} between the inputs. It is completely equivalent when the gain of the feedback system is set to 1 by providing it. Further, the effect of the delay Z ⁻¹ of the feedback system described above in the formula (1) is the same no matter where it is placed in the closed loop of the entire system. In the present embodiment, the accumulation in each accumulator 21 to 24 is performed. Automatically incorporated into register operation.

With the above configuration, the 4th-order 1-bit ΔΣ modulator is configured by a digitized circuit, and a multiplier or the like is not required, and each weighting coefficient is configured only by bit shifting of inter-block wiring. Therefore, according to this embodiment, a ΔΣ modulator having a small circuit size and capable of high-speed operation is realized.

FIG. 3 is a diagram for making it easier to understand the bit shift of the above-mentioned inter-block wiring. Particularly, the outputs of the two 20-bit accumulators 35 and 36 are 4 bits, respectively.
17-bit adder 37
7 shows a state of inter-block wiring when the data is transferred to the block. That is, the outputs QA5 to QA2 of the 20-bit accumulator 35
0 is shifted by 4 bits in the lower direction and input to the input ports A1 to A16 of the 17-bit adder 37, and outputs QB4 to QB20 of the 20-bit accumulator 36 are shifted by 3 bits in the lower direction and added to the 17-bit adder. It is input to the other 37 input ports B1 to B17. As a result, a power of 2 operation is realized without the need for a multiplier or the like, and the operation processing for requantization can be performed with a simple circuit scale and high-speed operation. The accumulator 35 described above is the accumulator 2 of FIG.
1, 23, and the accumulator 36 is the accumulators 22, 24 of FIG.
The adder 37 corresponds to the adders 29a and 29b in FIG. 2, respectively.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention when the present invention is applied in order to realize a digital ΔΣ modulator for a plurality of channels in which each arithmetic processing is time-divisionally performed for each channel. 2 shows a circuit configuration of a second embodiment. here,
The case of 2 channels will be described as a specific example.
It is apparent from the following description that the configuration of this example is similarly applicable to the case of three or more channels.

In FIG. 4, the input register and the accumulation register of each accumulator are two-word shift registers REG1 (45, 41 to 44) and REG2 for two channels.
(50, 46 to 49), and the inputs X _{1 (Z)} and X _{2 (Z)} for two channels are shift registers 45 and 5.
Each time it is alternately input via 0, the same arithmetic circuit is used to alternately generate and output the outputs Y _{1 (Z)} and Y _{2 (Z)} for two channels. Operation clock M commonly supplied from the clock supply circuit 40 to each of the shift registers
CK has an operating rate of 64F _S = 3.0 for each channel.
If it is 72 MHz, twice that, 128 F _S =
It is 6.144 MHz. 1 of this operation clock MCK
Clock calculation period 1 / 6.144 MHz ≈ 163 ns
The operation for one of the two channels, the 1-bit output, and the operation preparation for the next channel are executed.

That is, each second shift register REG
2 (46 to 49) outputs the accumulated data of one channel up to the previous time through the self-loop path in each accumulator, the path to the next-stage accumulator, and the feedforward adder. A series of operations such as the 1-bit output after passing through the feedback path and the addition to the new input after passing through the feedback path to the accumulator in the first stage are performed, and each first shift register R
It is taken into EG1 (41 to 44). At the same time, each first
The accumulated data of the other channel stored in the shift register REG1 (41 to 44) of the above is moved to each second shift register REG2 (46 to 49) so that it can be used for calculation in the next cycle. Become. By repeating the above operation, a simple 2-channel time-share type digital ΔΣ modulator can be realized without increasing the number of arithmetic circuits having a large circuit scale.

In this embodiment, shift registers REG1 and REG2 are used as registers for two channels each.
However, (i) the multiplexer for selecting between channels becomes unnecessary, and (ii) the delay time by the multiplexer can be omitted from the main operation path.
(iii) Since the same clock can be supplied to each register,
This is because it is possible to contribute to a reduction in circuit scale and an increase in calculation speed due to advantages such as simple control.

Further, in the present embodiment, the circuit 5 for setting the initial state of operation and resetting at the time of abnormal operation.
1-54 to the first shift register REG1 of each accumulator
And the second shift register REG2.
The circuits 51 to 54 have a function of initializing the accumulation register REG2 when the operation of the ΔΣ modulator of this example is started, and of setting the value of the register REG2 to a predetermined value when an abnormality occurs during operation, that is, during oscillation. This circuit 51-54
May be placed anywhere in the entire system. However, especially when the same arithmetic circuit is shared by a plurality of channels in a time-sharing manner as in the present embodiment, these circuits 51 to 52 are registers requiring high-speed operation. It is very disadvantageous to increase the delay time by inserting it in the operation path from REG2 to register REG1. Therefore, in the present embodiment, the circuits 51 to 51 are provided on the path between the shift transfers from the register REG1 to the register REG2.
By disposing 54, it is possible to contribute to speeding up the operation path from the register REG2 to the register REG1.

Further, the above-mentioned abnormality during operation is a typical overflow due to the finite number of bits of the accumulator, but in order to avoid this overflow, the present circuits 51 to 54 are The accumulation result of each time taken into the register REG1 is always checked, and if the accumulated result is equal to or more than a predetermined value (threshold value), it is determined that oscillation has occurred, and the register REG2 has a predetermined value for returning to a normal state. Send the reset data to a value (for example, all zeros). As a result, the registers REG2 to REG
It is possible to provide a stable digital ΔΣ modulator with a simple circuit configuration without deteriorating the speeding up of the calculation path to 1.

FIG. 5 shows the configuration of one of the accumulators of FIG. 4 in more detail. Register 62 is register 41-44 of FIG. 4, register 63 is register 46 of FIG.
˜49 and the circuit 64 correspond to the circuits 51 to 54 of FIG. 4, respectively. In FIG. 5, 62 registers REG1 and 63 registers RE are used as cumulative shift registers for two channels.
G2, and 61 accumulation adders are each composed of 20 bits, and 64 initialization and abnormal reset circuits are inserted and connected between the registers REG1 and REG2. Since the accumulation gain of this accumulator is 1/2, the input data is 19 bits D1 to D19. As for the adder 61, a normal full adder (full adder) is 20
Carry ripple adder (Carry-Ripple-A)
dder) and its data format is two's complement format. 20-bit first accumulation shift register REG1
(62), the second cumulative shift register REG2 (63), and the register for storing the 2-bit previous data in the initialization / abnormality reset circuit 64 are the same 128F _S = 12.28 MHz from the clock supply circuit 40. This clock MCK is operated by the clock MCK of
Data is shifted and transferred between registers every cycle.
The registers REG1 and REG2 store data of different channels.

2 in the initial setting / abnormality reset circuit 64
The bit register is the first accumulation shift register REG1.
Top 2 of the previous data of channels stored in (62)
Bits (J19, J20) are stored. In this example, the purpose is to detect the occurrence of overflow at the time of abnormality,

[0055]

[Outside 2]

[0056]

[Outside 3]

It is indicated that the above (a) has occurred.
Or in case of (b)

[0058]

[Outside 4]

Second accumulation shift register REG2 (63)
Data transferred to is reset to all zeros. Also, in the initial setting, at the beginning of operation,

[0060]

[Outside 5]

The contents of the second accumulation shift register REG2 are set to all zeros.

In the above judgment (a) or (b), the input is 19 bits, that is, the operation space of the accumulator is 1 bit or more larger than the number of bits (19 bits) of the input data. Assuming that
In Σ modulation, the cumulative gain is often set to ½ or less, so this overall condition can be a very effective determination condition. Further supplementing the above (a) and (b),

[0063]

[Outside 6]

This shows that the accumulated result up to the previous time was a value of +0.5 or more when normalized in the 20-bit space, so the result of adding a new 19-bit input is a positive value. There should be. Therefore, the register REG1
Q20 ', which is the sign bit of, must be 0 at this time. Therefore, when Q20 '= 1, it is recognized that a positive overflow has occurred and the sign bit has been determined.

[0065]

[Outside 7]

Since the accumulated result up to the previous time is a value of −0.5 or less when normalized in the 20-bit space, the value obtained by adding a new 19-bit input remains a negative value. There should be. Therefore, the sign bit Q20 'of the register REG1 must be 1 at this time. Therefore, when Q20 '= 0, it is recognized that a negative overflow occurs and the sign bit is inverted.

The configuration of the embodiment shown in FIG. 5 can realize overflow detection by checking only 3 bits without the need to check all 20 bits, and is already used without providing a new control circuit. A very simple circuit in that one clock supply circuit 40 can be used, that the initial setting and the reset at the time of abnormality are shared by the same reset circuit, and that a single circuit can be shared for two channels. Can be achieved with. Moreover,
Since the delay of reset or abnormality detection can be omitted from the operation path from the register REG2 to the register REG1 including the carry propagation delay, etc., it is simple and fast.
A digital ΔΣ modulator for a channel can be realized.

In the embodiment circuit of FIG. 5, the initial setting value and the reset value at the time of abnormality are all zero, but this is for the purpose of simplifying the circuit description, and reset values other than all zero are set. It is needless to say that the use, the setting of the initial set value and the reset value at the time of abnormality, and the like can be easily realized by a similar circuit configuration.

(Third Embodiment) Next, referring to FIGS. 6 and 7, one multi-bit adder is omitted from the ΔΣ modulators of the first and second embodiments described above, and the circuit of A third embodiment of the present invention for simplification will be described. This example
The gain g ₀ of the feedback path shown in FIG. 2 or 4 is set to an integer value of 2 or more, and the first-stage adder (see FIGS.
Of the adder 34) is omitted. Below, g ₀ =
This embodiment will be described with reference to FIGS. 6 and 7 showing the adder for accumulation in the first-stage accumulator for the case of 2 and the case of g ₀ = 3. This is equivalent to a case where the feedback gain is set to 1 by giving a gain of / g ₀ . Further, even in the case of g ₀ ≧ 4, it can be easily analogized by expanding the method described below.

FIG. 6 shows that gain g ₀ = 2 and integration coefficient K ₁ =
2 ³ = 8 (see FIG. 1), the first-stage adder (34) shown in FIGS. 2 and 4 is eliminated, and the input terminals D1 to D16 of the 19-bit accumulating adder are omitted. 16-bit data x ₁ ~x ₁₆ input X _(Z) is input directly,
To D17 of adder input terminal

[0071]

[Outside 8]

Is input and D18 and D of the adder input terminals are input.
The 1-bit output value Y _(Z) which is the quantization result is input to 19. In the following description, the output value Y _(Z) is expressed as Y _(Z) = 1 when the quantization result is positive and Y _(Z) = 0 when the quantization result is negative, and The data format used for all operations including the data X _(Z) is represented in 2's complement format with the left side as the MSB side.

When the input data X _{(Z) in} FIG. 6 is expressed by 19 bits, the upper 3 bits are sign bit extended,

[0074]

(5) x ₁₆ x ₁₆ x ₁₆ x ₁₆ x ₁₅ x ₁₄ x ₁₃ x ₁₂ x ₁₁ x ₁₀ x ₉ x ₈ x ₇ x ₆ x ₅ x ₄ x ₃ x ₂ x ₁ (3) and Y _{( When Z)} = 1 (quantization result is positive), the feedback value is -2 · FS (FS is the maximum value of input 16 bits),

[0075]

[Equation 6] 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... (4) must be added. The result of adding the data of equations (3) and (4) is that when x ₁₆ = 0 (input X _(Z)
Is a positive value)

[0076]

[Equation 7] 1 1 1 x ₁₆ x ₁₅ · · · · · · · · · · · · x ₂ x ₁ ... (5) When x ₁₆ = 1 (input X _(Z) is a negative value), 1 1 0 x ₁₆ x ₁₅ · · · · · · · · · · · · x ₂ x ₁ ... (6), and the data of equations (5) and (6) are

[0077]

[Equation 8]

It is expressed as

Next, when Y _(Z) = 0 (the quantization result is negative), the feedback value becomes + 2FS,

[0080]

[Formula 9] 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... (8) is added to the input data of the equation (1), and the addition result is x ₁₆ = When 0,

[0081]

[Formula 10] 0 0 1 x ₁₆ x ₁₅ ··· · · · · · · · · · x ₂ x ₁ ... (9) When x ₁₆ ,

[0082]

[Equation 11] 0 0 0 x ₁₆ x ₁₅ ··············· x ₂ x ₁ (10), and the data of equations (9) and (10) are also represented by Expressed.

From the above, the circuit configuration shown in FIG.
It is understood that the input x _(z) and the feedback amount ± g ₀ · FS are automatically added and input to the first-stage accumulator (first-stage accumulator register) while eliminating the first-stage adder. it can.

Next, FIG. 7 shows the case where g ₀ = 3 and K ₁ = 8. Again, the first stage adder is eliminated and the accumulating adder has 19 bits. At this zero, since the value of g ₀ is odd, lower 15-bit data x _{1 to} x 15 excluding the sign bit of X _(Z) is input to D _{1 to} D ₁₅ of the input terminal of the 19-bit accumulating adder. It is directly input, the inversion x ₁₆ which is the inversion value of the sign bit x ₁₆ is input to the input terminal D16 of the adder, and the 1-bit output value Y _(Z) which is the quantization result is input to the input terminal D17 of the adder. Inverted Y _(Z) which is the inverted value of Y _(Z) is input to D18 to D19 of the input terminals of the adder.

When Y _(Z) = 1, from g ₀ = 3, the feedback value is -3 · FS,

[0086]

[Equation 12] 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (11) is added to the data of the above equation (3). If x ₁₆ = 0, the addition result is

[0087]

[Equation 13] 1 1 0 1 x ₁₅ x ₁₄ ··· · · · · · · · · x ₂ x ₁ (12), and when x ₁₆ = 1

[0088]

[Equation 14] 1 1 1 0 x ₁₅ x ₁₄ · · · · · · · · · · · x ₂ x ₁ … (13)

[0089]

[Equation 15]

It is expressed as follows.

On the other hand, when Y _(Z) = 0, the feedback value is + 3 · FS,

[0092]

## EQU16 ## 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... (15) is added to the data of the above formula (3), and the addition result is x ₁₆ = 0. in case of,

[0093]

[Expression 17] 0 0 1 1 x ₁₅ x ₁₄ ············· x ₂ x ₁ (16), and when x ₁₆ = 1

[0094]

[Expression 18] 0 0 1 0 x ₁₅ x ₁₄ ············· x ₂ x ₁ (17), which are both expressed by the above equation (14).

As described above, when g ₀ = 3, the input X _(Z) and the feedback amount ± g ₀ · FS are automatically generated by the circuit configuration shown in FIG. 7 while eliminating the first-stage adder. Is added to the first stage accumulator (first stage accumulation register)
You can understand that it is entered in.

Obviously, the configuration described above can be expanded by the same method even when g ₀ = 4 or more. One of the main parts of the method is that when g ₀ = n and n is an even number, the sign bit x of the input X _(Z) is x.
₁₆ is input to D16 as it is, and when n is an odd number, the inversion x _{16 of the} sign bit is input to D17. In any case, according to the present embodiment, the circuit scale can be greatly reduced by eliminating the 19-bit first-stage adder, and the delay of the path having the largest operation delay can be reduced. The effect can be expected to be great in realizing a multi-channel digital ΔΣ modulator as in the second embodiment, which is required.

[0097]

As described above, according to the present invention,
It is possible to realize a high-order digital ΔΣ modulator capable of high-speed operation and use of multi-channel time sharing without requiring a multiplier, and moreover, the requantization output can be 1-bit data which is slower than before. Since it is possible, this Δ
This has the effect of facilitating mass production of an analog circuit for D / A converting the output of the Σ modulator and contributing to improving analog characteristics.

Further, according to the present invention, the same arithmetic circuit is used for each channel in a time-division manner, so that it is possible to provide a multi-channel digital ΔΣ modulator having a small circuit scale.

[Brief description of drawings]

FIG. 1 is a conventional fourth-order 1-bit Δ composed of analog elements.
It is a block diagram which shows the structure of a (sigma) modulator.

FIG. 2 shows the configuration of the first embodiment of the present invention, in which the weighting coefficients a _{1 to} a ₄ of the feedforward path are set to powers of 2 and the multiplication of each coefficient is performed by the bit shift of the wiring between blocks. It is a block diagram which shows the structure of the 4th-order 1-bit quantization digital (DELTA) (SIGMA) modulator when implement | achieved.

FIG. 3 is a block diagram showing details of bit shift by inter-block wiring in FIG.

FIG. 4 is a block diagram showing a configuration of a 2-channel time-share type digital ΔΣ modulator according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing the initial stage setting and abnormal reset circuit of FIG.
It is a circuit diagram which shows the detailed structural example at the time of arranging between the accumulation registers of the digital delta-sigma modulator for channels.

FIG. 6 is a diagram showing an addition circuit of the input X _(Z) and the feedback −g ₀ Y _(Z) in the first stage accumulation adder when the feedback gain g ₀ is 2 in the third embodiment of the present invention. It is a circuit diagram which shows a structure.

FIG. 7 is likewise a circuit diagram showing a configuration when g ₀ is 3.

[Explanation of symbols]

 1-4 Integrator 5-8, 25-28, 33 Feedforward path 10, 14, 15, 29a-29c, 37 Adder 11 1-bit quantizer 13 Gain setter 21-24, 35, 36 Accumulation 29 adder / quantizer 30 inverter 34 first-stage adder 40 clock supply circuit 41-45, 62 first shift register REG1 46-50, 63 second shift register REG2 51-54, 64 initial setting / abnormality reset circuit 61 Adder for accumulation

Claims (4)

[Claims] 1. A plurality of m accumulation means connected in cascade for accumulating a multi-bit input digital signal X _(Z) , and an accumulation result output from the m accumulation means, respectively. multiplied by the weight coefficient of a ₁ ~a _m, feedforward adder means for summing the multiplication results, based on the sum of the feedforward adder means to a predetermined criterion, wherein the input digital signal X _{(Z )} and re-quantization means for re-quantizing the smaller number bit digital output Y _(Z) than said input digital signal a predetermined feedback values corresponding to the re-quantized value Y _(Z) of該再quantizing means and a feedback means for inputting to the first stage of the accumulation means of said m accumulators means together with X _(Z), and the feedforward adder means the a ₁ ~a _m
Is a power of 2 and multiplication of the weighting factor is realized by bit shifting.
Σ modulator. 2. The m accumulating means can sequentially input a plurality of n channels of input digital signals X _{1 (Z) to} X _{n (Z)} in the order of channels, and each accumulating means has one multi-input. It has a bit adder and an n-word shift register, the output of the multi-bit adder is input to the first word of the n-word shift register, and the output of the n-th word is the multi-bit. The requantized value Y ₁ is fed back as the accumulation data of the adder, and as a result of performing all the calculations from the requantization means at the operation rate of n times the output rate of each channel. _(Z) to Y digital ΔΣ modulator according to claim 1, n _(Z), characterized in that the sequentially output. 3. An initial setting means or an abnormal resetting means or both of them are arranged between the first word to the nth word of the n-word shift register during the shift transfer. The digital ΔΣ modulator according to claim 2. 4. Requantization value Y _{(Z) of} said requantization means,
Alternatively, each of Y1 _{(Z) to} Yn _(Z) is 1-bit data, and the predetermined feedback value to the accumulating means at the first stage is the input digital signal X _(Z) or X1 _(Z). ~ X _{n (Z)}
Is an integer multiple of the maximum value of, and the feedback value and the input digital signal X
_(Z), or claims 1, characterized in that X ₁ and addition of the _{(Z) ~X} n _(Z) is realized with an accumulating adder in the accumulator means of the first stage 3 The digital ΔΣ modulator according to any one of items 1 to 5.