JPH04207716A - A/d converter - Google Patents

Abstract

PURPOSE:To simplify an analog circuit by converting plural analog input signals to digital data in a time division with an A/D converter, processing this digital data converted in a time division with a logic circuit and obtaining the data in a desired timing. CONSTITUTION:In the case of deriving the data in a necessary timing, for instance, the timing of An from the data An-1, Bn-1, Cn-1, An, Bn, Cn... subjected to A/D conversion by different timings, An is used as data DA as it is, (Bn-1+2Bn) obtained by adding Bn-1 preceding by two of An and 2Bn doubling Bn succeeding by one of An is used as data DB, and (2Cn-1+Cn) obtained by adding 2Cn-1 doubling Cn-1 preceding by one of An and Cn succeeding by two of An is used as data DC. In such a manner, data in a necessary timing can be derived by interpolation from the data subjected to A/D conversion by different timings. Thus, by executing the interpolating executed by a logic circuit instead of a sample-holding circuit, an analog circuit is simplified, and S/N is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion device that obtains digital data at a desired timing from a plurality of analog input signals.

[Prior Art] Generally, among the image pickup devices and their signal processing circuits used in digital electronic still cameras or camcorders, circuits using single-plate complementary color filter type image pickup devices use a luminance signal YI.
(and the signal YL regarding the color component.

R and B are generated. When A/D converting these signals, it is necessary to sample the signals YL, R, . . . B, particularly regarding the color components, at the same time.

FIG. 4 shows an example of a conventional A/D conversion device.

That is, the A/D converter ADI is controlled by the clock CLK and converts the analog input signal A into digital data DA and outputs it, and the A/D converter AD2 is controlled by the clock CLK and converts the analog input signal B into digital data DB.
The A/D converter AD3 outputs the clock CL.
Controlled by K, the analog input signal C is converted into digital data DC and output. However, such a conventional A/D converter uses three A/D converters, which has the disadvantage of increasing cost.

FIG. 5 shows another example of a conventional A/D converter, and FIG. 6 is a timing chart showing signals of each part in FIG. That is, the sample hold circuit SH1 receives the pulse signal SP.
Sample and hold analog human input signal A controlled by
The sample and hold circuit SH2 is controlled by the pulse signal SP to sample and hold the analog input signal B, and the sample and hold circuit SH3 is controlled by the pulse signal SP to sample and hold the analog input signal C. The output of the sample hold circuit SHI is input to the A/D converter AD4 via an analog switch S1 controlled by a pulse signal SA, and the output of the sample hold circuit SH2 is input to an analog switch S2 controlled by a pulse signal SB. The output of the sample hold circuit SH3 is input to the A/D converter AD4 via an analog switch S3 controlled by a pulse signal SC. A/D converter AD4 has analog switches 81 to S3.
The multiplexed input signal is time-divisionally converted into digital data by D-type flip-flops Fl and F2.
．． Output to F3. Flip-flop F1 controls digital data input from A/D converter AD4 using clock φ and outputs digital data DA, and flip-flop F2 outputs digital data input from A/D converter AD4 using clock φ8. The flip-flop F3 controls and outputs digital data DB, and the flip-flop F3 uses the digital data input from the A/D converter AD4 as a clock φ. to output digital data DC. Therefore, the digital data time-divisionally converted by the A/D converter AD4 is D
Type flip-flops Fl, F2. Synchronized at F3.

[Problems to be Solved by the Invention] However, it is difficult to create a high-speed, high-precision sample-and-hold circuit, and pulse noise easily mixes into the analog signal, resulting in a poor S/N ratio. Also, as can be seen from the timing chart in Figure 6, setting the sampling frequency to fsc (3,579545 MHz) requires a clock of 3 fsc, or a clock of 4 fsc, which is often used to create the timing of video signals. f s
In order to match the phase with the clock of C, it is necessary to use a 12 f sc oscillator or a synchronization circuit using a PLL circuit, which has disadvantages such as increased cost and complexity of the circuit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an A/D conversion device that can improve the S/N ratio, reduce the size, and reduce the cost by simplifying the analog circuit. purpose.

[Means for Solving the Problems] In order to solve the above problem, the present invention provides means for selecting one signal from a plurality of analog input signals, and A for converting the analog signal selected by this means into digital data. It consists of a /D converter and a logic circuit that obtains data at a necessary timing by interpolation from data A/D converted at different timings by the A/D converter.

[Function] The present invention converts a plurality of analog input signals into digital data in a time-divisional manner using an A/D converter, and processes the digital data converted in a time-divisional manner in a logic circuit to obtain necessary timing. Find the data by interpolation.

[Example] An example of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the A/D conversion device of the present invention, FIG. 2 shows a conceptual diagram of the operation of the invention, and FIG. 3 shows a timing chart showing signals of each part of FIG. 1. In FIG. 1, the timing generator TM is 4 fs from the oscillator O8C.
The reference signal of c is input, and the clocks CLKI, CLK2
．． φ1~φ,.

Generate pulse signals SA, SB, SC, KA, KB, KC, output clock CLK1 to A/D converter AD, and output clock CLK2 to each flip-flop FF7 to FF.
9, clocks φ1 to φ are output to D-type flip-flops FFI to FF6, respectively, and pulse signals SA and SB.

SC is output in correspondence to analog switches SWI to 5WW3, respectively, and pulse signals KA and KB are generated.

KC is outputted to data selectors DSI to DS3 in correspondence with each other. That is, the analog input signal A is input to the A/D converter AD via the analog switch SWI, which is controlled to turn on at the timing of the pulse signal SA, and the analog input signal B is turned on at the timing of the pulse signal SB. The analog human input signal C is input to the A/D converter AD via the analog switch SW2 controlled by
is connected to the A/D converter AD via an analog switch SW3 that is controlled to turn on at the timing of the pulse signal SC.
is input. As shown in FIG. 2, the output of the A/D converter AD is A n-1+ B n-1+C, l+ A,
, B, , C6, etc. are output in the following order. Here, if you want data at the timings ■, ■, ■, ■..., for example, at the timing ■, the output data DA uses Ao as is, and the output data DB uses B7-1 and B, . Using the value interpolated to .2, that is, 1/3 (B,, +2B,), the output data DC is 1/3, which is the interpolation of C,, -1 and C7 at a ratio of 2:1.
(2C,, +C,) and output these data. In addition, for the sake of simplicity in Figures 1 and 3, the respective output data DA, DB, and DC are multiplied by 3 and are calculated as 3A0°B.
, , +2B, , 2C, , , +C, are output.

The explanation will be given below based on FIGS. 1 and 3. In FIG. 1, the A/D converter AD is controlled by a clock CLK1, and converts analog input signals A, B, and C multiplexed by analog switches SW1 to SW3 into digital data Dr (A-, A--2) in a time-division manner. ,1,”')
, D2 (A-1.

A, + -=i, Ds (Bn, B-+2-...-
), D4 (Bo−+, Ba++−−), Ds(C, −2
, C, -...), D6 (C,, + Ca'+1・
...) and convert it into a D-type flip-flop FFI~
It outputs correspondingly to FF6. The D-type flip-flop FFI receives a clock φ. It outputs the digital data Q1 to the input terminal A21 of the adder ADD1 and also to the input terminal All of the data selector DSI. The D-type flip-flop FF2 is controlled by the clock φ3 and sends the digital data Q2 to the data selector DS2.
output to the input terminal Bll of. D type flip-flop F
F3 is controlled by clock φ1 and outputs digital data Q.
3 is output to the input terminal A22 of the adder ADD2 and is also output to the input terminal A12 of the data selector DS2.

D-type flip-flop FF4 is controlled by clock φ4 and outputs digital data Q4 to input terminal B12 of data selector DS2. D type flip-flop FF5
is controlled by the clock φ2 and outputs the digital data Q to the input terminal A2B of the adder ADD3 and also to the input terminal A13 of the data selector DS3. D-type flip-flop FF6 is controlled by clock φ and outputs digital data Qb to input terminal 813 of data selector DS3. The data selector DSI is controlled by the pulse signal KA, and outputs the digital data Q1 as the output Xll to the input terminal B21 of the adder ADD1 when the pulse signal KA is "1", that is, high level, and when the pulse signal KA is rOJ, that is, low level. Time output X1
1 and outputs the digital data Q2 to the input terminal B21 of the adder ADD1. The data selector DS2 is controlled by a pulse signal KB, and when the pulse signal KB is "1"
That is, when the level is high, the digital data Q is outputted as the output X12 to the input terminal B22 of the adder ADD2,
When the pulse signal KB is "0", that is, at a low level, the digital data Q4 is outputted as the output X12 to the input terminal B22 of the adder ADD2. The data selector DS3 is controlled by a pulse signal KC, and the pulse signal KC is "1".
That is, when the pulse signal KC is "0", that is, the low level, the digital data Q is output as the output X13 to the input terminal 82B of the adder ADD3, and when the pulse signal KC is "0", that is, the low level, the digital data Q6 is output as the output X1B to the input terminal 823 of the adder ADD3. Output. Adder ADD1 has output X2
1-A21+2XB21, the most significant bit of the data is shifted by 1 bit to the MSB side for the input on the 821 side of a normal full adder. The adder ADD2 inputs the most significant bit MS of the data to the 822 side input of the normal full adder so that the output is X22-A22+2xB22.
The one shifted by 1 bit to the B side is used. Adder ADD
3 uses the input of the B2B side of a normal full adder shifted by 1 bit to the most significant bit MSB side of the data so that the output becomes X23-A23+2xB2B.

In this case, the output
21. X22. X23 must be 2 bits wider than the bit width; for example, if the output of the A/D converter AD is 6 bits, the adder ADD 1°ADD2 . ADD3 is 8
Bitful adder is required. Therefore, adder A
3Q s and Ql+202 are obtained alternately at the output X21 of DD 1, and 3Q3 is obtained at the output X22 of adder ADD2.
and Q3+2Q4 are obtained alternately, and the output X231: of the adder ADD3 is obtained alternately as 3Q% and Qs +2Q6. The output X21 of the adder ADDI is input to the D-type flip-flop FF7, and this flip-flop FF7
is controlled by clock CLK2, and clock CLK2
Data DA is output in synchronization with the rising edge of . Adder A
The output X22 of DD2 is input to the D-type flip-flop FF8, and this flip-flop. Tsubu FF8 is clock CL
It is controlled by CLK2, and data DB is output in synchronization with the rising edge of clock CLK2. Adder ADD3 output X
23 is input to a D-type flip-flop FF9, which is controlled by a clock CLK') and outputs data DC in synchronization with the rising edge of the clock CLK2.
is output. D-type flip-flops FF7, FF8.9 are provided in consideration of delays in circuit elements. Therefore, the digital output data DA, DB, and DC appear simultaneously with a delay of two clocks by the D-type flip-flops FFI-9. In this case, the digital output data DA
, DB, and DC change with the period of the clock CLK2, but the actual sampling rate is 1.5 times the period of the clock CLK2. Furthermore, it is conceivable that errors may occur due to interpolation due to linear approximation, but the color components of the imaging system are
Since there is only a band of about MH2, fs is applied to clock CLK2.
Good image quality can be obtained even when using c (3,579545 MHz).

That is, as shown in the operational conceptual diagram of FIG. 2, data A is A/D converted at different timings. -1°B,,,C
n-1, A, , B, , C, ...... Necessary timing, for example, A. When obtaining data at the timing of , Afl is used as is as data DA, and B, -3, which is two places ahead of Ao, and B, which is one place after A, are used as data DB. 2B, which is doubled, and B-, which is added to
++2B, and as the data DC, 2C-+ which is double the Cn-1 one ahead of A, and C, two after A,
2c, , +c, which is the sum of , is used. By doing so, data at a necessary timing can be obtained by interpolation from data A/D converted at different timings.

As described above, by performing interpolation using a logic circuit instead of a sampling and holding circuit, data at the required point in time is obtained, which simplifies the analog circuit and
N improves. Furthermore, the logic circuit can be easily integrated into an IC, and the device can be made smaller.

In addition, a 3fsc clock is not required to sample three types of analog signals with fsc, and the circuit can be configured using only 4fsc of the video signal system.
Cost reduction becomes possible.

In the above embodiment, interpolation using linear approximation was used for data interpolation, but the present invention is not limited to this, and other methods such as interpolation using an Nth-order curve may be used.

[Effects of the Invention] As described above, according to the present invention, there is provided means for selecting one signal from a plurality of analog input signals, and A for converting the analog signal selected by this means into digital data.
It consists of an A/D converter and a logic circuit that processes the digital data converted by the A/D converter to obtain data at a desired timing. By converting the time-divisionally converted digital data into digital data and processing this time-divisionally converted digital data using a logic circuit to obtain data at the desired timing, the analog circuit can be simplified, and the S/N can be reduced. It is possible to improve the performance, reduce the size, and reduce the cost.

[Brief explanation of the drawing]

Figures 1 to 3 show one embodiment of the present invention.
The figure is a configuration explanatory diagram showing the A/D converter, and Figure 2 is the A/D converter.
A diagram for explaining the operational concept of the conversion device, Figure 3 is the same as Figure 1.
4 and 5 are configuration explanatory diagrams showing a conventional A/D conversion device, and 6.
The figure is a timing chart showing signals of each part in FIG. SWI~SW3...Analog switch, AD...A
/D converter, FF1-FF9...D flip-flop, DSI-DS3...data selector, ADD1-
ADD3... Adder. Applicant's agent Patent attorney Takehiko Suzue ■ ■ ■ ■ DA p2An-++An) Ar+ lAn
+2An++) i(2Arw+Arw)C) B
Bn-Ii (shi+2Bn) &Br++B+v)
B-. D C1cn-2”2cn-+)i2cn-++Cn)
Cn pcn+2crw) 12 Figure 'a6 Figure CL 1 Figure 3 CC Figure 4

Claims (1)

[Claims] Means for selecting one signal from a plurality of analog input signals; An A/D converter for converting the analog signal selected by the means into digital data; An A/D conversion device comprising: a logic circuit that obtains data at a necessary timing by interpolation from data A/D converted at a certain timing.