JPH0685670A - Method and system for sampling - Google Patents

Abstract

PURPOSE:To provide a sampling system which reduces distortion and a pattern noise generated in an interleave operation due to dispersion that exists among plural signal routes. CONSTITUTION:An input signal inputted from an analog input terminal 4 is sampled by applying the interleave operation at plural sample-and-hold circuits (1a, 1b), and the moving average of a sampling result is performed. In other words, the signal is delayed by the extent equivalent to the number of stages of the plural sample-and-hold circuits on the signal routes in addition to signal processors (8a, 8b) and signal delay devices (2a, 2b), and a result of adding the sampling result to the output of each delay device respectively in adders (3a, 3b) is outputted to an output terminal 6. Therefore, it is possible to relax the whole gain between mutliplexed routes or the coincidence of aperture time, etc., to accelerate sampling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling system, and more particularly to a sample hos having a sampling function.
The present invention relates to a sampling system that can be used for a field circuit, an AD converter, a switched capacitor filter, and the like.

[0002]

2. Description of the Related Art As a general sampling method, only a single sample and hold circuit is used. However, in this case, the sampling operation speed is limited by the sampling and holding circuit.

As one method for achieving a speed higher than that possible with a single sample and hold circuit, FIG.
The interleave method as shown in FIG. Here, a plurality of sample and hold circuits (16a to 16e)
Are arranged in parallel via the clock delay units (17a to 17d), the analog input signal input from the input terminal 15 is sampled by the interleave operation, and the signal held in each signal path is output to the selector 18. After that, it is output to the output terminal 19.

The sampling output by the interleave method includes distortion and pattern noise generated from the total variation existing between multiple paths. For example, in FIG.
As shown in (1), due to variations in gain between the two signal paths (gain 1, gain 2), sampling outputs v1, v2, ... Vn fluctuate as indicated by black circles with respect to a straight line input as indicated by a solid line. Alternatively, as shown in FIG. 13, variations in aperture time δt1 and δt that occur during sampling.
2 ..., the sampling outputs v1, v2, ... Vn fluctuate as shown by solid circles with respect to the straight line input shown by the solid line. As a result, sidebands can be formed symmetrically with the sampling frequency of the sample-hold circuit of each signal path and the harmonics up to the entire sampling frequency. Further, as shown in FIG. 14, the sampling outputs v1, v2, ... Vn also vary due to the overall offset error (offset 1, offset 2) between the signal paths, and the sample-hold circuit of each signal path is Pattern noise occurs at the sampling frequency that it has and harmonics up to the overall sampling frequency.

A two-stage sampling method (2-rank sampling in the English name) is known as a countermeasure for the variation in the aperture time existing in the signal path, and the details thereof are described in "K. Poulton, et al. ., A 1-GHz 6-bit ADC Sys
tem, IEEE J. Solid-State Circuits, vol. 22, No. 6,
pp. 962-970, Dec. 1987 ". In the above example, the AD conversion paths are multiplexed and interleaved in order to increase the speed of the AD converter. FIG. 15 shows a simple configuration example of the two-stage sampling method. In the sampling performed in advance, the single sample-hold circuit 20 common to the multiple signal paths is connected to the input terminal 15 to temporarily extract the instantaneous value of the input signal which changes every moment. The signal held for a certain period of time is further added to the next stage multi-sample hold circuit (1
6a to 16e, 17a to 17d) interleave, sample again, output terminal 19 via selector 18.
Output to. As described above, in the two-stage sampling method, the signal to be multi-sampled is temporarily sampled and held constant by the sample-hold circuit common to all signal paths, so that it is caused by the aperture error between the multi-paths. Distortion can be reduced significantly.

Generally, the multiplex structure using the interleave operation is (1) when it is impossible to achieve the required operation speed by using the current processing technology, or (2) the multiplex structure is used. It is desirable to adopt it when the overall power consumption can be reduced by reducing the operation speed of each signal path.
However, in the two-stage sampling method, the sample-hold circuit of the first stage has to operate at the entire speed, which is not suitable for the use of (1). In addition, even if the power consumption is reduced by the multiplex structure, the high-speed sample and hold circuit in the first stage consumes substantial power, which is not suitable for the use in (2). Further, although it is possible to suppress the aperture error between the multiple paths, the problem of the pattern noise generated from the distortion or the offset error generated from the overall gain error between the multiple paths cannot be solved.

[0007]

The second of the above-mentioned prior arts, that is, the multipath type sampling system provided with the interleave method is suitable for high speed or low power consumption. It is relatively difficult to achieve high precision because distortion and pattern noise are generated due to the overall variation existing between multiple paths.

A third party of the above prior arts, that is,
The multiplex configuration by the two-stage sampling method can reduce the distortion caused by the aperture error between the signal paths, but the effects of the gain error and the offset error are not improved, and the high-speed sample / hold circuit is provided in the first stage. Is required because
Power consumption is relatively high. Further, in the two-stage sampling method, since the operation speed is limited by the first-stage sample and hold circuit, it is impossible to achieve a speed higher than the operation speed obtained by the current processing technology even by the multiplex structure.

The object of the present invention is to solve the above-mentioned problems in the prior art, to make the circuit scale more complicated than the two-stage sampling method, and to generate it from the overall variation between multiple paths. It is an object of the present invention to provide a sampling system capable of reducing the distortion and the pattern noise that occur.

[0010]

The present invention is characterized in that the following two means are provided. First, the input signal is interleaved by a plurality of sample and hold circuits and sampled. Next, the sampling result is delayed in each signal path by the number of stages of the plurality of sample and hold circuits, and the outputs of the respective delay units are added.

[0011]

In the sampling system of the present invention,
High speed and low power are achieved by performing sampling in an iterative operation by a plurality of sample and hold circuits, and moving averages of the sampled results are used to perform overall sampling between multiple paths. The effect that the matching such as the gain and the aperture time can be relaxed is achieved.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a sampling system according to a first embodiment of the present invention, in which the number of stages of a plurality of sample and hold circuits existing in a signal path used for an interleave operation is shown. Is an example when L = 2.
In the figure, 1a and 1b are sample and hold circuits, and 2a and 2a.
Reference numeral b is a signal delay device, 3a to 3b are adders, 4 is an analog signal input terminal, 5 is a selector, and 6 is an output signal terminal. FIG. 2 is a diagram showing the clocks .phi.1 and .phi.2 shown in FIG. 1, and the clocks .phi.1 and .phi.2 have their phases inverted from each other.

Next, the operation of each part of the embodiment configured as described above will be described. The analog signal input from the analog signal terminal 4 is sampled and held by the interleave operation using the sample and hold circuits 1a and 1b and the clocks .phi.1 and .phi.2. The adder 3a adds and averages the output signal v2 of the sample and hold circuit 1b and the output signal v1 of the signal delay unit 2a output by the clock φ2, in other words, a moving average of 1/2 (v1 + v2). = V1 is obtained. Similarly, the adder 3b adds and averages the output signal v3 of the sample and hold circuit 1a and the output signal v2 of the signal delay unit 2b, which are output by the clock .phi.1, to obtain 1/2 (v2
+ V3) = V2 is obtained. As an example, sample ho
When the variation of the offset in the voltage circuit is the same as that of the conventional example described in FIG. 14, the moving average values V1, V2 ... Vn obtained by the embodiment of FIG. The error due to the variation of the offset is eliminated, and a stable output with a small error with respect to the input signal is output to the output terminal 6 via the selector 5.

In this way, the input signal is sampled and held, and the moving average is performed by the delay unit and the adder.

Equation 1 shows the transfer function obtained by the moving average.

[0016]

[Equation 1]

The frequency characteristic according to Equation 1 is given by Equation 2 with z = exp (jωT).

[0018]

[Equation 2]

Here, T is the sampling period, and ω is the angular frequency of the signal. The frequency characteristic expressed by Equation 2 is a linear delay with a group delay of 0.5T, and the amplitude characteristic is sin (ωT) / sin (0.5
ωT). The frequency characteristic of the gain obtained from Equation 2 is Equation 3
Shown in.

[0020]

[Equation 3]

The frequency characteristic of equation 3 is as shown in FIG.
It can be seen that the gain becomes zero when is half the sampling frequency, that is, the Nyquist frequency. That is, the sampling system of the above embodiment does not have a band up to the Nyquist frequency, and the 3-dB band according to Equation 3 is limited to a frequency that is a quarter of the sampling frequency. However, in applications such as video signal processing, the double-oversampling method is generally used as a measure to soften the cutoff characteristics of the pre-filter before sampling, so the effective bandwidth of the sampling system is 1/4 of the sampling frequency is sufficient. For the moment, bandwidth limitation by moving average is not a problem.

Table 1 shows a situation in which distortion and pattern noise due to variations between signal paths are alleviated by the moving average according to the method of the present invention as compared with the conventional example shown in FIG.
It is shown based on al-to- (Noise + Distortion) -Ratio.

[0023]

[Table 1]

FIG. 5 illustrates the relationship of S (N + D) R by the aperture error (δt) in Table 1.
According to the method of the present invention, S (N + D) R is 110 dB in the input frequency band of 10 ⁶ Hz.
It is 30 dB larger than the conventional configuration of 80 dB shown in FIG.

Further, S (N +) due to the gain error (δGo)
D) R also has the same relationship as shown in FIG.
A value larger by 30 dB is obtained in the band of the input frequency of 10 ⁶ Hz.

The following can be said from the results of Table 1 and FIGS. 5 and 6. When a 10-MHz band and 10-bit accuracy are required, in the conventional example shown in FIG. 11, an aperture error and a gain variation are 20-ps and 0.1%, respectively, and an offset error when a 2.0-V amplitude is taken. Is required to be suppressed to 1.4 mV, whereas when performing the moving average by the method of the present invention, the aperture error and the gain variation are set to 80-ps, respectively.
It is possible to reduce to 0.4% and completely eliminate the pattern noise generated from the offset error.

Although the operation in the above-described embodiment is only a sample and hold function, a special processing function may be added to the input signal. FIG. 7 shows a second embodiment in which a processing function is added to the embodiment shown in FIG. 8 in the figure
Reference numerals a to 8b are signal processors such as AD converters and filters, and H1 (Z) to H2 (Z) indicate their characteristics by Z functions. In this way, by providing the H1 (Z) to H2 (Z) with the AD conversion function or the filter, it is possible to realize the AD converter or the filter which exceeds the operation speed possible in the single path. The clocks φ1 and φ2 have the same waveform as that shown in FIG.

Next, the operation of the second embodiment constructed as described above will be explained. The analog signal input from the analog signal terminal 4 is sampled and held constant by the interleave operation by the sample and hold circuits 1a and 1b and the clocks .phi.1 and .phi.2. The output signal of the sample hold 1a output by the clock φ1 is processed by the signal processor 8a having the function of H1 (Z) during the period of the clock φ2. Similarly, the output signal of the sample hold 1b output by the clock φ2 is processed by the signal processor 8b having the function of H2 (Z) during the period of the clock φ1. The adder 3a adds the output signals of the signal processor 8b and the signal delay unit 2a output by the clock φ1.
Similarly, the adder 2b adds the output signals of the signal processor 8a and the signal delay unit 2b output by the clock φ2. The selector 5 selects the output signals of the adders 3a and 3b and sends them to the output terminal 6.

According to the second embodiment described above, H1 (Z) to H2
It is possible to add the processing function of (Z) to the sampling system of each signal path. In this case, the sampling output is a moving average of variations between both signal paths including the signal processing units 8a and 8b as well as the sample and hold circuits 1a and 1b, and high accuracy can be obtained. Moreover,
The function of high-speed sampling by the interleave operation is maintained as it is.

Further, a configuration as shown in FIG. 8 in which a signal processing function is added to the embodiment shown in FIG. 1 is also possible. In the figure, 10 is a newly added signal processor, and H (Z) shows its characteristic. The signal output from the selector 5 is processed by the signal processor 10. Unlike the second embodiment shown in FIG. 7, in the example of FIG. 8, since the signal processing path is single, the operation speed required for the signal processor 10 must be equal to the speed of the entire sampling system. . However, the variation in characteristics between H1 (Z) and H2 (Z), which occurs in the example of FIG. 7, does not pose a problem.

Each of the above-described embodiments has an interface.
This is a case where multiple signal paths used for the leave operation, in other words, the number of stages of the sample and hold circuit is L = 2. However, the present invention should not be limited to double paths.
FIG. 9 shows a fourth embodiment of the present invention in which the number of stages of the sample-hold circuit is L = 3.
In this example, signal delay devices (2a to 2) are provided on the same signal path.
f) is two, and the number of inputs in each adder (3a to 3c) is three. FIG. 10 shows the clock φ shown in FIG.
It is a figure which shows 1- (phi) 3. In the fourth embodiment configured as described above, the sample and hold circuits (1a to 1c) sequentially sample the clocks .phi.1 to .phi.3, and the sampling results are signal delay units (2a to 2f) on other paths.
A moving average value is obtained at the output terminal 6 by adding the respective outputs together with the adders (3a to 3c).

Similarly, in the sample-hold circuit having multiple paths of L = n, n-1 signal delay devices are inserted in each signal path. The number of inputs in the adder connected to the end of each signal path is n, including the inputs from all the other remaining signal paths.

The outputs of the sample and hold circuit and the signal delay unit may be weighted and added. For example, the output characteristics of the sample and hold circuit are input to the adder by multiplying the output of the first and first signal delay units by 0.8 and the weighted coefficient. It can be improved. Further, when the number of stages L = n is large, a delay device with a small weight may be omitted, that is, the number of signal delay devices may be slightly smaller than n−1 to simplify the configuration.

Each of the sampling systems of these embodiments is characterized in that the shortcomings of the interleave method are compensated and that the sampling operation can be speeded up or the power consumption can be reduced without increasing the circuit size so much. .
The sampling system of the present invention having such characteristics is a sample-hold circuit having a sampling function,
It can be widely used for AD converters, switched capacitor filters, etc., and can reduce power consumption particularly in applications requiring high accuracy in high bandwidth and high speed sampling.

[0035]

According to the present invention, a plurality of sample holders are provided.
The moving circuit averages the results sampled by interleaved operation in a loop circuit to mitigate the coincidence of the overall gain and aperture time among multiple paths, so the circuit scale is not so complicated. This has the remarkable effect that the conversion speed can be increased without changing the speed.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a sampling system that is a first embodiment of the present invention.

FIG. 2 is a diagram showing a clock waveform used in the embodiment.

FIG. 3 is a diagram illustrating a moving average in the first embodiment.

FIG. 4 is a diagram showing frequency characteristics of the first embodiment.

FIG. 5 is a diagram showing an effect of the first embodiment.

FIG. 6 is a diagram showing the effect of the first embodiment.

FIG. 7 is a diagram showing the configuration of a sampling system according to a second embodiment of the present invention.

FIG. 8 is a diagram showing the configuration of a sampling system according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a sampling system using a three-stage signal path in the first embodiment shown in FIG. 1 according to the fourth embodiment of the present invention.

FIG. 10 is a clock waveform diagram used in the fourth embodiment.

FIG. 11 is a diagram showing a configuration of a sampling system using a conventional interleave method.

FIG. 12 is a diagram showing an error caused by variation in gain in the example of FIG. 11.

FIG. 13 is a diagram showing an error caused by variation in aperture in the example of FIG. 11.

FIG. 14 is a diagram showing an error caused by variation in offset in the example of FIG.

FIG. 15 is a diagram showing the configuration of an interleaved sampling system using a conventional two-stage sampling system.

[Explanation of symbols]

1a, 1b ... Sample and hold circuit, 2a, 2b ... Signal delay device, 3a, 3b ... Adder, 4 ... Analog signal input terminal, 5 ... Selector, 6 ... Output signal terminal

Claims (13)

[Claims] 1. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, wherein the input signal is sequentially sampled through a plurality of signal paths, and a sampling output of each signal path is subjected to a moving average. The sampling method is characterized in that 2. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, wherein the input signal is sequentially sampled through a plurality of signal paths, and a sampling output of each signal path is subjected to signal processing. Then, the sampling method is characterized in that the result of the signal processing is output as a moving average. 3. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, wherein the input signal is sequentially sampled through a plurality of signal paths, and a sampling output of each of the signal paths is subjected to a moving average. Then, a signal processing is performed on the result of the moving average and the result is output. 4. The sampling method of the sequential method,
4. The sampling instant by each of the signal paths is sequentially delayed by a constant period, and after the sampling of all the signal paths is completed, the sampling signal is returned to the original signal path and the sampling is repeated again. The sampling method described in. 5. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, and a plurality of signal paths each including a sample and hold circuit and sampling the input signal in a sequential manner, and each of the signal paths. And a means for outputting a moving average of the sampling output of the above, and a sampling system. 6. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, and a plurality of signal paths each including a sample and hold circuit for sampling the input signal in a sequential manner, and each of the signal paths. 2. A sampling system comprising: means for signal-processing the sampling output; and means for moving average the results of the signal processing and outputting the result. 7. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, a plurality of signal paths each including a sample and hold circuit, and sampling the input signal in a sequential manner; A sampling system comprising: a means for moving average of the sampling output and outputting the moving average output; and a means for processing the moving average output and outputting the signal. 8. A signal existing in the plurality of signal paths is used as the means for outputting the moving average.
The sampling system according to any one of claims 5 to 7, further comprising: a signal delay device that delays the delay circuit by the number of stages, and an adder that adds the sampling output and each delay output. . 9. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, a plurality of sampling hold circuits each sampling the input signal by an iterative operation using clocks φ1 to φn. Of the signal paths and the sampling results are sequentially delayed by the number of stages of the plurality of sample-and-hold circuits, and each of the signal paths is operated according to the number of stages and operates with the clocks φ1 to φn. A sampling system comprising: a signal delayer; and a plurality of adders that add the sampling result and the output of the signal delayer in which the operation clocks φ1 to φn match each other. 10. The sample on each of the signal paths and
10. The sampling system according to claim 9, further comprising a signal processor provided between a hold circuit and the adder. 11. The AD converter according to claim 10, wherein the signal processor is an AD converter. 12. The filter according to claim 10, wherein the signal processor is a filter. 13. A sampling system for extracting and sampling an instantaneous value of an input signal which changes every moment, and a plurality of signal paths each including a sample and hold circuit for sampling the input signal by an iterative operation, and the sampling A signal delayer provided in each of the signal paths according to the number of stages in order to sequentially delay the sampling result to the number of stages of the plurality of sample and hold circuits; the sampling result and the signal delayer. A sampling system comprising: a plurality of adders for weighting and adding outputs.