JPH04167794A - Image pickup device - Google Patents

Abstract

PURPOSE:To made the entire signal processing system including an encoder into digital by performing the quadrature balance modulation of a color difference signal to be outputted while phase correction. CONSTITUTION:In a data latch clock, color difference signals R-Y and B-Y supplied from a signal processing circuit 3 are latched by the data latch clock supplied from a control circuit 7, and the color difference signals R-Y and B-Y after latch are supplied to a phase correction circuit 5. In the phase correction circuit 5, the phase correction of the color difference signal is performed, and the color difference signals R-Y and B-Y after phase correction are supplied to an encoder 6. In the encoder 6, the balance modulation of the supplied color difference signals R-Y and B-Y is performed by 4fsc clock and fsc clock supplied from a synchronizing signal generation circuit 9. Thus, the digital of the entire signal processing including the encoder 6 can be executed without deteriorating picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device, and more particularly, to an imaging device equipped with an optimal digital signal processing circuit.

[Conventional technology]

In recent years, the popularity of home video cameras has been rapidly increasing. The reasons for this rapid increase in penetration rate are: 1) small size;
2) lower cost, 3) improved performance such as higher image quality,
4) VTR (Video Tape Record)
The usability will be improved by developing a movie that integrates the camera section and the camera section. In addition, to realize these, 1
) solid-state imaging devices, and 2) rationalization of signal processing.

Solid-state image sensors have many features such as small size, light weight, and high reliability. At the beginning of their development, solid-state imaging devices were inferior to image pickup tubes in terms of manufacturing cost, sensitivity, resolution, etc., but with rapid advances in semiconductor technology, they have now surpassed image pickup tubes in terms of cost I and performance. Currently, almost all home video cameras use solid-state image sensors. The details of these events can be found in the Journal of the Television Society Vol. 1.41. No11
(1987) pp. 983-990.

On the other hand, in signal processing circuits, with the aim of making them smaller, lower cost, and higher performance, improvements in signal processing and the use of highly integrated ICs have been made. As a result, together with the adoption of the above-mentioned solid-state image sensor, home video cameras have achieved higher image quality, significantly smaller size and weight, and lower cost. However, when considering further rationalization of signal processing, the current signal processing method based on analog signal processing has its limitations, and in the future it seems likely that a signal processing method based on digital signal processing technology with the following features will be the best choice. .

1) It is possible to integrate a filter, which is a large component, into an IC with high viscosity.

2) Built-in A/D and D/A enable up to 1,000 chips.

3) It is easy to increase the S/N of the signal processing circuit by fully considering S/N deterioration due to calculation rounding errors.

An example of digital signal processing for such a video camera is discussed in Japanese Patent Publication No. 63-45153.

[Problem to be solved by the invention]

There are still many problems to be solved in the digitalization of signal processing for video cameras using the above-mentioned CCD sensors. One of these is the digitization of color signal encoders.

゛　4　.

Currently used CCDs have several different horizontal pixel counts. Since the horizontal scanning period is constant, as a result, the frequency of the horizontal pixel readout clock (hereinafter simply referred to as sensor clock) differs depending on the number of pixels. For example, for the NTSC system, the sensor clock frequency (hereinafter referred to as fs) is 9.5M, 12.7MH7,...
It is 14.3M7. In signal processing for digital cameras, generally, as in the aforementioned Japanese Patent Publication No. 63-45153,
Processing in synchronization with this sensor clock is simple and reduces the circuit scale, so it has great advantages. However, speaking only about the encoder, fsc's n(
Generally, it is necessary to process with n: 3 or 4) times as many clocks. Therefore, when digitizing all camera signal processing, if the relationship fs = n fsc (n = 3.4.6.8 etc.) is not satisfied, data is transferred to the encoder as follows: ( nfs)' jitter occurs. Now, if n=4, this jitter is: NTSC: (4,fsc)' = 70nsPA
L: (4fsc)” = 56ns.

When the allowable amount of jitter of the color signal is allowed, it is about 35 ns or less, and the above jitter is tolerable.It was found that in order to suppress the jitter within the allowable value, it is necessary to set rl to 8 or more. However, in reality, 8fsc (N T S
C: 2g, 6M)k, PAL: 35.44
Oscillating with MI(z) and processing data with 8 fsc clocks results in the following: 1) The oscillation tends to become unstable, and the specifications for the oscillator become stricter. Moreover, the consumption type of the oscillator also doubles.

2) The speed of the gate used in the encoder circuit is required to be twice that of the conventional one, and the specifications required for the element are also stricter, which also increases the power consumption of the encoder circuit.

There are problems such as these, and in reality, it is preferable to process with a clock of 4 fsc or less.

The digitization of this encoder is not mentioned in the known example: Japanese Patent Publication No. 63-45153.

The purpose of this patent is to provide a video camera in which all signal processing including the encoder is digitalized, and 4. as a data processing clock in the encoder. The object of the present invention is to realize a digital video camera that uses an fsc clock to reduce the jitter that occurs during parentheses to 35 ns or less, which is within the permissible value, and is optimal for low power consumption and miniaturization.

[Means to solve the problem]

In order to achieve the above object, A/D conversion means converts an output signal of a CCD sensor into a digital signal in synchronization with a sensor clock, and a sensor clock is used to convert the digitized sensor output output from the A/D conversion means into a digital signal. a signal processing means that processes the color difference signal based on the signal and generates a luminance signal and a color difference signal;
an encoder that performs balanced modulation based on the luminance signal (referred to as a clock), and a luminance signal generated by the encoder and the luminance signal
.

In a digital video camera, the digital video camera is equipped with a D/A conversion means that converts two digital signals of the modulated color signal into analog signals, respectively. m
a data clock conversion means for converting and outputting a data clock by launching a (m=l, 2, 3, 4-) cycle color difference signal with a latch pulse generated based on a 4fsc clock from a control circuit to be described later; In the above signal processing means, a phase reference signal (for example,
), which is the last stage latch pulse of the color difference signal, 4
The above latch pulse is generated and the relative phase between the above phase reference signal and the 4fsC clock is set to 4fs.
A control circuit that detects the rising and falling edges of the C clock and controls a phase correction circuit (described later) using this detection signal, and a color signal supplied from the data clock converting means.
8.

The apparatus further includes phase correction means for performing phase correction on the difference signal based on the phase detection signal supplied from the control circuit and further supplying the corrected color difference signal to the encoding means.

[Effect]

The control circuit latches the supplied phase reference (fj) at the rising edge and falling edge of 4fsc, and the change point of the color difference signal is 4f from the phase reference signal after these two latches.
It is determined whether it is in the period ``■]'' or the period ``L'' of sc, and this detection signal is supplied to the phase correction circuit. Now, if the ``I-I'' period and the ``L'' period of the 4 fsc clocks are made approximately equal, the above processing can determine the change point of the color difference signal in steps of 1/2 of (4 fsc)-1. Here, since (4fsc)'/2 = (8fsc)', the change point can be known with an accuracy of (8fsc)'.In addition, in this control circuit, as described above, the phase reference The signal is processed by the 4fsC clock to generate a launch pulse, and this latch pulse is supplied to the data clock conversion means.Here, the latch pulse is determined by the phase relationship between the phase reference signal and the 4fsc clock. Up to (4
fsc)-' jitter.

The data clock conversion means latches the color difference signals (R-Y) and (B-y) supplied from the signal processing means using the launch pulse supplied from the control circuit.

As a result, the latched color difference signals (RY), (B-Y
) can be processed using 4 fsc clock system signals. However, as described above, since the latch pulse at this time has a jitter of (4fsc)' at the maximum, the color difference signal after the latch naturally also has a jitter of (4fsc)-1 at the maximum. This latched color difference signal is further supplied to phase correction means.

The phase correction means first latches the color difference signal with the maximum (4 fsc) jitter supplied from the data clock using the latch pulse, and combines the latched color difference signal with the pre-latched signal supplied from the data clock. Then, according to the phase detection signal supplied from the control means, at the change point of the color difference signal, the signal is added to the ')-1' side of the 4fsc clock or l L
Of the I side, only when the color difference signal is on the phase side where the delay time due to the latch of the data clock conversion means is shortened, the color difference signal of the intermediate phase is selectively output for one clock of (4fsc)', In other parts, the color difference signal supplied from the data clock is output.

As a result, when the maximum jitter occurs, (4fsc)
A signal that advances by -1 can be effectively delayed by 1/(4fsc)', and the maximum jitter can be reduced to (4fsc).
' / 2 = (8fsc) -1. As described above, this is the permissible jitter of the color difference signal.

FIG. 2 shows an example to make it easier to understand how jitter is reduced by the above processing. In Figure 2, the sensor clock is fs: (4fsc) x (2/3) "1].

This shows a state in which the data cycle of the color difference signal is fs/2, the edges of the phase reference signal and the 4fsc clock match, and the jitter is at its maximum. In Figure 2, the waveform is the sensor clock, waveform B is the phase reference signal, 14 is the color difference signal (R-Y) and (B
-Y), waveform 15 is 4.4 when the rising phase of the fsc clock is slightly ahead of the rising phase of the phase reference signal (referred to as phase 4). The waveform 16 is the 4fsc clock when the rise of the 4fsc clock is slightly delayed from the phase reference signal (referred to as phase B), and the waveform 17 is the data latch clock when the phase is A. 18 is a data latch clock at phase B, waveform 19 is a waveform representing a color difference signal after latching at phase A, waveform 20 is a waveform representing a color difference signal after launch at phase B, and waveform 21 is a phase This is a waveform representing a color difference signal obtained by performing phase correction at the time of B.

Here, the data latch clock has a phase reference signal of 4f
It was decided to generate the signal by latching it twice at the rising edge of the sc clock. The reason why it is generated by latching twice is to prevent malfunctions due to the fact that, generally speaking, when the phases of the latch data and the latch clock completely match, the latch data sometimes becomes unstable.

However, whether or not jitter occurs in the latch is determined by the first latch.

As mentioned above, phase determination is performed when the phase reference signal 13 is 4f
is in the 1H' period of the sc clock (a in the figure), or
This is done depending on whether the phase reference signal 13 is in the l L
At phase B in the l L 1 period of fsc, the data after latching advances by approximately (4 fsc). Therefore, the control means detects the B phase and sends this detection signal to the phase correction means. In accordance with this detection signal, the phase correction means performs the above-mentioned phase correction only in the case of the B phase, and outputs the color difference signal after the phase correction shown in the waveform 21, and in the case of the A phase, The supplied color difference signal is shown in waveform 19. As is clear from comparing waveform 19 and waveform 20, the center point of the Nth data (indicated by 4 CA and CB' in the figure, respectively) is corrected by the above processing. The phase difference is approximately (8fscs), which is half the jitter (indicated by CA and C□ in the figure) when the jitter is not used. In other words, the maximum jitter (4fsc) is (8fsc) -
' has been reduced to.

As described above, according to the above means, the color difference signal supplied to the encoder can be processed with 4 fsc clocks, the jitter is within the maximum allowable value of (8 fsc)-'', and the color difference signal supplied to the encoder can be processed with any number of pixels. Digitalization of signal processing including the encoder can be realized for the sensor without deteriorating the image quality.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 1st
In the figure, 1 is a solid-state image sensor, 2 is an A/D converter, and 3
4 is a data clock conversion circuit; 5 is a phase correction circuit; 6 is an encoder; 7 is a control circuit; 8 is a drive circuit; 9 is a synchronization signal generation circuit; 10 and 11 is a D/A converter. The operation of this embodiment will be described below.

First, the synchronization signal generation circuit 9 generates synchronization signals (horizontal and vertical synchronization, subcarriers, clocks, etc.) necessary for the signal processing circuit 3, drive circuit 8, and other circuits. In FIG. 1, pulses and the like necessary for processing by the signal processing circuit 3, encoder 6, etc. are omitted because they are not directly necessary for this explanation.

The drive circuit 8 is synchronized with horizontal synchronization and vertical synchronization supplied from the synchronization signal generation circuit 9, and reads out signals from the solid-state image sensor 1 at sensor clock cycles (fs). The sensor output read from the solid-state image sensor 1 is supplied to an A/D converter 2. The A/D converter 2 synchronizes the sensor output signal with the sensor clock, converts it into a digital signal for each pixel, and supplies it to the signal processing circuit 3.

In the signal processing circuit, for example, the above-mentioned known example: Japanese Patent Publication No. 6
3-45153, the digital sensor output signal after A/D conversion supplied from the A/D conversion is processed based on the sensor clock to generate a luminance signal and a color difference signal, and output. ]5 ・ Force. The color difference signals (RY) and (
B-Y) is supplied to the data clock conversion circuit 4. The control circuit 7 receives, from the signal processing circuit 3, a phase reference signal (1
As mentioned above, for example, the latch clock of the color difference signal)
The phase of the data latch clock, the phase reference signal, and the 4 fsc clock supplied from the synchronization signal generation circuit is expressed as (
8fsc)' and supplies the data latch clock to the data clock conversion circuit 4 and the phase correction circuit 5, and also supplies the phase detection signal to the phase correction circuit 5. The data latch clock latches the color difference signals (R-Y) and (B-Y) supplied from the signal processing circuit with the data latch clock supplied from the control circuit 7. ) and (B-Y) are supplied to the phase correction circuit 5. The phase correction circuit 5 performs phase correction on the color difference signal in the same manner as the above-mentioned phase correction means, and sends the phase corrected color difference signals (R-Y) and (B-Y) to the encoder 6.
supply to. Above data clock conversion circuit 4, 16
- The control circuit 7 and the phase correction circuit 5 correspond to the data clock conversion means, control means, and phase correction means, respectively, and perform completely similar processing. As a result, in this example as well, the jitter associated with the data clock conversion of the color difference signals (R-Y) and (B-Y) supplied to the encoder is reduced, as described above for the use of a sensor with an arbitrary number of pixels. (8f
sc) 'can be kept below. The encoder 6 converts the supplied color difference signals (R-Y) and (B-, Y) into 4 fsc clocks and fsc clocks supplied from the synchronization signal generation circuit.
Balanced modulation processing is performed using the sc clock. The modulated color signal obtained through the above processing and the luminance signal generated by the signal processing circuit 3 are supplied to D/A conversion circuits 11 and 10, respectively. The D/A conversion circuits 10 and 11 convert the supplied luminance signal and modulated color signal into analog signals and output the analog signals. However, if these luminance signals and modulated color signals are to be processed later in the digital signal state, D/
A converters 10 and 11 are not required.

As described above, in this example, signal processing including the encoder can be integrated, and furthermore, when using a sensor with an arbitrary number of pixels, the jitter generated by the encoder can be suppressed to (8fsc)', and the image quality change due to thick can be prevented.

FIG. 3 shows an example of the configuration of the data clock conversion circuit 4, phase correction circuit, and control circuit. Figure 4 shows
This figure shows the waveforms of each part in FIG. 3, and as in the case explained in the above operation, the sensor clock is fs": (4fsc) x (2/3),
Furthermore, it is assumed that the edges of the phase reference signal and the 41sc clock match and the rigidity is at its maximum. Also, the data cycle of the color difference signals (R-Y) and (B-Y) is 1/2 of the sensor clock 2 fS, as in the above example.
shall be. In FIG. 3, the data clock conversion circuit 4 is provided with latch circuits 22 and 23, and a phase correction circuit 5.
are latch circuits 30 and 31. Addition circuits 32 and 33. Coefficient circuits 34 and 35. Multiplexers 36 and 37.
DFF (D flip-flop) 38. N○ Engineering Goo 1
~39. The control circuit 7 is further connected to the DFFs 24, 25, 26, 27, and 28 by the AND games 1 to 40.
They are each made up of 29 evenings. Further, in FIG. 4, waveform 13 is a phase reference signal, waveform 14 is a waveform representing a data string in which the]th (RY) and (B-Y) are combined and expressed as Di, and waveform 15 is a phase reference signal. Reference signal 13
Waveform 16 is a 4 fsc clock whose rise is slightly ahead of the rising edge of the phase reference signal (referred to as the B phase, as in Figure 2). be. These waveforms are
They are the same as those explained in FIG. 2, and are given the same numbers as in FIG. 2, respectively. The other waveforms in FIG. 4 that are the same as those in FIG. 2 are numbered the same.

Hereinafter, other waveforms will be sequentially explained while explaining their operations.

First, the phase reference signal and the 4fsc clock are transmitted to the control circuit 7.
supply to. In the control circuit 7, the supplied phase reference signal (waveform 13 in FIG. 4) is converted to 4 f by DFF2/l and 25.
Twice at the rising edge of the sc clock, and again DFF26゛19
I had lunch twice on the downhill by ゛ and 27. As a result, D
The Q outputs of FF25 and DFF26 each have waveform 1.
7 (toward phase), waveform 18 (toward phase), waveform 50 (toward phase), and waveform 51 (toward phase) are obtained. This DFF25
The Q output of is supplied to the data clock conversion circuit 4 and the phase correction circuit 5 as a data launch clock. On the other hand, D
The Q output of FF26 is further launched in DFF28 by the Q output of DFF25. A waveform 52 is outputted to the Q output of the DFF 28 in the F phase, and a waveform 53 is outputted in the B phase. Therefore, the Q output of DFF28 is /L
+ or 1H', the rising edge of the phase reference signal is in the 'H' period (a in the figure) of the 4fsc clock.
It is possible to detect whether it is in the r L + period. This is the phase detection described above.

The Q output of the DFF 28 is supplied to the phase correction circuit 5 as a phase detection signal.

In the data clock conversion circuit, the color difference signals (RY) and (I3-Y) shown by the waveform 14 are respectively converted to the latch circuit 2 by the data latch clock supplied from the control circuit 7.
2 and a latch circuit 23. The latch circuit 22 and the latch circuit 23 are configured, for example, by D corresponding to one pitch of the color difference signals (RY) and (B-Y). A waveform 19 (phase B) or a waveform (phase B) is outputted from the latch circuits 22 and 23. This output signal is supplied to the phase correction circuit 5.

In the phase correction circuit, the color difference signals (R-Y) and (B-Y) supplied from the data clock conversion circuit 4 are latched by the latch circuits 30 and 31 using the data latch clock supplied from the control circuit 7. do. The color difference signals (R-Y) and (B-Y) after the launch are combined in adder circuits 32 and 33 with the color difference signals (R-Y) and (B-Y) supplied from the data clock conversion circuit before the latch. and further, the signal coefficient circuits 34 and 3 obtained by this addition.
5 is multiplied by 1/2 to generate a color difference signal (D, +DL+□)/2 at an intermediate phase between D and D (+I), and supplies it to multiplexers 36 and 37. Multiplexer 3
6 and 37, the supplied color difference signal at the intermediate phase and the color difference signal supplied from the data clock conversion circuit are converted into A,
Output according to the output signals of ND 1 to 40.

Here, it is assumed that when the output of the gate 40 is 'I-I', a color difference signal with an intermediate phase is output. On the other hand, DFF3
8 and NOR gate 1 39 constitute a rising edge detection circuit, and the supplied data launch clock is L.
Immediately after switching from L I to 'I-(', 4fs
The AND gate generates an edge signal that becomes 'II' for one cycle of the C clock.The AND gate supplies this edge signal to the multiplexers 36 and 37 during the B phase according to the phase detection signal supplied from the control circuit 7. and is masked when the phase is A. The output signal waveforms of the AND gates 1 to 4 become the waveform 54 (phase B) and the waveform 55 (phase B) in FIG. 4. As a result, the multiplexers 36 and 37 A color difference signal of an intermediate phase is selectively outputted only at the edge portion of the B phase, and a color difference signal shown in waveform 19 is outputted in the A phase, and a color difference signal shown in waveform 2 is outputted in the B phase.These color difference signals are as described above. This is the color difference signal after jitter suppression.

FIG. 5 shows an example of the configuration of the digital encoder 6 in the NTSC system. In Figure 5, 58.
59 is a latch circuit, 62 and 63 are polarity inversion circuits, and Go/
61 is a DFF, and 64 is an adder circuit. The operation will be explained below with reference to FIG. First, the color subcarrier fsc supplied from the synchronization signal generation circuit 9 of FIG. Waveform 67 is the signal obtained as a result. Further, this signal is launched in DFF 61 to obtain a signal shown in waveform 68. Waveform 17 and waveform 1 thus obtained
The signals shown at 8 are color subcarrier signals having a phase difference of 90°, and are supplied to polarity inversion circuits 62 and 63, respectively.

The polarity inversion circuits 62 and 63 receive color difference signals (shown in waveform 69 and waveform 71) obtained by latching the color difference signal with a 4 fsc clock after the jitter has been suppressed by the above-mentioned phase correction circuit, and are supplied from the DFF 60 and DFF 61. When the signal is l L +, the polarity is inverted and waveform 70 and waveform 71
Outputs the signal shown in The signals shown in waveform 70 and waveform 71 are signals modulated by subcarriers with a 90° phase difference, and these 2°23° signals are added by an adder circuit 64 and quadrature balanced. Obtain a modulated color signal. The case of the NTSC system has been described above, but in the case of the PAL system as well, the line number is input to the polarity inversion circuit 62, and the subcarrier is L for each line.
By switching whether polarity inversion is performed at Hl or L L + , quadrature balanced modulation can be achieved with a similar configuration.

FIG. 7 shows another embodiment of the invention. Parts that operate in the same way as in the embodiment described above are given the same reference numerals. In this embodiment, 8 fsc clocks and 4 fsc clocks are further used.
Using a clock, change points of color difference signals (16fsc)
Detected with an accuracy of ' and performs phase correction. As a result, the jitter also becomes less than (16fsc)-1.

Although the maximum frequency waveform of the clock is doubled and the power consumption of the oscillator increases, data processing is performed at a maximum of 4 fsc, so the power consumption in data processing is the same as in the embodiment described above. This embodiment is basically different from the above-described embodiment only in the phase correction section, so this phase correction will be explained using FIG. 8.

'2-4-' 1 pan, 4. First, in the control circuit, 4. One cycle of the fsc clock is divided into four equal parts to detect the range in which the changing point of the color difference signal (the rising phase of the phase reference signal) changes. In FIG. 8, each phase range divided into four equal parts is a 1 b I C,
d, and the rising edge of the reference phase is a, respectively.
The cases in b, Q, and d will be referred to as A phase, B phase, C phase, and D phase.

Waveform 73 and waveform 74. Waveform 74 and waveform 75. Waveform 76 and waveform 77 and waveform 78 and waveform 79 are A phase, respectively.
4. When in B phase, C phase, and D phase. fsc clock and 8
This is the fsc clock. Also, waveform 80. Waveform 81.
Waveform 82 and waveform 83 are data latch clocks, which are take latch clocks for each phase generated by latching the phase reference signal B at the rising edge of 8 fsc and then latching it at the rising edge of 4 fsc.

These data latch clocks have a phase of (16 fsc)-' relative to the D phase, and a phase of 2 (16 fsc) for the B phase.
fsc) ', and further 3 (16fsc) in C phase
Therefore, the color difference signal latched by the data latch clock in the data clock conversion circuit 4 has the above-mentioned phase shift in each phase.

In the phase correction circuit 56, the conversion circuit 4 +, +'
D t), and output the intermediate phase data for one cycle of 4 fsc at the change point of the color difference signal at the A phase, B phase, and C phase, respectively;
Waveform 84. Waveform 85. Waveform 86. A waveform 87 is obtained. As a result, the center of each output signal is CA in the figure.

As shown in c, , c, , CD, a shift in the coordinate sum occurs.

That is, according to this embodiment, data processing is performed at 4fsc
(16fsc) -1
Jitter correction can be performed with high accuracy.

[Effects of the Invention] According to the present invention, in a video camera using a sensor with an arbitrary number of pixels, jitter that theoretically occurs in a digital encoder based on a 4 fsc clock can be reduced to (8 fsc
)", and the entire signal processing system including the encoder can be digitized without degrading the image quality, realizing a low consumption, compact, lightweight, high-quality video camera that takes advantage of the Merino 1- of digitalization. can.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing waveforms of each part of Fig. 1, and Fig. 3 is a data clock conversion circuit, phase correction circuit, and control circuit of Fig. 1. 4 is a waveform diagram showing the waveforms of each part in Fig. 3. Fig. 5 is a block diagram showing an example of the structure of the encoder. Figure 6 is a waveform diagram showing the waveforms of each part in total. 7 is a block diagram showing another embodiment of the present invention, and FIG. 8 is a waveform diagram showing a portion of waveforms in FIG. 7. 1 Solid-state image sensor, 2... A/D converter, 3... Signal processing circuit, 4... Data clock conversion circuit, 5... Phase correction circuit, 6... Encoder, 7... Control circuit, 8...
Drive circuit, 9 Synchronization signal generation circuit, 10, 11...D
/A conversion circuit.

Claims (1)

[Claims] 1. The output signal of the solid-state image sensor is converted into a digital signal in the signal readout cycle (fs), and the converted digital signal is digitally processed in the fs clock to generate a luminance signal and a color difference signal. In a video camera that generates a color difference signal generated based on the fs clock, the 4fs signal, which is four times the frequency of the color subcarrier (fsc), is input.
a data clock converting means (4) that performs clock conversion of data by latching with a data latch clock synchronized with the c clock; detecting and outputting the phase of a change point of the color difference signal generated based on the fs clock; At the same time, at the stable point after the change point of the color difference signal generated based on the fs clock,
control means (7) for generating the data latch clock that is latched in synchronization with the fsc clock; a phase correction means for outputting a phase-corrected color difference signal by selecting and outputting the intermediate phase color difference signal and the converted signal of the input data clock according to the phase detection signal output from the control circuit; 5); and modulation means (6) for orthogonally balanced modulating the color difference signals (for example, RY and BY) output from the phase correction means. 2. The control circuit is equipped with a detection means for detecting the change point of the color difference signal in steps of (4fsc)^-^1 based on the rising and falling edges of the 4fsc clock, and the phase correction according to claim 1 above. The circuit selects and outputs the average value of the signals before and after the change point of the color difference signal and the input signal according to the phase detection signal supplied from the detection means in 1 increments (4fsc), thereby obtaining a signal after phase correction. The imaging device according to claim 1, wherein the imaging device is configured to output. 3. The control circuit uses a 4fsc clock and an 8fsc clock, and the change point of the color difference signal is at 1 of the 4fsc clock.
The phase correction circuit according to claim 1, which is equipped with a detection means for detecting where the phase is located in four phase ranges obtained by equally dividing a cycle into four, generate a signal at an intermediate phase between the four
According to the phase detection signal supplied from the detection means for detecting two phases, the four signals of the three intermediate phase signals and the input signal are selectively outputted to output a phase correction signal. The imaging device according to claim 1.