JP3355975B2 - Color signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing circuit of a single-chip color camera used for an image pickup section of a video movie or the like.

[0002]

2. Description of the Related Art In a single-chip color camera, a complementary color filter is provided in front of a black-and-white image sensor in order to obtain a color signal from one solid-state image sensor. A color signal processing circuit is required to generate a color signal from an image signal on which components are superimposed. A conventional color signal processing circuit is described in, for example, "Digital Signal Processing of Single-Chip Video Camera", Technical Report of the Television Society of Japan, Vol.
15, No. 7 and "Design of VTR with Microminiature Camera", published by Trickeps Co., Ltd.
95, p. 96.

Hereinafter, a conventional color signal processing circuit will be described. FIG. 6 shows a block diagram of a conventional color signal processing circuit. In FIG. 6, reference numeral 1 denotes a complementary color filter.
Reference numeral 2 denotes a solid-state image sensor, which has a complementary color filter 1 and mixes two pixels in the vertical direction for each horizontal scan to generate a chrominance signal (2R
-G, 2B-G components) are output.
As a color signal, 2R-G components are (n +
1) The 2BG component is output from the line. 3 is A / D
The converter inputs the output of the solid-state imaging device 2 and converts it into digital data.

A 1H delay circuit 4 receives the output of the A / D converter 3 and outputs a signal delayed by one horizontal period. Reference numeral 5 denotes a line switching circuit, which outputs an output signal of the A / D converter 3 and 1H.
The output signal of the delay circuit is input and switched every horizontal period to simultaneously output the 2RG component and the 2BG component. 100
And 101, a white balance correction circuit which receives the output signal of the line switching circuit 5 and corrects the color difference signal to zero when white is imaged. Reference numerals 102 and 103 denote color separation circuits which input the output signals of the white balance correction circuits 100 and 101, respectively, and calculate the difference between adjacent pixels by (Ye + M).
g)-(Cy + G) = 2R-G, (Cy + Mg)-(Y
e + G) = 2B−G, and outputs a color difference signal. Here, Ye = R + G, Mg = R + B, Cy = B
+ G.

[0005] A time division circuit 104 is a color separation circuit 102,
The output signal of 103 is input, time-division-processed and output. The process of obtaining a color difference signal in the color signal processing circuit configured as described above will be described in more detail with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the line switching circuit, and FIG.
4 is an operation waveform diagram of each part in FIG. 4, FIG. 7 is a block diagram of a white balance correction circuit, a color separation circuit, and a time division circuit in a conventional color signal processing circuit, and FIG. 8 is an operation waveform diagram of a conventional color signal processing circuit. It is.

First, in the solid-state imaging device 2 having the complementary color filter 1, in the n-line, Ye + Mg / Cy + G
In the (n + 1) line, Ye + G / C
The signal of y + Mg is output. This output signal is converted into digital data by the A / D converter 3. A / D converter 3
Is input to the 1H delay circuit 4 and the line switching circuit 5 shown in FIG. The line switching circuit 5 includes n
Line signal and passed through the 1H delay circuit 4 (n +
1) The signal b of the line is switched every 1H, and 2R-G
Ye + Mg / Cy + G (hereinafter referred to as YM / C
G) is input to the 2B-G color separation system by Ye +
A signal d of G / Cy + Mg (hereinafter, described as YG / CM) is output.

The white balance correction circuit 100 receives the signal c and generates a time-division signal b1 of the correction coefficients A and B.
Is multiplied by a multiplier 106, and A (YM) and B (CG)
Outputs a signal l in dot sequence. The white balance is corrected so that A (YM) -B (CG) = 0 when capturing white. White balance correction circuit 10
1 receives the signal d, multiplies the signal b2 obtained by time-dividing the correction coefficients C and D by the multiplier 114, and outputs a signal m in which D (YG) and C (CM) are dot-sequential. . The white balance is defined as C (CM) -B (Y
G) = 0.

The color separation circuit 102 receives the signal l and inputs the signal l and the signal l to the flip-flop 107
The difference from the signal b3 delayed by one pixel is calculated as B (CG2).
-A (YM1) and A (YM3) -B (CG2) generate a signal b4 in which the dot sequence is obtained, and the generated signal b4 is used as an operation clock by the latch circuits 109 and 110 as fck. fck represents an operation clock.) fck /
2 is "H" and the data when fck / 2 is "L" are respectively held, and the subtracter 111 uses the output signal b5 of the latch circuit 109 from the A (YM3) -B (CG2) of the latch circuit 109 to hold the latch circuit. B (CG2) -A of 110 output signal b6
(YM1) is subtracted, and A (YM1) -2B (CG2) +
A color difference signal b7 represented by A (YM3) is generated, and the generated color difference signal b7 is converted by the latch circuit 112 into fck / 2 "
The data at the time of L "is held, and a color difference signal n of fck / 2 rate is output.

The color separation circuit 103 receives the signal m, and outputs the signal m and the signal m to a flip-flop 115 by a subtractor 116.
The difference from the signal b8 delayed by one pixel is calculated by C (CM2)
-D (YG1) and D (YM3) -C (CM2) generate a dot-sequential signal b9, and the generated difference signal b9 is output by the latch circuits 117 and 118 when fck / 2 is "H". The data and the data when fck / 2 is "L" are respectively held, and the subtractor 119 outputs the output signal b of the latch circuit 118.
11 from C (CM2) -D (YG1) to latch circuit 11
7 is subtracted from D (YM3) -C (CM2) of the output signal b10, and -D (YG1) + 2C (CM2) -D (YG3)
Is generated, and the data when the fck / 2 is "L" is held by the latch circuit 120 with the generated color difference signal b12, and the color difference signal o at the fck / 2 rate is generated.
Is output.

The time division circuit 104 receives the output signal n of the color separation circuit 102 and the output signal o of the color separation circuit 103,
When fck / 2 is “H”, the signal n is changed to “fck / 2”.
At the time of L ", the signal o is selected and the color difference signal p time-divided by fck is output.

[0011]

As described above, the color signal processing circuit of the conventional single-chip color camera, when obtaining a color difference signal, has independent white balance correction circuits for the 2R-G system and the 2BG system. In addition, a color separation circuit is required, and the number of multipliers and subtractors used is large, which causes a problem that the entire circuit scale becomes large.

[0012] The present invention solves this problem, and 2R
An object of the present invention is to provide a small-scale color signal processing circuit by performing time-division processing on the -G system and the 2B-G system and integrating the white balance correction circuit and the color separation circuit into one system.

[0013]

According to the present invention, there is provided a solid-state image pickup device comprising a complementary color filter, which outputs an image signal by mixing two pixels in a vertical direction for each horizontal scan. A sampling circuit that samples a signal output from the solid-state imaging device; a 1H delay circuit that receives an output signal of the sampling circuit and delays one horizontal period; and receives an output signal of the sampling circuit and an output signal of the 1H delay circuit. A line switching circuit for switching and outputting an input signal every one horizontal period; and a first output signal of the line switching circuit.
A first signal obtained by adding signals separated by one pixel and delaying by one pixel;
A first arithmetic circuit that outputs a second signal that is one pixel away from the input signal, and a second output signal of the line switching circuit that inputs a signal that is two pixels away from the input signal and a signal that is four pixels away from the input signal A second arithmetic circuit that outputs the added first signal and a second signal that is four pixels away from the input signal;
A time-division circuit that inputs the first and second signals of the arithmetic circuit and the first and second signals of the second arithmetic circuit, selects each signal at intervals of an operating frequency, and performs time-division processing; A white balance correction circuit for inputting an output signal of the time division circuit and correcting the color difference signal to be zero when capturing white, and an output signal of the white balance correction circuit for inputting the output signal of the white balance correction circuit and taking a difference between adjacent pixels to obtain a color difference. And a color separation circuit for obtaining a signal.

Thus, the white balance correction circuit and the color separation circuit can be integrated into one system without increasing the operating frequency, and a small-scale color signal processing circuit can be realized.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a solid-state image pickup device having a complementary color filter for mixing two pixels in the vertical direction for each horizontal scan and outputting an image signal; A sampling circuit for sampling a signal output from an image sensor, a 1H delay circuit for inputting an output signal of the sampling circuit and delaying it for one horizontal period, and an output signal of the sampling circuit and an output signal of the 1H delay circuit. A line switching circuit for switching and outputting an input signal every one horizontal period, a first output signal of the line switching circuit being input, and adding the input signal and a signal separated by two pixels from the input signal to delay by one pixel A first arithmetic circuit that outputs a second signal that is one pixel away from the input signal, a second output signal of the line switching circuit, and two pixels from the input signal. A first signal obtained by adding a distant signal and a signal separated by four pixels, a second arithmetic circuit that outputs a second signal that is separated by four pixels from the input signal, and first and second signals of the first arithmetic circuit 2 and the first of the second arithmetic circuit,
A time-division circuit for inputting a second signal, selecting each signal at intervals of the operating frequency and performing time-division processing, and a color-difference signal that becomes zero when an output signal of the time-division circuit is input and white is imaged. And a color separation circuit that receives an output signal of the white balance correction circuit, obtains a difference between adjacent pixels, and obtains a color difference signal, and includes a 2R-G component. Is the first arithmetic circuit and 2
The BG component is preliminarily operated by the second operation circuit,
After a total of four types of signals, the first and second signals of the first arithmetic circuit and the first and second signals of the second arithmetic circuit, are subjected to time division processing at intervals of the operating frequency, white balance correction and By adopting a configuration for performing color separation, a single system of white balance correction circuit and color separation circuit can be used without increasing the operating frequency.
This has the effect that a color signal is obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a color signal processing circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a complementary color filter. Reference numeral 2 denotes a solid-state image sensor, which has a complementary color filter 1 and outputs an image signal obtained by mixing two pixels in the vertical direction for each horizontal scan and superimposing a color signal (2RG, 2BG component) on a luminance signal. . As a color signal, a 2R-G component from the n-th line is 2B-G from the (n + 1) -th line.
The G component is output.

Reference numeral 3 denotes an A / D converter, which inputs the output of the solid-state imaging device 2 and converts it into digital data. Reference numeral 4 denotes a 1H delay circuit which receives the output of the A / D converter 3 and outputs a signal delayed by one horizontal period. 5 is a line switching circuit,
The output signal of the converter 3 and the output signal of the 1H delay circuit are input and switched every horizontal period to simultaneously output the 2R-G component of the first output signal and the 2BG component of the second output signal.
Reference numeral 6 denotes a first arithmetic circuit, which inputs a 2R-G component, adds an input signal and a signal two pixels away from the input signal and delays it by one pixel, and a second signal one pixel away from the input signal. Output a signal.

Reference numeral 7 denotes a second arithmetic circuit which inputs a 2BG component and adds a signal two pixels away from the input signal and a signal four pixels away from the input signal, and a first signal four pixels away from the input signal. 2 is output. Reference numeral 8 denotes a time-division circuit, which inputs four types of signals, that is, the first and second output signals of the first arithmetic circuit 6 and the first and second output signals of the second arithmetic circuit, and operates at intervals of the operating frequency. Each signal is selected and time-division-processed. Reference numeral 9 denotes a white balance correction circuit which receives the output signal of the time division circuit 8 and corrects the color difference signal to zero when capturing white.

A color separation circuit 10 receives the output signal of the white balance correction circuit 9 and determines the difference between adjacent pixels by (Ye
+ Mg)-(Cy + G) = 2R-G, (Cy + Mg)-
(Ye + G) = 2B−G, and outputs a dot-sequential color difference signal. Here, Ye = R + G, Mg = R +
B, Cy = B + G. The process of obtaining a color difference signal in the color signal processing circuit configured as described above will be described in more detail with reference to the drawings.

FIG. 4 is a block diagram showing a configuration of a line switching circuit, FIG. 5 is an operation waveform diagram in each part of FIG. 4, and FIG. 2 is a first and a second arithmetic circuit and a time division circuit in the embodiment of the present invention. FIG. 3 is a block diagram of a white balance correction circuit and a color separation circuit, and FIG. 3 is an operation waveform diagram in the color signal processing circuit according to the embodiment of the present invention. First, the complementary color filter 1
, The solid-state imaging device 2 having Y for n pixels has Y
In the (n + 1) line, the signal of M / CG is converted to YG for each pixel.
/ CM signal is output. This output signal is sampled by the A / D converter 3 of the sampling circuit with the operation clock fck and converted into digital data. The output signal a of the A / D converter 3 is input to the 1H delay circuit 4 and the line switching circuit 5 shown in FIG. Line switching circuit 5
Switches the signal of the nth line and the signal b of the (n + 1) th line passing through the 1H delay circuit 4 every 1H,
It outputs a first output signal c in which YM / CG of RG component is repeated and a second signal d in which YG / CM of 2BG component is repeated.

The first arithmetic circuit 6 inputs the signal c, and the adder 15 converts the signal c and the signal c into the flip-flops 13, 1.
4, a signal a1 delayed by two pixels is added, a first output signal e further delayed by one pixel by a flip-flop 16, and a signal c is delayed by one pixel by a flip-flop 13.
7, the second output signal f whose level is doubled is output.

The second arithmetic circuit 7 receives the signal d, and the adder 22 delays the signal d by two pixels by the flip-flops 18 and 19 and the signal a3 and the signal d by the flip-flop 18,
A first output signal g obtained by adding the signal a5 delayed by 4 pixels at 19, 20, and 21 and a second output signal h obtained by doubling the level of the signal a5 by the doubling circuit 23 are output. The time division circuit 8 includes a first output signal e of the first arithmetic circuit 6 and a second output signal e.
, And the first output signal g of the second arithmetic circuit 7,
The second output signal h is input, the signal f is output when fck / 2 and fck / 4 are both "L", and the signal f is output when fck / 2 is "H".
When the signal ck / 4 is "L", the signal e is output.
When fck / 4 is "H" at L ", the signal g is set to fck /
When both 2 and fck / 4 are "H", the signal h is selected,
2 (CG2), (YM1 + YM3) at fck rate,
The signal i subjected to the time-division processing in the order of (YG1 + YG3) and 2 (CM2) is output.

The white balance correction circuit 9 receives the output signal i of the time division circuit 8, and the signal i and f
When ck / 2 and fck / 4 are both "L", the correction coefficient B, when fck / 2 is "H", and when fck / 4 is "L", the correction coefficient A, and when fck / 2 is "L", fck / 4 Is "H"
, The correction coefficients D, fck / 2 and fck / 4 are both "
In the case of "H", the correction coefficient C is multiplied by the output signal a6 of the selector circuit 24 which is output in a time-division manner, and 2B (CG
2), A (YM1 + YM3), D (YG1 + YG3),
2C (CM2) outputs a dot-sequential signal j.

The color separation circuit 10 receives the output signal j of the white balance correction circuit 9, and outputs a signal a 7 obtained by delaying the signal j by the subtractor 27 and the signal j by one pixel by the flip-flop 26.
A (YM1 + YM3) −2B (CG2) = A
(YM1) -2B (CG2) + A (YM3) and 2C (C
M2) -D (YG1 + YG3) =-D (YG1) + 2C
A dot-sequential color difference signal a8 represented by (CM2) -D (YG3) is generated, and the generated color difference signal a8 is latched by the latch circuit 2.
8 holds the data when fck / 2 is "H",
A ck / 4 rate color difference signal k is output.

If the fck at this time is, for example, 12 MHz, the clock rate of the color difference signal k is 3 MHz, which is half that of the conventional circuit, but is 1.5 MHz or less, which is considered to be sufficient as a color difference signal for a single-chip color camera. A color difference signal k satisfying the band is obtained. As described above, according to the embodiment of the present invention, the 2R-G component is divided into 2 by the first arithmetic circuit.
The BG component is preliminarily operated by the second operation circuit,
After a total of four types of signals, the first and second signals of the first arithmetic circuit and the first and second signals of the second arithmetic circuit, are subjected to time division processing at intervals of the operating frequency, white balance correction and With the configuration for performing color separation, a color signal can be obtained without increasing the operating frequency by one system of white balance correction circuit and color separation circuit.

If the time division circuit 8, the white balance correction circuit 9 and the color separation circuit 10 are operated at double fck and the timing is taken into consideration, a color difference signal satisfying the same band as the conventional one can be obtained. It is also possible.

[0027]

As is apparent from the above description, according to the present invention, the 2R-G component is converted to the 2B-G component by the first arithmetic circuit.
The components are processed in advance by a second arithmetic circuit, and the first and second signals of the first arithmetic circuit and the first and second signals of the second arithmetic circuit are subjected to a total of four types of operating frequency signals. After performing time-division processing at intervals of, white balance correction and color separation are performed so that the operating frequency does not increase.
The white balance correction circuit and the color separation circuit can be integrated into one system to realize a small-scale color signal processing circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a color signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of first and second arithmetic circuits, a time division circuit, a white balance correction circuit, and a color separation circuit according to the embodiment of the present invention.

FIG. 3 is an operation waveform diagram in the color signal processing circuit according to the embodiment of the present invention;

FIG. 4 is a block diagram of a line switching circuit.

FIG. 5 is an operation waveform diagram of the same.

FIG. 6 is a block diagram of a conventional color signal processing circuit.

FIG. 7 is a block diagram of a white balance correction circuit, a color separation circuit, and a time division circuit in a conventional color signal processing circuit.

FIG. 8 is an operation waveform diagram of the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Complementary color filter 2 Solid-state image sensor 3 Sampling circuit 4 1H delay circuit 5 Line switching circuit 6 First arithmetic circuit 7 Second arithmetic circuit 8 Time division circuit 9 White balance correction circuit 10 Color separation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/04-9/11 H04N 9/64-9/78

Claims (1)

(57) [Claims] 1. A solid-state imaging device having a complementary color filter and mixing two pixels in a vertical direction for each horizontal scan to output an image signal; a sampling circuit for sampling a signal output from the solid-state imaging device; A 1H delay circuit that receives an output signal of the sampling circuit and delays it by one horizontal period, and a line switch that receives an output signal of the sampling circuit and an output signal of the 1H delay circuit and switches and outputs an input signal every horizontal period A first signal obtained by inputting a first output signal of the line switching circuit, adding an input signal and a signal separated by two pixels from the input signal and delaying by one pixel, and a second signal separated by one pixel from the input signal
A first arithmetic circuit that outputs a signal of the line switching circuit, a first signal obtained by adding a signal that is two pixels away from the input signal and a signal that is four pixels away from the input signal, and A second arithmetic circuit that outputs a second signal that is four pixels away from the signal, and outputs the first and second signals of the first arithmetic circuit and the first and second signals of the second arithmetic circuit. A time-division circuit that inputs and selects each signal at an interval of an operating frequency to perform time-division processing; and a white balance that corrects so that a color difference signal becomes zero when an output signal of the time-division circuit is input and white is imaged. A color signal processing circuit comprising: a correction circuit; and a color separation circuit that receives an output signal of the white balance correction circuit and obtains a color difference signal by taking a difference between adjacent pixels.