JP3147056B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to digital signal processing most suitable for a color video camera using a CCD sensor of a pixel-mixing two-row simultaneous scanning type.

[0002]

2. Description of the Related Art Solid-state imaging devices have many features such as small size, light weight, and high reliability. Initial development, manufacturing cost, sensitivity,
Although it was inferior to the image pickup tube in resolution and the like, rapid progress in semiconductor technology has led to cost and performance surpassing the image pickup tube. At present, solid-state imaging devices are used in almost all home video cameras. These circumstances are described in the Journal of the Institute of Television Engineers of Japan, Vol. 41, No11 (198
7) Discussed on pages 983-989.

On the other hand, large-scale integrated circuits and improvements in signal processing have been promoted in signal processing circuits for the purpose of miniaturization, low cost, and high performance. As a result, in conjunction with the adoption of the above-described solid-state imaging device, the home video camera has achieved not only high image quality but also significant reduction in size, weight, and cost. However, considering further signal processing synthesis,
There is a limit in the current signal processing method based on analog signal processing, and in the future, a signal processing method based on digital signal processing technology having the following features is considered to be a favorite.

I) Large components L (inductor), C
A filter constituted by (condenser) and R (resistance) can be constituted by a digital filter, and a high-precision filter can be integrated in an IC.

[0005] II) In digital signal processing, there is no variation, and therefore no adjustment or the like for absorbing the variation is required.

III) Automatic electronic adjustment of each adjustment is possible.

[0007] IV) By incorporating A / D and D / A, one-chip IC integration is relatively easy.

[0008] V) By designing with sufficient consideration given to S / N degradation due to rounding errors in computation, S / N degradation by the signal processing circuit does not occur.

An example of such a digital signal processing of a video camera is discussed in Japanese Patent Publication No. 63-45153.

The above-described solid-state imaging device has various configurations, and is roughly classified into a MOS type and a CCD type. Generally M
The OS type sensor has a multi-line output, while the CCD type sensor has a single line output. Considering the digitization of signal processing, a CCD sensor having a single line output requires only one A / D converter, and is therefore more advantageous than a MOS sensor which requires a large number of A / D converters. is there. Although there are various types of CCD type, at present, the Technical Report of the Institute of Television Engineers of Japan, TEBS87-3, ED691,
The pixel-mixing readout type CCD sensor discussed on pages 3 to 28 is common. This CCD sensor has a different configuration from that of the CCD sensor disclosed in Japanese Patent Publication No. 63-45153, but the signal processing can be digitized by similar processing.

[0011]

In a video camera using the above-mentioned pixel-mixing readout type CCD sensor, a color difference signal corresponding to (RY) and (BY) is originally generated for each horizontal scan. One of the color difference signals not generated is interpolated by the color difference signal one horizontal scan (1H) before. Therefore, there is the following problem in image quality.

I) The vertical resolution of the color difference signal is reduced by the line interpolation.

II) Since the original signal processing of the camera, such as generating a color difference signal after subjecting the R, G, and B signals to γ processing, is not performed, the fidelity of color reproduction is lacked apart from the quality of the color tone. Also, the degree of freedom of the color matrix is small, and the color moiré tends to increase.

In a digital signal processing video camera discussed in Japanese Patent Publication No. 63-45153,
The basic configuration of signal processing is the same, and has similar problems.

An object of the present invention is to provide a digital signal processing circuit which does not have the above-mentioned problems in a video camera using the above-mentioned pixel-mixing readout type CCD sensor for the purpose of high image quality and rationalization.

[0016]

In order to achieve the above object, after an output signal of a CCD sensor is subjected to CDS (correlation double sampling), AGC (Auto Gain Control) processing and the like, an analog signal is converted into a digital signal for each pixel signal. A / D conversion means for converting, 1H delay means for delaying the first digital signal output from the A / D conversion means by 1H, and second digital signal output from the first digital signal and the 1H delay means. A first method for generating R (red), G (green), and B (blue) signals by separating pixel signals from digital signals and subjecting the separated pixel signals to matrix processing.
Calculation means; and enhancement means for generating a luminance (Y) signal having at least a vertical edge enhanced by using the first digital signal and the second digital signal as inputs,
Γ processing for each of the R, G, B and Y signals
Processing means; second arithmetic processing means for generating a color difference signal (RY) signal and a (BY) signal from the R, G, and B signals after the γ correction; and (RY), ( BY) signal and γ
A signal processing circuit is constituted by a standard television signal generating means for generating a standard television signal from the corrected luminance signal.

[0017]

The filter arrangement of the pixel-mixing readout type CCD sensor is as shown in FIG. 2, and the photoelectrically converted charges are read out two rows at a time. For example, in the A field, as shown in FIG., A _n, as referred to A n _{+ 1,} also, in the B field, B _n, reads as that B n _{+ 1.} (Here, the combination is changed between the A field and the B field for interlaced scanning. As a result, (Mg + Ye) and (G + C
y), and (Mg + Cy) and (G + Ye) pixel signals are output alternately.

Therefore, from the first digital signal and the second digital signal obtained by delaying the first digital signal by 1H, the above (Mg + Ye), (G + Cy), (Mg + Cy), (G
+ Ye) are obtained, and the R, G, B signals can be generated by processing them with the first arithmetic means. Assuming that Mg = R + B, Ye = R + G, and Cy = G + B, And therefore,

[0019]

(Equation 1)

## EQU1 ## now,

[0021]

(Equation 2)

Then, the above equation becomes Y = AX− (6). If the RGB matrix is X = A'Y- (7) and the equation (7) is substituted into (6), then Y = A (A'Y) = AA ') Y- (8), and A' is AA ′ = I (I is a unit matrix). A 'has a degree of freedom, and there are many solutions, but in practice, it is determined so that the color moiré is minimized. The first calculation means performs the matrix calculation of the equation (7) using A '. In the conventional system, it is difficult to optimize such a matrix, and therefore, the present system can reduce color moire compared to the conventional system.

The R, G, and B signals thus obtained are γ-corrected by the γ-correction means, and in the second arithmetic processing, the signals after the γ correction are used, for example, in NTSC, the following equation -Y = 0.7R-0.59G-0.11B- (9) BY = 0.89B-0.59G-0.3R- (10) The color difference matrix processing represented by the following equation is performed, and the color difference signal (R -Y) and (BY) are generated. At this time, unlike the conventional example described above, two color difference signals are generated for each horizontal scan without interpolation. The process of generating the above color difference signal is a normal color signal process, and has excellent color reproduction fidelity.

Therefore, according to the present method, the above-mentioned problems of the prior art such as the vertical resolution of color, the fidelity of color reproduction, and the color moiré can be solved.

Further, in the above-mentioned enhancer circuit, a difference signal between the first digital signal and the second digital signal is obtained, and after processing such as base clipping and high-frequency noise removal is performed on the difference signal, the first digital signal is processed. To the digital signal (or the second digital signal) to perform vertical edge enhancement. That is, with the above configuration in which the 1H delay unit is shared between the color separation and the enhancer, the response in the vertical direction can be improved without adding the 1H delay unit.

When the above processing is performed by analog processing, the 1H delay is constituted by a synchronous CCD delay line. In this case, 1) gain variation 2) poor linearity 3) Color mixture occurs between the two types of pixel signals of the dot sequential signal.

As a result, the generated color signal flaps (line pair) every horizontal scanning. On the other hand, in this method, because of digitization,
There is an advantage that the above 1) variation, 2) linearity, 3) color mixing does not occur and the line pair can be prevented.

In addition, the following effects described above can be obtained by greatly digitizing the signal processing.

I) A filter constituted by a large-sized CCR can be constituted by a digital filter and integrated into an IC.

II) No adjustment is required to absorb variations.

III) Automatic electronic adjustment of each adjustment is possible.

IV) A single-chip integration of IC is possible by incorporating A / D and D / A.

V) S / N degradation can be prevented by sufficiently considering S / N degradation due to rounding errors.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, 1 is a solid-state imaging device, 2 is a preprocessing circuit, 3 is an A / D conversion circuit, 4 is a drive circuit, 5 is a control circuit, 6 is enhancement circuits 7a and 7b are γ.
(Gamma) correction circuit, 8 is 1H delay memory, 9 is RGB
Matrix circuit, 10 is a white balance circuit, 12 is a color difference matrix circuit, 13 is a standard television signal generation circuit, 14.14a to 14h.15 to 27.28a.2.
8b is a terminal.

The drive circuit 4 synchronizes with the control circuit 5 to transmit a drive pulse to the solid-state image pickup device 1 via a terminal 28a and a pre-processing circuit to supply a control pulse required for the CDS via a terminal 28b. Supply. The solid-state imaging device 1 reads an electric signal obtained by photoelectrically converting an image formed on an imaging surface by a lens (not shown) according to the supplied driving pulse. The signal output from the solid-state imaging device 1 is supplied to a pre-processing circuit 2, where a CDS process for improving noise reduction and an AGC process for keeping the signal amount constant are performed.
Supplied to In the A / D conversion circuit 3, the pixel signal supplied from the pre-processing circuit 2 is A / D-converted in a dot-sequential manner for each pixel by an A / D conversion clock supplied from the control circuit 5 to the terminal 14d. Digital signal to RGB
It is supplied to the matrix circuit 9, the 1H delay memory 8 and the enhancement circuit 6. The configuration of the digital signal changes every horizontal scanning. As described above, a certain horizontal scanning consists of two color pixel signals (the two color pixel signals are A and B). (Pixel signals of these two colors are C and D). These two color pixel signals are obtained alternately in a dot-sequential manner. (Less than,
This signal is called a dot-sequential signal. Here, for example, in the sensor having the filter arrangement shown in FIG. 2, the above four pixel signals are (Mg + Ye), (G + Cy), (Mg + C
y), (G + Ye), and the dot sequential signal shown in FIG. 3 is obtained. In the 1H delay memory, the supplied dot sequential signal is delayed by 1H and then supplied to the enhancer circuit 6 and the RGB matrix circuit 9. In the RGB matrix circuit 9,
From the point-sequential signal supplied from the A / D conversion circuit 3 and the 1H-delayed point-sequential signal supplied from the 1H delay memory,
The four color pixel signals A, B, C, and D are separated, and the separated pixel signals A, B, C, and D are subjected to matrix processing to generate R, G, and B signals for each horizontal scan. I do. R, G, B generated by the RGB matrix circuit
The signal is supplied to the white balance circuit 10 to perform white balance processing. This white-balanced R
The G and B signals are further supplied to the γ processing circuit 7a. γ
The processing circuit 7a performs γ processing on the supplied R, G, and B signals, and outputs the processed R, G, and B signals to the color difference matrix circuit 12.
To supply. The color difference matrix circuit 12 performs matrix processing on the supplied γ-corrected R, G, and B signals to generate color difference signals (RY) and (BY) for each horizontal scan as described above. The signal is supplied to the signal generation circuit 13. The above is the color difference signal processing up to the generation of the color difference signal.

Next, the luminance signal processing will be described.

The luminance signals are the above-described pixel signals A, B, and C.
And D. In the enhancement circuit 6, first, A
The bandwidth of the point-sequential signal supplied from the / D conversion circuit 17 and the point-sequential signal supplied from the 1H delay memory 8 are limited (fs / 2
The component is removed, fs: the pixel reading frequency), and a luminance signal before 1H delay and a luminance signal after delay are generated. Next, by taking the difference between these two luminance signals, a high-frequency component in the vertical direction is extracted, and this is added to the luminance signal before the 1H delay or the luminance signal after the delay, thereby enhancing the vertical high-frequency component of the luminance signal. (Enhance). In this manner, the luminance signal in which the high frequency in the vertical direction is emphasized further emphasizes the high frequency in the horizontal direction. As a result, the MTF (Modulation Transfer Fact
or), the deterioration of the MTF of the luminance signal can be compensated. The luminance signal that has been subjected to the above enhancement processing is output to the γ processing circuit 7.
b. The γ processing circuit 7b performs γ processing on the supplied luminance signal, and supplies the luminance signal after γ processing to the standard signal generation circuit 13. The above is the luminance signal processing up to the γ processing.

In the standard signal generation circuit 13, the color difference signals (RY) supplied from the color difference matrix circuit 12,
(B−Y) and the luminance signal supplied from the γ processing circuit 7b in accordance with the control signal supplied from the terminal 14c.
A standard television signal such as TSC is generated and output.
At this time, if the input interface of the equipment to be connected is digital, the digital signal is output as it is, and if it is an analog input, it is output after D / A conversion.

The above is the operation of the first embodiment of the present invention. According to this embodiment, the following effects are obtained as described above.

First, 1) the color difference signals (RY) and (BY) can be generated for each horizontal scan by the signal processing method, and the vertical resolution of the color signals is hardly deteriorated.

2) Good color reproducibility, high degree of freedom of color matrix, and little moiré.

3) Without adding a 1H delay memory,
The luminance signal can be enhanced in the vertical direction.

Next, the digitization can prevent the above-mentioned line pair occurring in the color difference signal when the same processing is performed in 4) analog signal processing.

5) There is almost no S / N deterioration in signal processing, and high S / N processing can be performed.

6) Further, the following rationalization is possible.

I) ICs can be integrated with high accuracy by configuring digital filters as filters, which are large components composed of LCRs.

II) There is no variation and no adjustment for absorbing variation is required.

III) Automatic electronic adjustment can be performed.

IV) By incorporating A / D and D / A, a one-chip signal processing IC can be realized.

FIGS. 4 to 13 are block diagrams showing an example of each block of the first embodiment in detail, and show signals of each section in each block. Hereinafter, each block will be described with reference to these drawings.

FIG. 4 shows an example of the RGB matrix circuit 9, and FIG. 5 shows signal waveforms at various parts in this example. In FIG. 4, reference numeral 30 denotes a switch, 31a and 31b demultiplexers (De-Multiplex, hereinafter simply referred to as De-MPX), 32a to 32l coefficient multiplier circuits, and 33a to 33c.
Denotes an adder circuit, and 29a to 29c denote latch circuits. The A / D converter 3 and the 1H delay memory 8 supply an A / D converted point-sequential signal and a signal obtained by delaying the point-sequential signal by 1H to the SW 30 via the terminals 17 and 18.
As described above, the structure of the dot sequential signal changes for each horizontal scan. For a certain horizontal scan, the dot sequential signal is composed of pixel signals A and B as shown in FIG. As shown, it is composed of pixel signals C and D. Therefore, when the signal shown in FIG. 5A is input to the terminal 17 in a certain horizontal scan, the signal shown in FIG. 5B 1H before is input to the terminal 18, and in the next horizontal scan, 5 (b) and FIG. 5 (a) are input to the terminals 17 and 18, respectively.
Are alternately supplied for each horizontal line. Switch 30
In accordance with the pulse of the half frequency of the horizontal frequency supplied from the terminal 14e, the De-MPXs 31a and 31
The above-mentioned dot-sequential signal supplied to b is switched. As a result, D
The signals shown in FIG. 5A and FIG. 5B are always supplied to the e-MPXs 31a and 31b, respectively. De-M
In the PX 31a, two pixel signals A _i and B _i (i = 0, 1, 1) included in the dot-sequential signal supplied from the switch 30
2, 3...) To generate signals shown in FIGS. 5 (c) and 5 (d). Similarly, in De-MPX31b, separates the pixel signal C _i and D _i, FIG. 5 (e), generates a signal shown in (f). De-MPX31a, pixel signals A _i and B _i and C _i and D _i generated by 31b is, as shown in FIG. 4, & respective coefficient multiplying circuits 32a-32e, 32i and 32b
32f ・ 32j and 32c ・ 32g ・ 32k and 32d ・
It is supplied to 32h and 32l. Multiplication circuits 32a, 32b,
32c, 32d, 32e, 32f, 32g, 32h, 3
In 2i, 32j, 32k, and 32l, the supplied pixel signals are sequentially converted into k _r1 to k _r4 , k _g1 to k _g4 , and k _b1 to k _r1 , respectively.
Each signal obtained by multiplying by a coefficient of k _b4 and calculating
As shown in FIG. 4, the signals are supplied to the adders 33a to 33c.
The addition circuits 33a to 33c add the supplied signals, and the signals after the operation are added to the latch circuits 33a to 33c, respectively.
To supply. Here, the calculations of the coefficient multiplication circuit and the addition circuit are summarized as follows.

[0053]

(Equation 3)

Here, A 'is used for the aforementioned matrix,

[0055]

(Equation 4)

If so, equation (9) is an RGB matrix operation, and as a result, R _i , G _i , and B _i are obtained. The latch circuit 29 a to 29 c, supplied R _i, G _i, to B _i signal is latched by the latch clock supplied from the terminal 14e output. Thus, the latch circuits 29a to 29a
From c, the signals shown in (8), (h), and (i) of FIG. 5 are output. The above is the operation of the RGB matrix circuit.

Next, an example of the gamma processing circuit 7a will be described with reference to FIG. 6, 34a to 34c are subtraction circuits, 35a to 35c are black level detection circuits, and 36a to 36c.
c is a gamma correction circuit. The R _i , G _i , and B _i signals after the gain adjustment supplied from the white balance circuit 10 are subtracted from the subtraction circuits 34a to 34c and the black level detection circuit 35a, respectively.
To 35c. Black level detection circuits 35a to 35c
Then, the black level is detected from the supplied R _i , G _i , and B _i signals, and the detected values are respectively subtracted by the subtraction circuit 3.
4a to 34c. There are several methods for detecting the black level, but a general method is to block a part of the horizontal or vertical BLK portion of the light receiving surface of the sensor and remove the optically black portion. And each signal R _i ,
G _i, by integrating the B _i is a method of detecting the black level. In the case of this method, the black level detection circuits 35a to 35c detect the black level by averaging the signals in the optical black level period according to the pulse indicating the optical black level period input from the terminal 14g. In the subtraction circuit, the supplied R _i ,
G _i, the B _i signal, the black level detection value supplied from the black level detecting circuit 35a~35c subtracted respectively, align the black level of the γ signal constant value (e.g., 0). (This processing is called black level reproduction.) R _i ,
G _i, B _i signal is supplied to γ correction circuit 36 a - 36 c,
The gamma correction circuits 36a to 36c perform gamma correction represented by the following equation.

R _i ′ = (R _i ) ^1/2 − (11) G _i ′ = (G _i ) ^1/2 − (12) B _i ′ = (B _i ) ^1/2 − (13) , Γ are 2.2 in the NTSC system and PA
In the L, SECAW system, it is 2.8. However, in practice, the γ correction is performed by approximation using, for example, a polygonal line characteristic as shown in FIG.

FIG. 8 is a block diagram showing an example of the color difference matrix circuit 12. In FIG. 8, 37a to 37
c and 38a to 38c are coefficient multiplication circuits, 39a and 39b
Denotes an adder circuit, and 40a and 40b denote latch circuits. The operation of this configuration example is as follows. The R _i ′, G _i ′, and B _i ′ signals that have been γ-corrected by the γ processing circuit 7a are as shown in FIG.
Coefficient multiplication circuits 37a, 37b, 37c and 3 respectively
8a, 38b and 38c. Coefficient multiplication circuit 37
a, 37b, 37c and 38a, 38b, 38c,
In order, the supplied signal is 0.7, -0.59, -0.11.
, -0.3, -0.59, 0.89, and supplies the signals obtained by this operation to the adders 39a and 39b. The adders 39a and 39b add the supplied signals and add 0.7R _i '-0.59G _i ' -0.11B _i '-(14) and 0.89B _i ' -0.59G _i '-, respectively. A signal of 0.3R _i '-(15) is obtained. The signals given by these equations (14) and (15) are the color difference signals (RY) and (BY), respectively.
It is. The color difference signals (RY) and (BY) thus obtained
Are supplied to the latch circuits 40a and 40b, respectively.
In the latch circuits 40a and 40b, the supplied signal is
It is output after latching with the latch clock supplied from 14h.

FIG. 9 is a block diagram showing an example of the enhancement circuit 6. As shown in FIG. In FIG. 9, 41a and 41
b and 41c are low-pass filters (hereinafter simply referred to as LPFs), 42a and 42b are delay circuits, 43a and 43b are addition circuits, 44a and 44b are base clip circuits, and 45a
45b is a coefficient multiplying circuit, 46 is a band pass filter (hereinafter simply referred to as BPF), and 47 is a subtraction circuit. Less than,
The operation of the present embodiment will be described. First, LPF41a
And 41b are supplied with a dot-sequential signal and a dot-sequential signal delayed by 1H. As described above, these dot-sequential signals are signals in which two pixel signals (A and B or C and D) are repeated before each horizontal scan, and the components of the repeated cycle are removed by the LPFs 41a and 41b. By doing so, a luminance signal Y and a luminance signal Y _D delayed by 1H are obtained. Further, the luminance signal Y is supplied to the delay circuit 42a subtracting circuit 47, the luminance signal Y _D obtained by 1H delay and supplies to the subtracting circuit 47. The subtraction circuit 47 subtracts the luminance signal delayed by 1H from the luminance signal Y, and converts the difference signal (Y−Y _D ) into the LPF 41.
c. The LPF 41c removes high-frequency components including high-frequency noise from the supplied difference signal, and then supplies the difference signal to the base clip circuit 45a. Base clip circuit 45a
Has the input / output characteristics shown in FIG.
The following small amplitude components are regarded as noise and removed. Thus, a vertical enhancement signal is obtained. This vertical enhancement signal does not require much frequency characteristics, and the LPF 41c has a cutoff frequency of about 1 to 2 MHz. Further, the vertical enhancer signal is supplied to a coefficient multiplying circuit 45a.
In and k _V-fold, and supplies it to the adder circuit 43a. On the other hand, the delay circuit 42a delays the supplied luminance signal by a predetermined time and supplies the delayed luminance signal to the addition circuit 43a. At this time, the luminance signal is delayed by the total delay time of the subtraction circuit 47, the LPF 41c, the base clip circuit 44c, and the coefficient multiplication circuit 45a, and the delay time is made equal to the vertical enhancement signal supplied to the addition circuit 43a. The addition circuit 43a adds a vertical enhancement signal to the supplied luminance signal to generate a luminance signal that has been enhanced in the vertical direction. further,
This luminance signal is supplied to the delay circuit 42b and the BPF 46. The BPF 46, the base clipping circuit 44b, the coefficient multiplying circuit 45b, the delay circuit 42b, and the adding circuit 43b constitute a horizontal enhancer. The BPF 46 extracts a frequency component to be enhanced from the supplied luminance signal. Further, the frequency component extracted by the BPF 46 is supplied to the base clip 44b. In the base clip 44b, small amplitude components are regarded as noise and removed from the supplied signal in the same manner as in the above-described base clip circuit 44a.
Generate a horizontal enhancement signal. Here, when the noise included in the signal is small, the base clip processing is not always necessary and can be omitted. The horizontal enhancement signal, after k _H multiplied by the coefficient multiplication circuit 45b, and supplies to the adding circuit 43b. In the delay circuit 42b, similarly to the delay circuit 42a, the BPF 46 and the base clip 4
The supplied luminance signal is delayed only by the total delay time of 4b and the coefficient multiplication circuit 45b, and then supplied to the addition circuit 43b. The addition circuit 43b adds the horizontal enhancement signal to the luminance signal. As described above, according to the present embodiment, a luminance signal enhanced both vertically and horizontally is obtained. However, when the above enhancement is performed, in general, at low illuminance where the signal S / N is low, noise is not removed by the above-described base clip circuit, and the S / N deteriorates. As a result, the image quality may be rather deteriorated. Accordingly, the coefficient multiplying circuits 45a and 45b further determine the enhancement amount. The coefficients k _H and k _V are set to be smaller at low illuminance than at high illuminance. For example, in conjunction with the AGC voltage, k _H and k _V are reduced when the AGC operates.

FIG. 11 is a block diagram showing an embodiment of the standard signal generation circuit 13. In FIG.
48a and 48b are addition circuits, 49 is an encoder circuit, 5
0a and 50b are D / A conversion circuits.

In standard television signals such as NTSC, PAL, and SECAM, a chrominance signal is generally multiplexed with a luminance signal after being modulated. The modulation method of this color signal differs depending on each method, and NTSC and PAL use the color difference signal (R-
Y) and (BY) are quadrature balanced modulated by the color subcarrier fsc. In SECAM, the color difference signal is FM-modulated line-sequentially. Easy to digitize is NTSC and PAL
This is a quadrature balanced modulation scheme. The digital quadrature balanced modulation is basically the same as the analog case, and (R−
Y) and (B−Y) may be phase-shifted by 90 ° and may be balanced-modulated by two pulses having a frequency of fsc, and then the two signals may be added. Also, this digital balanced modulation circuit
When the pulse is H, a positive polarity signal is output. When the pulse is L, a negative polarity signal is output. FIG. 11 shows NTSC which can easily modulate this color signal.
And the PAL system. The operation will be described below.

The color difference signals (RY) and (BY) are supplied from the color difference matrix circuit to the encoder 49 and the addition circuit 48a via the terminals 22 and 23. The adding circuit 48a adds the burst signal supplied from the control circuit 5 via the terminal 14c to the supplied (BY) signal, and supplies the signal to which the burst has been added to the encoder 49. In the encoder 49, the supplied color difference signal (R
-Y) and (B-Y) are subjected to the above-described digital quadrature balanced modulation by the sub-carrier pulse supplied from the control circuit 5, and the modulated color signal is further supplied to the D / A conversion circuit 50a. The D / A conversion circuit 50a performs D / A conversion of the supplied color difference signal and outputs a converted analog color signal. The luminance signal is supplied to the addition circuit 48b via the terminal 27.
To supply. The adder circuit 48b adds a composite synchronizing signal (C · SYN) supplied from the control circuit 5 to the supplied luminance signal.
C) is added and supplied to the D / A conversion circuit 50b. D /
The A conversion circuit 50b D / A converts the supplied digital luminance signal and outputs the converted analog luminance signal.

The main blocks of the first embodiment have been described above. Although the white balance circuit 10 and the luminance signal 7b have not been described in detail,
The white balance circuit 10 can be easily constituted by a digital multiplication circuit for changing the gains of the R signal and the B signal, and the gamma processing circuit 7b for the luminance signal can be constituted exactly like the gamma correction circuit 7a for the color signal. In addition, each of the above blocks has been described with an extremely orthodox configuration. However, actually, the configuration becomes more complicated due to the purpose of suppressing an increase in the number of circuits. This example will be described with reference to FIGS.

FIG. 12 is a block diagram showing another example of the above-mentioned gamma correction circuit 7a, and FIG. 13 shows the waveform of each part. In FIG. 12, 35a, 35b and 35c are the above-described black level detection circuits, 34 is a subtraction circuit, 36 is a gamma correction circuit similar to that described above, and 51a and 51b are multiplexers (hereinafter simply referred to as MPX). R input from terminal 20
_i, G _i, B _i signal supplies MPX51a and black level detecting circuit 35a, 35b, to 35c, respectively. The black level detection circuits 35a, 35b, and 35c detect the black levels of the respective color signals R _i , G _i , and B _{i in} the same manner as in the above-described embodiment, and detect the detected values k _r , k _g , and k of the respective black levels. _b to MP
X51b. In the MPXs 51a and 51b, FIG.
3 (a), (b) and (c), the supplied R _i , G _i ,
The _Bi signal and the above k _r , k _g , and k _b are multiplexed in a dot-sequential manner according to the select signal supplied from the control circuit 5 as shown in FIGS. The multiplexed color signal and the black level detection value are supplied to a subtraction circuit 34, which further subtracts the multiplexed black level from the multiplexed color signal, as shown in FIG. A signal is generated by multiplexing the above-described color signals reproduced at the black level. The color signal reproduced at the black level is supplied to the γ correction circuit 36, and γ correction is performed in the same manner as in the above γ correction circuit, and the γ corrected color signals R _i ′ and G shown in FIG. _i ′ and B _i ′ are multiplexed. According to this example, the number of circuits is increased only by a small-scale MPX circuit, the circuit scale is large, and three channels are required.
All you need is a channel. As a result, an increase in the circuit scale can be suppressed as much as possible.

The example of reducing the circuit scale of the γ processing has been described above, but the circuit scale can be reduced in other color signal processing blocks by the same method.

FIG. 14 is a block diagram showing a second embodiment according to the present invention. In FIG. 14, 11 is a comb filter, 52a and 52b are 1H delay memories, 53
a and 53b are addition circuits. In this embodiment, the first
The same reference numerals are given to the portions having the same functions as those of the embodiment, and the description is omitted here. Hereinafter, portions different from the first embodiment will be described.

This embodiment is different from the first embodiment in that 1H delay circuits 52a and 52b and adder circuits 53a and 53a are provided between the color difference matrix circuit 12 and the standard signal generation circuit 13.
53b. 1H delay circuits 52a and 5
An adder 53a delays the (RY) and (BY) signals output from the color difference matrix circuit by 1H, respectively.
And 53b. In the adder circuits 53a and 53b, the color difference signals (R-
Y) and (BY), 1H delay circuits 52a and 52b
1H delayed (RY) and (B-
Y) are added. That is, the 1H delay circuit 52
a, the addition circuit 53a, and the 1H delay circuit 52b and the addition circuit 53b each constitute a so-called comb filter. For this reason, the standard signal generation circuit 13
3a and the color difference signal (R-
Y) and (BY) are S / S with respect to the case of the first embodiment.
N has been improved. Further, in photographing a subject having a portion where different colors are in contact with the screen obliquely, an effect of reducing unnaturalness in which the boundaries of the colors are jagged can be obtained. Although the vertical resolution of the color difference signal is slightly deteriorated, the deterioration is less than when a similar comb filter is used in the conventional method. Other effects are the same as those of the first embodiment.

FIG. 15 is a block diagram showing a third embodiment according to the present invention. In the present embodiment, the second
The number of 1H delay memories used for signal processing is smaller than that of the embodiment of 1), and 1) S / N of the same degree as the comb filter of the second embodiment.
And 2) realizing a 3-line vertical enhancer. In FIG. 15, 8 'is a 1H delay memory, 9' is R
A GB matrix circuit 6 'is an enhancer circuit. The other parts are the same as those of the first embodiment, and the same reference numerals are used here to omit the description.

This embodiment differs from the first and second embodiments in that the RGB matrix circuit 9 'and the enhancer circuit 6' are composed of an A / D conversion circuit 17, a 1H delay memory 8 and a 1H delay memory. By processing pixel signals of three adjacent horizontal scans supplied from the memory 8 ', R, G,
Generating the B signal and the luminance signal. Hereinafter, the operations of the RGB matrix circuit 9 'and the enhancement circuit 6' will be described with reference to FIGS.

FIG. 16 is a block diagram showing an example of the RGB matrix circuit 9 '. In FIG.
54 is an addition circuit, 55 is a coefficient multiplication circuit, and 9 is an RGB matrix circuit of the first embodiment. Now, assuming that two pixel signals A _i and B _i are input from the terminal 17 in a certain l-th horizontal scan, the terminal 18 has 1-delayed 1− Pixel signals C _i and D _i obtained in the first horizontal scanning are input, and
To 8 ′, pixel signals A _i and B _i obtained in the (l−2) th horizontal scan delayed by 2H are input. Here, in the following description, in order to distinguish pixel signals of each horizontal scan, for example, a pixel signal obtained in the l-th horizontal scan is

[0072]

(Equation 5)

Is displayed. Terminal 17 and terminal 1
Input from 8 '

[0074]

(Equation 6)

And

[0076]

(Equation 7)

Is supplied to the adding circuit 54. The adder circuit 54 adds the supplied pixel signals, and obtains the resulting pixel signal.

[0078]

(Equation 8)

Is supplied to a coefficient multiplying circuit 55. The coefficient multiplying circuit 55 multiplies the supplied signal by １ ／ and supplies the signal to the RGB matrix circuit 9. In the RGB matrix circuit 9, the pixel signal supplied from the coefficient multiplying circuit 55

[0080]

(Equation 9)

And a dot-sequential signal consisting of

[0082]

(Equation 10)

From the dot sequential signals comprising

[0084]

[Equation 11]

Then, the same matrix processing as in equation (9) is performed, and

[0086]

(Equation 12)

Is obtained. Also this

[0088]

Equation 13] B _T ^l _i is represented by the following formula.

[0089]

[Equation 14]

By transforming this,

[0091]

(Equation 15)

Here, the first and second terms on the right side of the above equation are the same as those in the equation (9), and are obtained by the l-th and (l-1) -th adjacent horizontal scans in the first embodiment. .

[0093]

(Equation 16)

And

[0095]

[Equation 17]

Is as follows. Equation (17) is

[0097]

## EQU18 ## which is obtained by the RGB matrix circuit 9 '.

[0098]

[Equation 19]

Was obtained in the first embodiment.

[0100]

(Equation 20)

The result is the same as the one processed by the comb filter. Compared to the second embodiment, there is a difference between the operation with the RGB signal and the operation with the color difference signal. However, in the present embodiment, similarly to the second embodiment, the S / N of the color signal is improved. And the unnaturalness of the border between colors can be reduced. FIG.
4 shows an example in which the circuit shown in FIG.

FIG. 18 is a block diagram showing an example of the enhancement circuit 6 '. In FIG. 18, 41
a, 41b, 41c, 41d are LPFs, 56a, 56
b and 56c are coefficient multiplication circuits. In addition, the same portions as those in the example shown in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted here. First, a dot-sequential signal that has been A / D converted by the A / D conversion circuit 3 is input from the terminal 17.
Further, a point sequential signal delayed by 1H by the 1H delay memory 8 is input from the terminal 18. Further, from the terminal 18 ', the 1H delay circuit 8 and the 1H delay circuit 8'
A delayed point-sequential signal is input. These dot sequential signals are supplied to the LPFs 41a, 41b and 41d, respectively. In the LPFs 41a, 41b, and 41d, as in the embodiment shown in FIG. 9, frequencies near the repetition frequency of two pixels are removed, and a luminance signal is generated from each point-sequential signal. Further, in the coefficient multiplication circuits 56a, 56b, 56c,
The luminance signals supplied from the LPFs 41a, 41b, and 41d are multiplied by ／, ２ ，, and −１, respectively, and supplied to the addition circuit 47. The addition circuit 47 adds the supplied signals and outputs the result of the operation. Now, LPF41
an output signal when a Y _M than b, the signal output from 41a and 41d are Y _M · Z and Y · Z ^-1. Therefore, when the output signal Y _E of the adder circuit, Y _E is

[0103]

(Equation 21)

And the transfer function is

[0105]

(Equation 22)

The following is obtained. This is a third-order symmetric FIR filter, and is a BPF having a flat group delay characteristic. Furthermore Y _E signal extracted in this BPF, after having reduced noise LPF41d and base clip 44a, the gain adjust in the coefficient multiplying circuit 45a, and supplies to the adding circuit 43a. The adder circuit 43a, the luminance signal Y _M delayed adjusted by the delay circuit 42a, and adds the vertical enhancer signal supplied from the coefficient multiplier circuit to obtain a luminance signal subjected to vertical enhancement processing. The above-described vertical enhancer section is a so-called three-line enhancer, and has extremely excellent transient response characteristics as compared with the above-described enhancer circuit. The transient response waveform at the vertical edge obtained by the enhancer circuit is shown in FIG. 19A in comparison with the waveform by the enhancer (FIG. 19B). In FIG. 19, the waveform obtained by the present enhancement circuit is such that the undershoot and overshoot are balanced, the vertical edge is emphasized by a good transient response, and an RGB matrix circuit for performing color separation with the present enhancement circuit 6 '. 9 '
Two 1H delay memories are shared, so less 1H
The delay memory can realize 1) improvement of S / N of a color signal and reduction of unnaturalness of a boundary of a color signal, and 2) enhancement of three lines.

The other effects are the same as in the first embodiment, as in the second embodiment.

FIG. 20 is a block diagram showing a fourth embodiment according to the present invention. 20, reference numeral 57 denotes a white detection circuit, and 58 denotes a terminal for supplying a detection value of the white detection circuit to the control circuit 5. Further, the same reference numerals are given to the components which operate in the same manner as in the above-described embodiment, and the description is omitted. This embodiment is obtained by adding an automatic white balance adjustment circuit to the third embodiment. Hereinafter, the operation of the automatic white balance adjustment circuit will be described. First, the white detection circuit 57 obtains two color difference signals R and Q signals by performing a matrix operation on two color difference signals (RY) and (BY) supplied from the color difference matrix circuit. The R signal axis is an axis through which white moves when the color temperature changes,
The Q signal axis is an axis orthogonal to this. Now, if the above conversion matrix is H,

[0109]

(Equation 23)

Is obtained. The white detection circuit 57 detects a region 59 indicated by oblique lines in FIG. 21 with the R and Q signals, and generates a detection signal by integrating the R signal in this region.
(This detection signal is denoted by ∫Rdt.) Further, the detection signal ∫Rdt is supplied to the control circuit 5 through the terminal 58. The control circuit 5 has a built-in up-down counter.
If Rdt is positive, the up / down counter counts down, and if ∫Rdt is negative, it counts up. Further, assuming the counter value R _Det obtained in this way,

[0111]

(Equation 24)

[0112] made to the coordinate axes conversion, the control voltage K _R and K _B
Generate Moreover K _R, K _B white balance circuit 1
Is supplied to the 0, the white balance circuit 10, K _R, K _B
, The gains of the R signal and the B signal are controlled. here,
The white balance circuit 10, the γ correction circuit 7a, the color difference matrix circuit 12, the white detection circuit 57, and the control circuit 5 constitute a control loop, and perform control so that ∫Rdt = 0. When ∫Rdt = 0, the white balance is maintained, and R−Y 0 and B−Y 0 hold in the achromatic portion.

In this embodiment, in addition to the effects of the third embodiment, the white balance can be automatically adjusted.

FIG. 22 is a block diagram showing a fifth embodiment according to the present invention. This embodiment is an embodiment in which an automatic white balance adjustment circuit is added as in the fourth embodiment.
However, in the above-described fourth embodiment, the color difference signals RY and BY are provided.
In this embodiment, white detection is performed from RGB signals, while white detection is performed more. In the present embodiment, automatic white balance adjustment can be realized in the same manner.

[0115]

Since the present invention is configured as described above, it has the following effects.

First, effects due to the signal processing method are as follows: 1) Two color difference signals (RY) and (B) for each horizontal scan.
−Y) is generated, so that the vertical resolution of the color signal is hardly degraded.

2) Since it is an orthodox color signal processing and the degree of freedom of the color matrix is high, color reproduction fidelity is good and color moire is small.

3) The 1H delay circuit for color separation can be shared with the vertical enhancement circuit, so that enhancement in the vertical direction can be performed without adding a 1H delay memory.

Next, the effects of digitizing the signal processing are as follows: 4) When the same processing is performed in the analog signal processing, a line pair of the color difference signal is generated due to the variation. This phenomenon can be prevented.

5) S / N degradation hardly occurs due to signal processing, and high S / N processing can be performed.

6) The following can be rationalized.

I) ICs can be integrated with high accuracy by using digital filters for filters, which are large components composed of LCRs.

II) There is no variation, and adjustment for absorbing variation is unnecessary.

III) Automatic electronic adjustment pressure is available.

IV) One chip I with built-in A / D and D / A
C conversion is possible.

7) The 1H delay memory can set the number of delay stages arbitrarily as compared with the analog CCD delay line.

With such a feature, any CCD sensor having a different number of horizontal pixels or the like can be handled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic diagram of a filter arrangement of a solid-state imaging device.

FIG. 3 is a schematic diagram of a digital point-sequential signal.

FIG. 4 is a block diagram showing an example of each block of the first embodiment.

FIG. 5 is a waveform chart of each part of the RGB matrix circuit.

FIG. 6 is a block diagram showing an example of each block of the first embodiment.

FIG. 7 is an input / output characteristic diagram of a γ correction circuit.

FIG. 8 is a block diagram showing an example of each block of the first embodiment.

FIG. 9 is a block diagram showing an example of each block of the first embodiment.

FIG. 10 is an input / output characteristic diagram of a base clip circuit.

FIG. 11 is a block diagram showing an example of each block of the first embodiment.

FIG. 12 is a block diagram showing an example of each block of the first embodiment.

FIG. 13 is a waveform chart of each part of the γ correction circuit.

FIG. 14 is a block diagram showing one embodiment of the present invention.

FIG. 15 is a block diagram showing one embodiment of the present invention.

FIG. 16 is a block diagram showing an example of each block of the third embodiment.

FIG. 17 is a block diagram showing an example of each block of the third embodiment.

FIG. 18 is a block diagram showing an example of each block of the third embodiment.

FIG. 19 is a waveform diagram of a luminance signal after enhancement.

FIG. 20 is a block diagram showing one embodiment of the present invention.

FIG. 21 is a chromaticity diagram showing an area where white detection is performed.

FIG. 22 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Preprocessing circuit, 3 ... A / D conversion circuit, 4 ... Drive circuit, 5 ... Control circuit, 6 ... Enhancement circuit, 7a, 7b ... γ correction circuit, 8 ... 1H delay memory, 9 ... RGB matrix circuit, 12 ... color difference matrix circuit, 13 ... standard signal generation circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Michio Masuda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-175594 (JP, A) 2-128591 (JP, A) JP-A-53-107231 (JP, A) JP-A-61-191684 (JP, U) JP-B-63-45153 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 9/04-9/11 H04N 9/64-9/78

Claims (3)

(57) [Claims] In a horizontal scanning period, a first color and a first color are used.
Consists of a repetition of two types of pixel signals corresponding to the second color
In the next horizontal scanning period, the third color and
And the repetition of two types of pixel signals corresponding to the fourth and fourth colors.
A solid-state imaging device for outputting a dot-sequential signal, an A / D conversion circuit for digitally converting the dot-sequential signal output from the solid-state imaging device, and one horizontal scan of the signal output from the A / D conversion circuit A first 1H delay circuit for delaying a period, a second 1H delay circuit for delaying a signal output from the first delay circuit for one horizontal scanning period, the A / D conversion circuit, and the first 1H delay Circuit and the second one
The first, second, and second signals output from the H delay circuit
3, four different pixel signals corresponding to the fourth color are mapped.
By Torikusu operation, R, and the RGB generating circuit for generating G, and B signals, and color difference matrix circuit for generating the RGB generating circuit R that is output from, G, the color difference signal by calculating the B signal, the A / D conversion means and the signal output from the first 1H
A luminance signal generating means for generating a luminance signal from a signal output from the delay means and a signal output from the second 1H delay circuit; a color difference signal output from the color difference matrix circuit; and the luminance signal generating means A standard signal generation circuit for generating a standard signal based on the luminance signal obtained from the image signal. 2. A gamma correction circuit for multiplexing video signals output from the R, G, B signal generation circuit, correcting the black level of the multiplexed color signals in a point-sequential manner, and performing gamma correction. And
2. The imaging apparatus according to claim 1, wherein the color difference matrix circuit generates R, G, and B signals output from the gamma correction circuit to generate a color difference signal. 3. The image pickup device has a filter in which four different colors are arranged, and reads out the photoelectrically converted signals every two rows to correspond to the first color and the second color. 3. The method according to claim 1, wherein a pixel signal, a pixel signal corresponding to a third color and a fourth color are output in a dot-sequential manner, and a combination of a certain field and two rows read in the next field is changed. An imaging device according to any one of the preceding claims.