JP2738778B2 - Imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device, and more particularly to an imaging device having an optimal digital signal processing circuit.

[Conventional technology]

In recent years, the penetration rate of home video cameras has been rapidly increasing. The reasons for the rapid increase in the penetration rate are 1) small size and light weight, 2) low cost, 3) improvement in performance such as high image quality, and 4) integration of the VTR (Video Tape Recorder) unit and camera unit. There is an improvement in usability through the development of a movie. In addition, there are not a few parts where 1) solid-state imaging device and 2) rationalization of signal processing have contributed to the realization of these.

Solid-state imaging devices have many features such as small size, light weight, and high reliability. At the beginning of development, solid-state imaging devices were inferior to imaging tubes in terms of manufacturing cost, sensitivity resolution, etc., but due to rapid advances in semiconductor technology, cost and performance have surpassed those of imaging tubes. At present, solid-state imaging devices are used in almost all home video cameras. These circumstances are discussed in the Journal of the Institute of Television Engineers of Japan, Vol. 41, No. 11 (1987), pp. 983-990.

On the other hand, in signal processing circuits, large-scale integrated circuits have been promoted with the improvement of signal processing for the purpose of miniaturization, low cost, and high performance. As a result, coupled with the adoption of the solid-state imaging device described above, the home video camera has a high image quality and a significantly small size / size.
Weight reduction and cost reduction have been achieved. However, when considering further rationalization of signal processing, there is a limit in the current signal processing method based on analog signal processing, and in the future the signal processing method based on digital signal processing technology having the following features seems to be the favorite .

1) Filters, which are large components, can be integrated into ICs with high accuracy.

2) Built-in A / D and D / A enables one chip.

3) S / N ratio of signal processing circuit can be easily increased by designing with sufficient consideration of S / N deterioration due to rounding error of operation.

An example of such digital signal processing of a video camera is discussed in JP-B-63-45153.

[Problems to be solved by the invention]

There are still many problems to be solved in digitizing the signal processing of a video camera using the above CCD sensor. One of them is the digitization of a color signal encoder.

Currently used CCDs have a number of horizontal pixels. Since the horizontal scanning period is constant, the frequency of the horizontal pixel read clock (hereinafter simply referred to as a sensor clock) differs depending on the number of pixels. For example, the sensor clock frequency (hereinafter referred to as fs) for the NTSC system is 9.5 MHz, 12.7 MHz, and 14.3 MHz. In signal processing of a digital camera, generally, as described in JP-B-63-45153, it is easy to perform processing in synchronization with the sensor clock, and the circuit scale is reduced. However, as far as the encoder is concerned, it is necessary to process at a clock which is n times fsc (generally n: 3 or 4) times. Therefore, when all the signal processing of the camera is digitized, if the relationship of fs = n fsc (n = 3, 4, 6, 8 etc.) is not satisfied, (n fs ) A jitter of ^-1 occurs. Assuming that n = 4, the ^{jitter, NTSC: (4fsc) -1 =} 70ns PAL: (4fsc) is ^-1 = 56 ns. When the allowable amount of the jitter of the color signal was evaluated, it was about 35 ns or less. It was found that the above-mentioned jitter was unacceptable, and it was necessary to set n to 8 or more in order to suppress the jitter within the allowable value. However, actually, 8fsc (NTSC: 28.6MHz, PA
(L: 35.44 MHz) and performing data processing with the 8 fsc clock: 1) Oscillation tends to be unstable, and the specifications for the oscillator become severe. Also, the power consumption of the oscillator doubles.

2) The speed of the gate used in the encoding circuit is twice as fast as that of the conventional one, and the specifications required for the elements become severe, and the power consumption of the encoding circuit also increases.

In practice, it is preferable to process with a clock of 4 fsc or less.

Known examples of digitization of this encoder include:
It is not mentioned in JP-B-63-45153.

The purpose of this patent is to realize a video camera that digitizes all signal processing including the encoder, using a 4 fsc clock as a data processing clock in the encoder, and realizing a jitter that occurs at this time within an allowable value of 35 ns or less,
An object of the present invention is to realize a digital video camera which is optimal for low power consumption and reduction in size and weight.

[Means for solving the problem]

In order to achieve the above object, A / D conversion means for converting an output signal of a CCD sensor into a digital signal in synchronization with a sensor clock, and digitizing a sensor output output from the A / D conversion means with a sensor clock Signal processing means for generating a luminance signal and a color-difference signal based on the signal; encoding means for performing balanced modulation of the color-difference signal based on a clock having a period of 4 fsc (hereinafter simply referred to as 4 fsc clock); And D / A conversion means for converting each of the two digital signals of the modulated color signal generated by the above into an analog signal, wherein the digital video camera is generated by a signal processing means based on the sensor clock. A color difference signal of fs / m (m = 1, 2, 3, 4,...) cycles is latched by a latch pulse generated based on a 4 fsc clock from a control circuit described later. A data clock conversion means for converting and outputting a data clock by touching, and the signal processing means for providing a change phase of a color difference signal of fs / m cycle outputted by the signal processing means based on the sensor clock. From the phase reference signal (for example, the last stage latch pulse of the color difference signal), the latch pulse to be supplied to the data clock conversion means is generated based on the 4fsc clock, and the phase reference signal and the
A control circuit that detects a relative phase with respect to the 4fsc clock at a rising edge and a falling edge of the 4fsc clock, and controls a phase correction circuit, which will be described later, based on the detection signal, and a color difference signal supplied from the data clock conversion unit. Phase correction means for performing phase correction based on the phase detection signal supplied from the control circuit, and for supplying the corrected color difference signal to the encoding means.

[Action]

In the control circuit, the supplied phase reference signal is
The latch is performed at the rising edge and the falling edge of the sc. The change point of the color difference signal is “f” of 4fsc from the phase reference signal after the two latches.
It is determined whether it is during the period or during the 'L' period, and this detection signal is supplied to the phase correction circuit. Now this 4fsc
When the 'H' period and the 'L' period of the clock are substantially equal, the change point of the color difference signal can be determined in steps of 1/2 of (4fsc) ⁻¹ by the above processing. Here (4 fsc) from a ^{-1 / 2 = (8fsc) -1} , it is possible to know the change point in the result (8 fsc) ^-1 accuracy. Also, in this control circuit, as described above,
Further, the phase reference signal is processed by the 4fsc clock to generate a latch pulse, and the latch pulse is supplied to the data clock conversion means. Here, this latch pulse may have a maximum of (4fsc) ^-1 jitter with respect to the phase reference signal due to the phase relationship between the phase reference signal and the 4fsc clock.

The data clock conversion means latches the color difference signals (RY) and (BY) supplied from the signal processing means in accordance with the latch pulse supplied from the control circuit. As a result, the latched color difference signals (RY), (B
-Y) can be processed thereafter with a signal of the 4fsc clock system. However, as described above, since the latch pulse at this time has a jitter of (4fsc) ^{-1 at} the maximum, the color difference signal after the latch naturally has a jitter of (4fsc) ^{-1 at} the maximum.
The latched color difference signal is further supplied to the phase correction means.

In the phase correction means, first, the color difference signal having the maximum (4fsc) ^-1 jitter supplied from the data clock is latched by the above-mentioned latch pulse, and the color difference signal after the latch and the data before the latch supplied from the data clock are latched. Signal and
An intermediate phase color difference signal is generated. Next, according to the phase detection signal supplied from the control means, at the changing point of the color difference signal, the delay time due to the latch of the data clock conversion means for the color difference signal, on the 'H' side or the 'L' side of the 4fsc clock. Only when it is on the phase side where is shorter, the color difference signal of the above-mentioned intermediate phase is selectively output only for one clock of (4fsc) ^-1 , and the other portions output the color difference signal supplied from the data clock. . As a result, when maximum jitter occurs,
(4 fsc) only proceeds signal ^-1 effectively, 1/2 of (4 fsc) ^-1
Only can be delayed, the maximum jitter (4 fsc) may be ^{-1 / 2 = (8fsc) -1} . This is the allowable jitter of the color difference signal as described above.

FIG. 2 shows an example to make it easier to understand how jitter is reduced by the above processing. FIG. 2 shows that the sensor clock is fs (4fsc) × (2/3), the data cycle of the color difference signal is fs / 2, the edge of the phase reference signal matches the edge of the 4fsc clock, and the jitter is reduced. This shows the maximum state. In FIG. 2, the waveforms include a sensor clock and a waveform B.
Is the phase reference signal, 14 is the color difference signals (RY) and (B-
Y), the waveform 15 is the 4fsc clock when the rising phase of the 4fsc clock is in a phase (referred to as the A phase) slightly advanced from the rising phase of the phase reference signal, and the waveform 16 is the rising of the 4fsc clock. Is slightly delayed from the phase reference signal (referred to as phase B), a waveform 17 is a data latch clock at the time of phase A, a waveform 18 is a data latch clock at the time of phase B, and a waveform 19 is a data latch clock at the time of phase A. A waveform representing the color difference signal after latching at the time, a waveform 20 is a waveform representing the color difference signal after latching at the phase B, and a waveform 21 is a waveform representing the color difference signal obtained by performing the phase correction at the phase B. .
Here, the data latch clock sets the phase reference signal to 4fsc.
It is generated by latching twice at the rising edge of the clock. The reason why the latch data is generated by latching twice is generally to prevent the latch data from becoming unstable sometimes when the phases of the latch data and the latch clock completely match, thereby preventing malfunction. However, whether or not jitter occurs in the latch is determined by the first latch. As described above, the phase determination is that the phase reference signal 13 is 4f
It is in the 'H' period (a in the figure) of the sc clock or 'L'
According to the above assumption, when the rise of the phase reference signal 13 is in the phase B in the "L" period of 4fsc, as shown in FIG. 2, the data after latching is almost (4fsc). ^It's time to go ^-1 . Therefore, the control means detects the B phase and supplies this detection signal to the phase correction means.
In accordance with this detection signal, the phase correction means performs the above-described phase correction only at the time of the B phase, and outputs a color difference signal after the phase correction shown in the waveform 21, and at the time of the A phase, the waveform 19
The supplied color difference signal shown in FIG. As apparent try than the waveform 19 and waveform 20, N-th of the center point of the data processing described above jitter when (FIGS during 4C _A, indicated by C _B ') is not corrected (figure C _A , are substantially the (8fscs) ^-1 is a phase difference of half of the) represented by C _B. That is,
The maximum (4fsc) ^-1 jitter has been reduced to (8fsc) ^-1 .

As described above, according to the above-described means, the color difference signal supplied to the encoder can be processed by the 4 fsc clock, and the jitter is within the allowable value of the maximum (8 fsc) ⁻¹ . For the sensor, digitization of signal processing including an encoder can be realized without deterioration of image quality.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a solid-state imaging device, 2 is an A / D converter, 3
Is a signal processing circuit for generating a luminance signal and a color signal, 4 is a data clock conversion circuit, 5 is a phase correction circuit, 6 is an encoder, 7 is a control circuit, 8 is a drive circuit, 9 is a synchronization signal generation circuit, and 10 and 11 Is a D / A converter. Hereinafter, the operation of the present embodiment will be described.

First, the synchronizing signal generation circuit 9 generates synchronizing signals (horizontal / vertical synchronization, subcarrier, clock, etc.) necessary for the signal processing circuit 3 drive circuit 8 and other circuits. In FIG. 1, pulses and the like necessary for processing of the signal processing circuit 3, the encoder 6, and the like are omitted because they are not directly necessary for the present description.
The drive circuit 8 reads a signal from the solid-state imaging device 1 in a sensor clock cycle (fs) in synchronization with the horizontal synchronization and the vertical synchronization supplied from the synchronization signal generation circuit 9. The sensor output read from the solid-state imaging device 1 is supplied to the A / D converter 2. The A / D converter 2 converts the sensor output signal into a digital signal for each pixel in synchronization with the sensor clock, and supplies the digital signal to the signal processing circuit 3. In the signal processing circuit, for example, based on a sensor clock, a processing is performed on the basis of a sensor clock from an A / D-converted digital sensor output signal supplied from the A / D converter by the processing discussed in the above-mentioned known example: Japanese Patent Publication No. 63-45153 To generate and output a luminance signal and a color difference signal. The color difference signals (RY) and (BY) thus generated are supplied to the data clock conversion circuit 4. In the control circuit 7,
In the same manner as the control means described above, the signal processing circuit 3 generates a data latch clock, a phase reference signal, and a synchronization signal from a phase reference signal (for example, a latch clock of a color difference signal as described above) representing a change point of the color difference signal. The phase with the 4fsc clock supplied from the circuit is detected with (8fsc) ^-1 accuracy,
The data latch clock is supplied to the data clock conversion circuit 4 and the phase correction circuit 5, and the phase detection signal is supplied to the phase correction circuit 5. In the data latch clock, the color difference signals (RY) and (BY) supplied from the signal processing circuit
Is latched by the data latch clock supplied from the control circuit 7, and the latched color difference signals (RY) and (B-
Y) is supplied to the phase correction circuit 5. The phase correction circuit 5 corrects the phase of the chrominance signal in the same manner as the above-described phase correction means, and outputs the chrominance signal (R-Y) after the phase correction to the encoder.
And (BY) are supplied to the encoder 6. As described above, the data clock conversion circuit 4, the control circuit 7, and the phase correction circuit 5
Correspond to the data clock conversion means, the control means, and the phase correction means, respectively, and perform exactly the same processing.
As a result, in the present example, similarly to the case of using a sensor having an arbitrary number of pixels, the jitter accompanying the data clock conversion of the chrominance signals (RY) and (BY) supplied to the encoder is also described. (8fsc) ^-1 or less. In the encoder 6, the supplied color difference signal (RY)
And (BY) are subjected to balanced modulation processing by the 4fsc clock and the fsc clock supplied from the synchronization signal generation circuit. The modulated chrominance signal obtained by the above processing and the luminance signal generated by the signal processing circuit 3 are D / A conversion circuits 11 and 10, respectively.
To supply. The D / A conversion circuits 10 and 11 convert the supplied luminance signal and modulated chrominance signal into analog signals and output the analog signals. However, when the luminance signal and the modulated chrominance signal are processed in a digital signal state, the D / A converters 10 and 11 are not necessary.

As described above, in the present example, the signal processing including the encoder can be digitized, and when the sensor having an arbitrary number of pixels is used, the jitter generated in the encoder can be suppressed to (8fsc) ^−1, and the image quality change due to the jitter can be reduced. Can be prevented.

FIG. 3 shows a configuration example of the data clock conversion circuit 4, the phase correction circuit, and the control circuit. FIG. 4 shows waveforms at various points in FIG. 4, and the sensor clock is fs (4fsc) × (2/3), as in the case described in the above operation. Assume that the phase reference signal coincides with the edge of the 4fsc clock and the jitter amount is maximized.
Further, the data cycle of the color difference signals (RY) and (BY) is also equal to 1/2 of the sensor clock: fs, as in the above-described example.
And In FIG. 3, the data clock conversion circuit 4 is constituted by latch circuits 22 and 23, the phase correction circuit 5 is constituted by latch circuits 30 and 31, addition circuits 32 and 33, and coefficient circuits 34 and 3.
5, Multiplexers 36 and 37, DFF (D flip-flop)
The control circuit 7 comprises DFFs 24, 25, 26, 27 and 28 and an inverter 29, respectively. Also, in FIG.
13 is the phase reference signal, and waveform 14 is the i-th (RY) and (B)
−Y) together with a waveform representing the data sequence represented as Di
Reference numeral 15 denotes a 4fsc clock whose phase rises slightly ahead of the rise of the phase reference signal 13 (referred to as an A phase as in FIG. 2).
The waveform 16 is a 4fsc clock whose rising edge is slightly delayed from the rising edge of the phase reference signal (referred to as B phase). These waveforms are the same as those described in FIG. 2, and are denoted by the same reference numerals as those in FIG. 4, the same waveforms as those in FIG. 2 are given the same numbers. Hereinafter, other waveforms will be sequentially described while describing the operation.

First, the phase reference signal and the 4fsc clock are supplied to the control circuit 7. The control circuit 7 latches the supplied phase reference signal (waveform 13 in FIG. 4) twice at the rising edge of the 4fsc clock by DFFs 24 and 25, and twice at the falling edge by DFFs 26 and 27. As a result, the waveforms 17 (A phase), 18 (B phase), and 50 waveform are output to the Q outputs of DFF25 and DFF26, respectively.
(A phase) and the waveform 51 (B phase) are obtained. This DFF25
Is supplied to the data clock conversion circuit 4 and the phase correction circuit 5 as a data latch clock. Meanwhile, DF
The Q output of F26 is further latched at DFF28 by the Q output of DFF25. The Q output of DFF28 has a waveform 5 in the A phase.
2 and the waveform 53 is output in the B phase. Therefore, depending on whether the Q output of DFF28 is “L” or “H”, the rise of the phase reference signal is in the “H” period of the 4fsc clock (a in the figure).
Or during the 'L' period. This is the above-described phase detection. The Q output of DFF28 is supplied to the phase correction circuit 5 as a phase detection signal.

In the data clock conversion circuit, the color difference signals (RY) and (BY) shown by the waveform 14 are respectively latched by the data latch clock supplied from the control circuit 7.
And latch by the latch circuit 23. The latch circuits 22 and 23 are provided with, for example, color difference signals (RY) and (B
-Y). The waveform 19 (A phase) or the waveform (B phase) is output to the outputs of the latch circuits 22 and 23. This output signal is supplied to the phase correction circuit 5.

In the phase correction circuit, the data clock conversion circuit 4
The color difference signals (RY) and (BY) supplied from
The data is latched by the latch circuits 30 and 31 with the data latch clock supplied from the control circuit 7. The latched color difference signals (RY) and (BY) are added to adders 32 and 33, respectively.
, The color difference signals (RY) and (BY) supplied from the data clock conversion circuit before the latch are added, and further, the signal coefficient circuits 34 and 35 obtained by the addition are added.
The color difference signal (D _i + D) at half the phase between D _i and D _{i + 1
i + 1} ) / 2 is generated and supplied to the multiplexers 36 and 37. The multiplexers 36 and 37 output the supplied color difference signal having the intermediate phase and the color difference signal supplied from the data clock conversion circuit according to the output signal of the AND gate 40. Here, it is assumed that when the output of the gate 40 is “H”, an intermediate-phase color difference signal is output. Meanwhile, DFF38 and NOR gate
A rising edge detection circuit 39 generates an edge signal which becomes 'H' for one cycle of the 4fsc clock immediately after the supplied data latch clock switches from 'L' to 'H'. I do. The AND gate converts this edge signal into
According to the phase detection signal supplied from the control circuit 7, the signal is supplied to the multiplexers 36 and 37 at the time of the B phase, and
Mask at the time. The output signal waveform of this AND gate is
FIG. 4 shows a waveform 54 (A phase) and a waveform 55 (B phase). As a result, the multiplexers 36 and 37 select and output the color difference signal of the intermediate phase only at the edge portion of the B phase, and output the color difference signal shown in the waveform 19 in the A phase and the color difference signal shown in the waveform 21 in the B phase. I do. These color difference signals are the color difference signals after the above-described jitter suppression.

FIG. 5 shows a configuration example of the NTSC system of the digital encoder 6. In FIG. 5, 58 and 59 are latch circuits, 62 and 63 are polarity inversion circuits, 60 and 61 are DFFs, 64
Is an addition circuit. Hereinafter, the operation will be described with reference to FIG. First, the color subcarrier fsc supplied from the synchronizing signal generation circuit 9 shown in FIG. 1 as shown in the waveform 66 is latched by the DFF 60 by the 4fsc clock shown in the waveform 65 also supplied from the synchronizing signal generation circuit 9. Waveform 67 is the resulting signal. Further, this signal is latched by the DFF 61 to obtain a signal shown by a waveform 68. Waveform 17 thus obtained
And the signal shown in the waveform 18 is a color subcarrier signal having a phase difference of 90 ° and is supplied to the polarity inverting circuits 62 and 63, respectively. In the polarity inversion circuits 62 and 63, the color difference signal after the jitter is suppressed by the above-described phase correction circuit is latched by the 4fsc clock (shown in waveforms 69 and 71).
When the signals supplied from DFF60 and DFF61 are “L”, the polarity is inverted and the signals shown in waveforms 70 and 71 are output. Waveform
The signals 70 and 71 are signals modulated by subcarriers having a phase difference of 90 °, respectively.
The two signals are added by the adder circuit 64 to obtain a color signal subjected to quadrature balanced modulation. Although the case of the NTSC system has been described above, also in the case of the PAL system, the line ID is input to the polarity inversion circuit 62, and for each line, the polarity is inverted when the subcarrier is 'H', or the 'L' If it is switched at any time, quadrature balanced modulation can be performed by the same configuration.

FIG. 7 shows another embodiment of the present invention. Portions performing the same operations as those in the above-described embodiment are denoted by the same reference numerals. In the present embodiment, a change point of the color difference signal is detected with an accuracy of (16 fsc) ^-1 by using the 8 fsc clock and the 4 fsc clock, and the phase is corrected. As a result, the jitter also becomes (16fsc) ^-1 or less. Although the maximum frequency of the clock is doubled and the power consumption of the oscillator increases, the data processing is performed at a maximum of 4 fsc, so that the power consumption in the data processing is equal to that of the above-described embodiment. In this embodiment, basically, only the phase correction section is different from the above-described embodiment, and therefore, this phase correction will be described with reference to FIG.

First, in the control circuit, one cycle of the 4fsc clock
The range where the change point (rising phase of the phase reference signal) of the color difference signal changes is detected in equal ranges. Each of the four equally divided phase ranges is represented by a, b, c, and d in FIG. 8, and A represents a case where the rise of the reference phase is at a, b, c, and d, respectively.
The phases are called phase, B phase, C phase, and D phase. Waveform 73 and 74, Waveform 74 and Waveform 75, Waveform 76 and Waveform 77 and Waveform 78 and Waveform
Reference numeral 79 denotes a 4 fsc clock and an 8 fsc clock for the A phase, the B phase, the C phase, and the D phase, respectively. Waveforms 80, 81, 82, and 83 are data latch clocks, each phase data being generated by latching the phase reference signal B at the rising edge of 8 fsc and then latching it at the rising edge of 4 fsc. This is a latch clock. For these data latch clocks, the A phase is (16 fsc) ^{-1 with} respect to the D phase,
Also, 2 (16fsc) ^{-1 in} the B phase and 3 (16fsc) in the C phase
sc) The phase is advanced by ^-1 . Therefore, the color difference signal latched by the data latch clock in the data clock conversion circuit 4 has the above-described phase shift in each phase. In the phase correction circuit 56, based on the color difference signals (D _i−1 , D _i ) supplied from the conversion circuit 4, Of the intermediate phase of the color difference signal
The data of the above-mentioned intermediate phase are respectively stored in A for only one cycle.
Output during phase, B phase, C phase, waveform 84, waveform 85, waveform 8
6, Obtain waveform 87. As a result, the center of each output signal is C _A , C in the figure.
_A coincident phase shift occurs as shown by _B , C _C , and C _D. That is,
According to the present embodiment, the jitter correction can be performed with high accuracy of (16 fsc) ^-1 even though the data processing is performed at 4 fsc.

〔The invention's effect〕

According to the present invention, in a video camera using a sensor having an arbitrary number of pixels, jitter that occurs in principle in a digital encoder based on a 4 fsc clock can be suppressed to an allowable value of (8 fsc) ⁻¹ , and an encoder is included. All signal processing systems can be digitized without image quality deterioration, and a low power consumption, small size, light weight, and high image quality video camera can be realized by taking advantage of the digitization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms at various parts in FIG. 1, and FIG. 3 is a data clock conversion circuit, a phase correction circuit, and a control circuit in FIG. FIG. 4 is a block diagram showing a waveform of each part in FIG. 3, FIG. 5 is a block diagram showing a configuration example of an encoder, and FIG. 6 is a waveform chart showing a waveform of each part in FIG. , FIG.
FIG. 8 is a block diagram showing another embodiment of the present invention.
It is a waveform diagram which shows the waveform of a part of figure. DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... A / D converter, 3 ... Signal processing circuit, 4 ... Data clock conversion circuit, 5 ... Phase correction circuit, 6 ... Encoder, 7 ... Control circuit, 8 ... Drive circuit, 9 ... Synchronous signal generation circuit, 10/11 ... D / A conversion circuit.

Claims (3)

(57) [Claims] An output signal of a solid-state imaging device is converted into a digital signal in a signal readout cycle (fs), and the converted digital signal is digitally processed by an fs clock to generate a luminance signal and a color difference signal. In the video camera, a color difference signal generated based on the fs clock is input and latched by a data latch clock synchronized with a 4 fsc clock which is four times the frequency of the color subcarrier (fsc), thereby performing data clock conversion. Data clock conversion means (4) for performing; detecting and outputting a phase of a change point of the color difference signal generated based on the fs clock, and after a change point of the color difference signal generated based on the fs clock; 4fsc at stable point
A control means (7) for generating the data latch clock to be latched in synchronization with a clock; and a signal obtained before and after a signal change point is calculated from a data clock converted color difference signal output from the data clock means. A phase correction unit (5) that outputs a phase-corrected color difference signal by selecting and outputting a converted signal of the intermediate phase color difference signal and the input data clock according to the phase detection signal output from the control circuit. ) And; a color difference signal (for example, R
Modulating means (6) for quadrature balanced modulation of -Y and BY)
And an imaging device comprising: 2. The phase control circuit according to claim 1, wherein said control circuit includes detection means for detecting a change point of the color difference signal at (8fsc) ^-1 increments according to the rise and fall of a 4fsc clock. The correction circuit selectively outputs the average value of the signals before and after the change point of the color difference signal and the input signal in accordance with the (8fsc) ^-1 phase detection signal supplied from the detection means, thereby converting the signal after the phase correction. The imaging device according to claim 1, wherein the imaging device is configured to output the image. 3. The control circuit uses a 4fsc clock and an 8fsc clock, and includes a detecting means for detecting where a change point of the color difference signal is located in four phase ranges obtained by dividing one cycle of the 4fsc clock into four equal parts. The phase correction circuit according to claim 1 generates signals in three intermediate phases based on signals before and after the change point, and supplies the signals from detection means for detecting the four phases. 2. The imaging apparatus according to claim 1, wherein four signals of the three intermediate phases and the input signal are selectively output according to a phase detection signal to output a phase correction signal.