JP2675678B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device capable of controlling the number of high-speed vertical transfer stages by a control signal from an external device (microcomputer or the like) and at the same time controlling the phase of a color difference signal. .

[0002]

2. Description of the Related Art In recent years, development of video cameras and electronic still cameras using a solid-state image pickup device has been focused on their small size, light weight, high image quality, multi-functionality, and low price.
First, FIG. 4 shows a system configuration diagram of a conventional solid-state imaging device. This solid-state imaging device includes a solid-state imaging device 5, a drive signal generator 6, a signal processor 7, and an external device (here, a microcomputer) 9. The solid-state image sensor 5 includes a photoelectric conversion element 1, a vertical transfer unit 2, a horizontal transfer unit 3, and a signal charge detection unit 4.

A color difference signal recognition pulse (hereinafter abbreviated as FH2 pulse) is created by dividing a horizontal synchronizing signal (hereinafter abbreviated as HD) into 1/2 by a T flip-flop or the like. φ
V is a 4-phase vertical transfer pulse applied from the drive signal generator 6 to the solid-state imaging device 5, φH is a 2-phase horizontal transfer pulse similarly applied to the solid-state imaging device 5, and CP is a drive signal generator 6 from the external device 9. Transfer stage number control pulse given to
QP is a signal processing pulse sent from the drive signal generator 6 to the signal processor 7.

The timing of the FH2 pulse will be described below with reference to FIG. FIG. 5 shows the voltage waveform of each pulse in the vicinity of the vertical blanking period. (a) is a vertical synchronizing signal (hereinafter abbreviated as VD) of a television signal,
(b) shows HD and (c) shows FH2 pulse. (d) and (f) show a pulse (hereinafter, abbreviated as φV1 pulse) applied to the first gate among the four-phase pulses applied to the vertical transfer unit 2, and (d) shows after the charge pulse CHP. The waveform has no high-speed transfer pulse, and (f) shows the waveform having the high-speed transfer pulse HTP after the charge pulse CHP. TP is a normal transfer pulse. The FH2 pulse inverts the logic every time HD is input.

Then, whether the phase of the color difference signal generated from the signal charges output from the solid-state image pickup device 5 in each horizontal scanning period is 2R-G or 2B-G is recognized by the logic of the FH2 pulse, and the signal processing unit 7 is operated. Color processing is carried out, and this is combined with the luminance signal and the synchronizing signal to create a color television signal.

[0006]

However, in the above-mentioned structure, an odd number of high-speed vertical transfer pulses are generated by the solid-state image pickup device in response to the vertical transfer stage number control signal CP from the external device 9 in the image stabilization function or electronic zoom. When applied to 5, the color difference signals are out of phase. An object of the present invention is to provide a solid-state imaging device that can always maintain a proper relationship between the phase of a color difference signal and the logic of a pulse for recognizing the phase of the color difference signal, regardless of whether the number of high-speed transfer stages in the vertical direction is odd or even. That is.

[0007]

According to the solid-state image pickup device of the present invention, the minimum number of transfer stages among the control signals consisting of a plurality of bits for controlling the number of high-speed transfer stages of the vertical transfer unit which is input from the external device to the drive signal generating unit. There is provided a control unit for switching the logic of the pulse for recognizing the phase of the color difference signal according to the odd-even of the number of high-speed transfer stages and giving it to the signal processing unit by the logic of the bit indicating the.

[0008]

According to the structure of the present invention, the logic of the pulse for recognizing the phase of the color difference signal is switched according to the odd / even number of high-speed vertical transfer stages, so that the phase of the color difference signal is changed regardless of the odd / even number of the high-speed vertical transfer stages. It is possible to always maintain an appropriate relationship between and the logic of the pulse for recognizing the phase of the color difference signal.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of a solid-state imaging device according to an embodiment of the present invention. This solid-state imaging device is composed of a solid-state imaging device 5, a drive signal generation unit 6 of the solid-state imaging device 6, a signal processing unit 7, an FH2 control unit 8 and an external device (microcomputer) 9, and is different from the conventional example. Is that the FH2 control unit 8 is provided. The solid-state image sensor 5 includes a photoelectric conversion element 1, a vertical transfer unit 2, a horizontal transfer unit 3, and a signal charge detection unit 4.

FIG. 2 shows a configuration example of the FH2 pulse control circuit (FH2 control section 8) and the FH2 pulse creation circuit (drive signal generation section 6) in the embodiment of the present invention. Sum gate (hereinafter referred to as EX-O
(Abbreviated as R) 11. FIG. 3 is a voltage waveform of each pulse in each part near the vertical blanking period. In FIG. 3, (a) shows VD and (b) shows HD.
(c) and (e) show FH2 pulses, (c) is a waveform when high-speed transfer is not performed, and (e) is a waveform when high-speed transfer of an odd number of stages is performed. (d), (f) show φV1 pulse,
(d) When high-speed transfer is not performed (charge pulse CHP
(When there is no high-speed transfer pulse after), (f)
When performing high-speed transfer of an odd number of stages (charge pulse CHP
(When there is an odd number of high-speed transfer pulses HTP after). (g) shows a CCD output signal, (h) shows a luminance signal, (i), (j), (k) show color difference signals, and (l) shows a color television signal.

An external device (microcomputer) 9 sends to the drive signal generator 6 the number of vertical high-speed transfer stages immediately after the charge pulse CHP immediately before the charge pulse CHP by a transfer stage number control pulse CP consisting of 7-bit serial data. . Here, the number of high-speed transfer stages is 7 bits and the positive logic is 2
The bit indicating the minimum transfer stage number (1 stage) is the least significant bit (LSB).

In the case of (d), φ when the number of high-speed transfer stages is 0
The V1 pulse voltage waveform is shown. At this time, since the logic of the least significant bit (LSB) in the 7-bit serial data is also low (in the case of positive logic), the FH2 control unit 8 does not change the logic and the FH2 remains unchanged (see FIG. The logic (FH2 ') of c)) is input to the signal processing unit 7. on the other hand,
In the case of (f), φV when the number of high-speed transfer stages is n (n: odd number)
A 1-pulse voltage waveform is shown. At this time, since the logic of the least significant bit (LSB) in the 7-bit serial data is high, the FH2 pulse is logically changed by the FH2 control unit 8 and the reverse logic (FH2 ′) of FIG. 3 (e). ) Is input to the signal processing unit 7.

The output signal (FIG. 3 (g)) transferred by the vertical transfer pulse φV and output from the signal charge detector 4 is passed through a low pass filter to obtain a luminance signal (FIG. 3).
(h)). Further, by separately passing through a band pass filter and a color sampling circuit, a repeating color difference signal of 2R-G and 2B-G (FIG. 3 (i)) is obtained for each scanning line.

The color difference signal thus obtained is 1H.
The signals are passed through the delay line and passed through the 1H delay line, and signals not passed through the delay line are selected by the FH2 pulse to perform synchronization. For example, when the FH2 pulse is low, the 1H delay line output is connected to the 2B-G output, and the 1H delay before signal is connected to the 2R-G output. When the FH2 pulse is high, connect the 1H delay line output to the 2R-G output and
Connect the pre-H delay output to the 2B-G output.

In this way, the two output signals are simultaneously converted so that the color difference signals in the 2R-G and 2B-G directions are always output (see FIGS. 3 (j) and 3 (k)). This color difference signal is modulated, a luminance signal and a synchronizing signal are added, and a color television signal (FIG. 3 (l)) is created. As a result, the phase inversion of the color difference signals does not occur due to the shaking function by driving the solid-state image sensor 5 and the application of the odd-numbered high-speed vertical transfer pulses in the electronic zoom or the like.

In this embodiment, the T flip-flop 10
Although the circuit configuration example using the FX-OR gate 11 has been described, another logic circuit may be used. Further, in this embodiment, the interline transfer type CCD has been described, but it goes without saying that the same applies to CCDs having other storage units.

[0017]

According to the solid-state image pickup device of the present invention, the logic of the pulse for recognizing the phase of the color difference signal is switched according to the odd / even number of stages of vertical high speed transfer. The relationship between the phase of the color difference signal and the logic of the pulse for recognizing the phase of the color difference signal can always be maintained properly.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a drive signal generator and an FH2 pulse controller in this embodiment.

3 is an example of a synchronizing signal for a television signal in the vicinity of a vertical blanking period in the solid-state imaging device of FIG. 1, a driving pulse of an FH2 pulse and a solid-state imaging device, and various signal voltage waveforms in a signal processing unit. It is a timing chart shown.

FIG. 4 is a system configuration diagram of an example of a conventional solid-state imaging device.

5 is a timing chart showing an example of a sync signal for a television signal, an FH2 pulse, and a drive pulse of a solid-state image pickup device in the solid-state image pickup device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element 2 Vertical transfer part 3 Horizontal transfer part 4 Charge detection part 5 Solid-state image sensor 6 Drive signal generation part 7 Signal processing part 8 FH2 control part 9 Microcomputer 10 T flip-flop 11 EX-OR gate

Claims (1)

(57) [Claims] 1. A photoelectric conversion unit having a plurality of photoelectric conversion elements arranged two-dimensionally, a vertical transfer unit for vertically transferring signal charges accumulated in the photoelectric conversion unit, and a transfer from the vertical transfer unit. Solid-state image pickup device having a horizontal transfer section for horizontally transferring the signal charge to be generated, and a signal charge detection section for converting the signal charge from the horizontal transfer section into a signal voltage or a signal current and outputting the signal voltage or the signal current; A drive signal generating section for generating a signal for driving the element, a signal processing section for generating a color television signal based on an output signal of the solid-state image pickup element, and the drive signal generating section from an external device during a vertical blanking period. The phase of the color difference signal according to the odd / even of the number of high-speed transfer stages by the logic of the bit indicating the minimum number of transfer stages in the control signal consisting of a plurality of bits for controlling the number of high-speed transfer stages of the vertical transfer unit that is input to A solid-state imaging device including: a control unit that switches the logic of a pulse for recognizing a signal and supplies the pulse to the signal processing unit.