JP2819944B2 - Video signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal generator suitable for use in inspection or evaluation of a television receiver or the like.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional video signal generating apparatus using digital processing.

[0003] In FIG. 6, 60 denotes an input terminal of the clock Nf _H, 61 is an address counter, 62 a memory, 63 a D / A converter, 64 is a low pass filter (LPF), 6
5 is a buffer, and 66 is an output terminal of a video signal.

A video signal for one scanning line is stored in a memory 62,
Direct digital data quantized is written at the timing of the clock Nf _H. Simultaneously reading the digital data by a counter 61 at the timing of the clock Nf _H, it is converted into an analog signal by a D / A converter 63, a video signal having a harmonic component as shown in FIG. When unnecessary harmonic components are removed from the video signal by the low-pass filter 64, a smooth video signal is obtained from the output terminal 66.

[0005]

If the output position of only the burst signal is made variable in the video signal generator, it is effective for evaluating the color reproduction system of the television receiver. However, in the above-described conventional video signal generating apparatus, since the synchronizing signal, the luminance signal, the burst signal, and the chrominance signal constituting one scanning line are all stored in the memory 62 as digital data in a combined state,
If the output position of only the burst signal is to be varied, it is necessary to prepare individual video signal digital data corresponding to each position, and there is a problem that an increase in memory capacity cannot be avoided.

The present invention solves such a conventional problem. The output position of the burst signal can be shifted without preparing new video signal digital data. It is an object of the present invention to provide a video signal generating device capable of preventing the image signal from being generated.

[0007]

The technical means of the present invention for achieving the above object is to convert a video signal into a luminance signal, a synchronization signal, two color difference signals orthogonal to each other, and two color subcarrier signals orthogonal to each other. Storage means for storing digital data obtained by quantizing these signals with a clock, and timing for reading out the digital data of the luminance signal and the two color difference signals, only when the two color difference signal digital data are within the horizontal blanking period. An address control unit for controlling to shift the digital signal, a means for processing the output digital data, the synchronous signal and the digital data of the two color subcarrier signals output at a fixed timing, And a D / A converter for converting the digital data into an analog signal.

The address control section includes horizontal address generating means for reading out digital data of a luminance signal and two color difference signals at clock timing, and outputs a horizontal address corresponding to the two color difference signal digital data to a burst position control value. To control the shift so that the shift is performed only within the horizontal blanking period.

The arithmetic processing means multiplies one of the color difference signal digital data and the color subcarrier signal digital data, and multiplies the other color difference signal digital data by the color subcarrier signal digital data. And a means for adding the two modulated wave digital data, and adding the luminance signal digital data and the synchronization signal digital data to the addition result.

[0010]

Therefore, according to the present invention, the color subcarrier digital data read at a fixed timing is
Since the read timing of the color difference signal digital data in the horizontal blanking period is controlled, the burst position can be shifted without preparing new digital data. In this case, the SCH phase can be fixed regardless of the position shift.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing a video signal generator according to one embodiment of the present invention.

[0013] In FIG. 1, 1 is a memory which holds luminance signal digital data D _Y quantized in clock Nf _H synchronized with the line frequency f _H (N = integer), 2 and 3
Memory held by two mutually orthogonal quantized in clock Nf _H synchronized with the line frequency f _H RY and BY color difference signals digital data D _RY and D _BY, respectively, the 4 line frequency f _H Synchronized clock Nf _H
The memories 5 and 6 which hold the synchronization signal digital data D _S quantized by the above are color co-carrier signal digital data D cos and two cos θ and sin θ orthogonal to each other, quantized by the clock Nf _H synchronized with the line frequency f _H. Dsin is stored in each memory, 7 is memories 1, 2,
3 is an address control unit that controls the timing of reading digital data held by 3 so that the two color difference signal digital data D _RY and D _BY are shifted only within the horizontal blanking period. 8 is held by the memories 4, 5 and 6 counter for reading digital data at a fixed timing clock Nf _H, 9 is a digital multiplier, the memory 2
The color difference signal read from the digital data D _RY and read from the memory 5 the color subcarrier signal digital data Dcos multiplies, read from the color difference signals read out from the memory 3 the digital data D _BY a memory 6 The digital data Dsin is multiplied by the obtained color subcarrier signal digital data to obtain RY modulated wave digital data and BY modulated wave digital data, respectively. 10a is R-Y and B-Y digital adder for adding the modulated wave digital data, 10b synchronization signal read from the luminance signal digital data D _Y and the memory 4 is read from the memory 1 to the addition result Digital adder for adding digital data, 1
1 is a D / A converter for converting the result of addition by the digital adder 10b into an analog signal, 12 is a low-pass filter (LPF), 13 is a buffer, and 14 is an output terminal of the analog video signal.

FIG. 2 shows an example of the address control unit 4. 2, 20 is a counter that operates at a clock Nf _H, 21 is a digital comparator, 22 is a data selector, 23 is an AND gate, 24 inverting gate, 25 of the read address for the memory 1, 2 and 3 in Figure 1 Output end.

The select signal input to the S input of the data selector 22 is

[0016]

[Outside 1]

The two signals input to the AND gate 23 are respectively

[0018]

[Outside 2]

[0019]

[0020]

[Outside 3]

It is assumed that The three signals (external 1), (external 2) and (external 3) will be described with reference to the timing chart shown in FIG.

As shown in FIG. 3, the signal (the outer 2) in the start timing of one line, a signal such that one period L _O clock Nf _H.

The signal (the outer 3) ends the horizontal blanking period, at the timing when the effective video period is started, a signal such that one period L _O clock Nf _H.

The signal (1) is a signal from the falling timing of the signal (2) to the falling timing of the signal (3), that is, a horizontal blanking period L _O.

Next, the operation of the address control unit 4 shown in FIG. 2 will be described with reference to the timing chart shown in FIG.

The clock Nf _H divides one line into N intervals. Now, it is assumed that the horizontal blanking period corresponds to an interval of a number. In the data selector 22, a burst position control value "b" is given to the A input and a value "a" is given to the B input from the beginning. During the horizontal blanking period,
Since the signal (external 1) is L _O , the data selector 22 outputs the burst position control value “b” given to the A input and supplies it to the counter 20. AND gate 23 at the start of the horizontal blanking period, and outputs the one period L _O clock Nf _H by a signal (out 2). This signal is applied to the load input of the counter 20 for counting up at the timing of the clock Nf _H, the counter 20 at the timing shown in FIG. 4 (A) captures the burst position control value "b", and outputs this.

FIG. 4A shows the output states of the data selector 22 and the counter 20 when "b" = 0. Counter 20 will sequentially well counted up thereafter, its output when the signal (outer 3) becomes L _O becomes "a-1". The digital comparator 21 normally outputs L _O as the comparison output at this timing, but Hi as a result of inverting the signal (3) by the inverting gate 24 is the enable terminal.

[0028]

[Outside 4]

As a result, the comparison output remains Hi. As a result, the counter 20 is not cleared and is placed in the load state by the signal (outside 3). At this timing, since the signal (external 1) is at Hi, the data selector 22 outputs the value “a”. Therefore, the counter 20 takes in the value "a" at the timing shown in FIG. 4B and outputs it.

FIG. 4A shows the output state of the data selector 22 and the counter 20 when the burst position control value "b" = 3. Counter 2
0 counts up from "3" at the timing of (A), the "a-1" reaches, for turn signal at that timing (outer 3) is Hi, the comparator 21 compares the output and L _O , The counter 20 is cleared. Thereafter, the counter 20 counts up to "1" and "2" during the horizontal blanking period, and outputs (a) again at the timing of (B) in FIG.

From the above operation, only the address corresponding to the horizontal blanking period is shifted to the output terminal 25 by the burst position control value, and the address is output in such a state that it does not shift during the effective video period. . When such a horizontal address is supplied from the output terminal 25 to the memories 1, 2 and 3 of FIG. 1, the memories 2 and 3 output the color difference signal digital data D _RY ,
Only D _BY is output in a state shifted to the left as the burst position control value “b” increases in the positive direction. On the other hand, since the memory 1 has the same data that does not change at all during the horizontal blanking period,
There is no effect of the burst position control. FIG. 5 shows an analog manner in which the digital data output from the memories 1, 2, and 3 is changed by the burst position control as described above.

The thus obtained color difference signal digital data D _RY, D _BY and, fixed output from the memory 5 and 7 by a counter 8 for the read operation at a clock Nf _H color subcarrier digital data Dcos, Dsin , The following operation is performed by the multiplier 9 and the adder 10a.

E _C = (D _BY ) × (D sin) + (D _RY ) × (D cos) The color signal digital data E _C obtained by such an operation
Contrast, luminance signal digital data D _Y and the synchronization signal digital data D _S is outputted from the memory 1 and the memory 5 are added by an adder 10b, the video signal the digital data is formed. This video signal digital data is converted into an analog signal by the D / A converter 11 and unnecessary high frequency components are removed by the low-pass filter 12, whereby a smooth video signal is obtained at the output terminal 14.

When the burst position control value “b” is 0 ≦ b
By setting a value in the range of ≦ a−1, the output terminal 14
The video signal obtained from
/ Nf _H [s] can be shifted left and right.

[0035]

As described above, according to the present invention, a video signal is decomposed into a luminance signal, a synchronizing signal, two mutually orthogonal color difference signals and two mutually orthogonal color subcarrier signals, and these are separated into digital data. Since the read position of the digital data of the two color difference signals among the digital data is shifted and controlled only within the horizontal blanking period, the output position of the burst signal is varied. It is not necessary to separately prepare video signal digital data corresponding to each position. Further, since the color difference signal digital data is shifted with respect to the fixed color subcarrier digital data, the burst position can be controlled without changing the SCH phase. Since it is not necessary to separately prepare video signal digital data corresponding to each position as described above, it is possible to prevent an increase in memory capacity.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a video signal generation device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an address control unit used in the video signal generator.

FIG. 3 is a timing chart of signals for operation of the address control unit.

FIG. 4 is a timing chart for explaining the operation of the address control unit;

FIG. 5 is an explanatory diagram analogously showing a state in which a luminance signal and a chrominance signal output from a memory in a video signal generating device according to an embodiment of the present invention are changed by burst position control.

FIG. 6 is a schematic block diagram showing a conventional video signal generator.

FIG. 7 is an explanatory diagram of an analog signal that has been D / A converted by the video signal generator.

[Explanation of symbols]

 1 Memory 2 Memory 3 Memory 4 Memory 5 Memory 6 Memory 7 Address Control Unit 8 Counter 9 Digital Multiplier 10a Digital Adder 10b Digital Adder 11 Converter 12 Low-Pass Filter 13 Buffer 14 Video Signal Output Terminal 21 Digital Comparator 22 Data Selector 23 AND gate 24 Inverting gate 25 Horizontal address output terminal

Claims (3)

(57) [Claims] A storage means for decomposing a video signal into a luminance signal, a synchronizing signal, two mutually orthogonal color difference signals, and two mutually orthogonal color subcarrier signals, and storing digital data obtained by quantizing these signals with a clock. An address control unit for controlling the timing of reading the digital data of the luminance signal and the two color difference signals so that the two color difference signal digital data are shifted only within the horizontal blanking period; Means for processing digital data of the synchronizing signal and two color subcarrier signals output at a fixed timing, and a D / A converter for converting the digital data after the processing to an analog signal Signal generator. 2. An address control unit comprising: a horizontal address generating means for reading out digital data of a luminance signal and two color difference signals at a clock timing; and a horizontal address for the two color difference signal digital data and a burst position control value. 2. The apparatus according to claim 1, wherein the control is performed such that the shift is performed only within the horizontal blanking period.
The video signal generator according to the above. 3. An arithmetic processing means multiplies one color difference signal digital data by a color subcarrier signal digital data, multiplies the other color difference signal digital data by a color subcarrier signal digital data, and modulates the modulated wave digital data respectively. 3. The video signal generating apparatus according to claim 1, further comprising: a multiplying means for obtaining the digital data, and a means for adding the digital data of the two modulated waves and adding digital data of the luminance signal and digital data of the synchronizing signal to the addition result.