JPH05199547A - Digital camera - Google Patents

Abstract

PURPOSE:To obtain an image of 3:4 by applying the digital processing to the video signal received from an image pickup part for a wide EDTV having an aspect ratio of 9:16. CONSTITUTION:A CCD imaging device 1 photographs a wide screen, and the video signal is outputted and undergoes the black shading correction, etc., at an analog video signal processing part 2. Then the video signal is converted into a digital signal by an A/D converter 3 with use of a clock CLK1 of 8fs and then undergoes the digital processing of the dither correction, the detail correction, etc., with the clock CLK1 through a digital video signal processing part 4. The switches 9 and 10 decide the intervention or the bypass of a video signal storage part 5. Both switched 9 and 10 are set at A and the read clock of the part 5 is set at 3/4 6fs of a write clock. Thus an image of an aspect ratio 3:4 is obtained from an image of 9:16. Meanwhile an image of an aspect ratio 9:16 is obtained when the switches 9 and 10 are set at B and with the bypass of the part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television type digital camera having a wide screen.

[0002]

2. Description of the Related Art In recent years, a television system has been reviewed, and a television system in which the aspect ratio of the screen is widened from the standard 3: 4 to 9:16, for example, the number of scanning lines remains the standard 525. A method of widening the screen in the horizontal direction (wide EDTV) and a method of widening the screen by setting the number of scanning lines to 1125 have been proposed.

Image signal processing devices compatible with these television systems include image pickup devices and display devices for HDTV and wide EDTV. Of these, the HDTV type image pickup device and display device are new systems that are completely different from the standard system, and thus are not widely used and expensive. On the other hand, a processing circuit of a standard television system video signal processing device can be used for an image pickup device and a display device of a wide EDTV. However, since the aspect ratio of these imaging devices is 9:16, an image with an aspect ratio of 3: 4 cannot be obtained. Therefore, an imaging device with an aspect ratio of 9:16 and 3: 4
Imagers must be manufactured individually. Moreover, from the user's point of view, although the wide EDTV and the standard television video signal processing device are almost the same, they are required separately from the standard video signal processing device to adopt the wide EDTV. There is
It is inefficient.

[0004]

SUMMARY OF THE INVENTION In the above conventional one,
By adding a device for obtaining a standard television 3: 4 image from a wide EDTV image pickup device, it is possible to add a wide EDTV image pickup device without producing individual image pickup devices and video signal processing devices. Even so, it is a useful device because it can be used together with a standard video signal processing device. However, from an image pickup device for a wide EDTV using a standard CCD as an image pickup element, an aspect ratio of 3:
The image of 4 cannot be taken out.

An object of the present invention is to provide a digital camera which can digitally process a video signal from an image pickup section for a wide EDTV having an aspect ratio of 9:16 to obtain a 3: 4 image. is there.

[0006]

A digital camera according to claim 1 is a CCD for R (red), G (green) and B (blue) having an aspect ratio of 9:16 driven by a first clock.
And an analog video signal processing unit for generating R, G, and B signals, an analog video signal processing unit for performing analog signal processing on the R, G, and B signals from the imaging unit, and an analog video signal processing unit with a first clock. And an analog-to-digital converter for digitally converting the R, G, and B signals processed in step 1, and a horizontal conversion into an R, G, and B signal digitally converted by a second clock that is an integral multiple or an integer fraction of the first clock, A line memory having a digital video signal processing unit that performs signal processing including vertical detail creation and a line memory, and the output signal from the digital video signal processing unit using the second clock as a writing clock in units of horizontal synchronization intervals. To the read start address, which is the start address of the line memory, and the read clock with the speed of 3/4 of the write clock. The video signal storage section that is read from the line memory with, the digital-analog converter that converts the output signal of the video signal storage section into an analog signal, and the output of the digital-analog converter as input, and the composite obtained by encoding this input An encoder for outputting a signal is provided, and a synchronizing signal given a delay time identical to the delay time of the signal generated in the video signal storage unit is added to the output signal of the video signal storage unit or the composite signal.

According to a second aspect of the present invention, there is provided a digital camera according to the first aspect, wherein the read clock in the video signal storage section is 3 / of the write clock.
The clock having the speed of 4 and the same clock as the write clock can be selected. The digital camera according to claim 3 is driven by the first clock 9: 1.
An image pickup section having CCDs for R (red), G (green) and B (blue) having an aspect ratio of 6, and generating R, G and B signals, and R, G and B signals from the image pickup section. An analog video signal processing unit that performs analog signal processing, an analog-digital converter that digitally converts the R, G, and B signals processed by the analog video signal processing unit at the first clock;
A digital video signal processing unit for performing signal processing including horizontal and vertical detail creation on R, G, B signals digitally converted by a second clock that is an integral multiple or a fraction of the clock of The output signal from the digital video signal processing unit is written to the line memory in units of horizontal synchronization intervals using the second clock as the write clock, and an arbitrary address of the line memory is read out and used as the start address, 3/4 of the write clock. A digital signal that converts the output signal of the video signal storage unit or the digital video signal processing unit from the video signal storage unit that reads from the line memory with a read clock with speed to analog
Input the output of the analog converter and the digital-analog converter to the encoder, which outputs the composite signal obtained by encoding this input, and the output signal of the digital video signal processing unit directly to the digital-analog converter A second mode for switching between a first mode for operating the digital video signal processing unit and a second mode for inputting the output signal of the digital video signal processing unit to the digital-to-analog converter via the video signal storage unit. At this time, a synchronizing signal having the same delay time as that of the signal generated in the video signal storage section is added to the output signal or the composite signal of the video signal storage section.

According to a fourth aspect of the present invention, there is provided the digital camera according to the first, second or third aspect, wherein the read start address of the line memory in the video signal storage unit is set to the center of the image portion of the write signal and the image of the read signal. It is characterized in that the center of the section is made to coincide.

[0009]

According to the structure of the present invention, the output signal of the digital video signal processing unit is written into the line memory of the video signal storage unit by using the second clock as a writing clock in units of horizontal synchronization intervals. By reading an arbitrary address as a start address and reading from the line memory with a read clock that has a speed of 3/4 of the write clock, after being converted to analog by the digital-analog converter, it is output as a composite signal from the encoder. , Aspect ratio is 3:
4 images can be obtained.

Furthermore, by setting the read clock in the video signal storage unit to be the same clock as the write clock, or by directly inputting the output signal of the digital video signal processing unit to the digital-analog converter, the aspect ratio can be improved. Images of 9:16 can be selected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a digital camera according to an embodiment of the present invention. In FIG. 1, 1 is an aspect ratio of 9: 1.
6 CCD image sensor, 2 analog video signal processing unit, 3
Is an analog / digital converter, 4 is a digital video signal processing unit, 5 is a video signal storage unit, 6 is a digital / analog converter, 7 is an encoder, 8 is a horizontal / vertical synchronizing signal / clock generating unit, 9, 10, 20 , 21 is a switch, 22 is a clock generator, and 27 is a lens that constitutes an image pickup unit together with the CCD image pickup device 1.

The CCD image pickup device 1 has a horizontal and vertical synchronizing signal
8fs generated by the clock generator 8 (fs = 3.579)
Clock CLK1 (first clock) of 545 MHz)
Is driven by. NTSC type CCD with 400,000 pixels
Then, R (red), G (green), and B (blue) each require a clock of 4 fs. By shifting the R and G timings by half a pixel, the high frequency resolution of the video signal can be increased. 8 fs is used as the reference clock for this purpose.

A wide-screen image is picked up by the CCD image pickup device 1 to output a video signal, and the analog video signal processing unit 2 performs double sampling, black shading correction, white shading correction and pre-gamma correction, and an 8 fs clock CLK1. The video signal is digitized by the analog-digital converter 3 driven by
Similarly, the digital video signal processing unit 4 driven by the clock CLK1 of 8 fs performs the dither correction, the gamma correction,
Digital processing of masking correction and detail correction is performed, and the RGB video signal is converted into a luminance signal Y and color difference signals I and Q in a matrix.

Next, inputting to the video signal storage unit 5 or bypassing the video signal storage unit 5 is selected by switches (mode switching means) 9 and 10. When the switches 9 and 10 are set to the A side, an image with an aspect ratio of 3: 4, and when set to the B side is 9 :.
Select 16 images. The write clock (second clock) of the video signal storage unit 5 is 8 fs, and by setting the read clock to 6 fs, which is 3/4 of the write clock, an image with an aspect ratio of 9:16 can be converted into a 3: 4 image. obtain. The video signal obtained here or the video signal bypassing the video signal storage unit 5 is converted into an analog video signal by the digital-analog converter 6, and the video signal and the horizontal and vertical synchronizing signals are converted into the composite video signal a by the encoder 7. ..

FIG. 2 shows the configuration of the horizontal / vertical synchronizing signal / clock generator 8. In this horizontal / vertical synchronization signal / clock generation unit 8, a clock CLK1 of 8 fs for driving the CCD image pickup device 1 and the like and a horizontal scanning frequency (about 15.734 kHz).
z) horizontal synchronizing signal H and vertical scanning frequency (about 59.94).
Vertical synchronizing signal V of (Hz) and a voltage controlled oscillator (VCO) 23 for generating a frequency of 8 fs and frequency dividers 24, 25,
26. In addition, VCO2
Select 3 and GEN LOCK.

FIG. 3 shows the internal structure of the video signal storage section 5 and the switches 9 and 10 for switching the video signals. Also,
FIG. 4 shows an internal image of the line memories 12 and 15 of the video signal storage unit 5. The switches 9 and 10 select whether the video signal is passed through the video signal storage unit 5 or bypassed. When the switches 9 and 10 are set to the B side and bypassed (first mode), the image of the composite video signal a has an aspect ratio of 9:16. When the switches 9 and 10 are set to the A side (second mode), the video signal is input to the line memories 12 and 15. The write address counters 11 and 14 of the line memories 12 and 15 are driven by the clock CLK1 of 8 fs which is the same as that of the CCD image pickup device 1 and the like, and the read address counters 13 and 16 are of the clock generator 2.
It is driven by a clock CLK2 of 6 fs generated by 2. The horizontal synchronizing signal H resets the write address counters 11 and 14 (R) and presets the read address counters 13 and 16 (PR).

In FIG. 4, is a start address, is an address to which the read address counters 13 and 16 are preset, and is a read address counter 1.
The address at which 3 and 16 are reset is the address at which one line written from the address by the write address counters 11 and 14 ends. As shown in FIG. 4, the preset value of the read address counters 13 and 16 is set to 2/16 of the count value of one line, and the drive clock CLK2 of the read address counters 13 and 16 is set to the drive clocks of the write counters 11 and 14. By setting FS to 3/4 of CLK1 for 6 fs, 3/4 line of one line of the wide EDTV can be taken out with the same center before reading from the preset value and re-preset by the horizontal synchronizing signal H. Further, since writing to and reading from the memory cannot be performed at the same time, two sets of write address counters 11 and 14, line memories 12 and 15, and read address counters 13 and 16 are set.
And the flip-flop 17 using the clock (CK) as the horizontal synchronization signal H allows the line memory 15 to be read when the line memory 12 is write-enabled.

In this way, a 3: 4 image can be obtained from an image with an aspect ratio of 9:16, but since the writing and reading of the line memories 12 and 15 can be delayed by one line, the synchronizing signal is also delayed. I have to let you. To deal with this, as shown in FIG.
And switches 20 and 21 that determine whether to bypass or bypass the delay circuit 18. When the switches 20 and 21 are set to the B side, an image with an aspect ratio of 9:16 is selected and A
The operations of the switches 9, 10, 20, and 21 are synchronized so as to select a 3: 4 image when turned to the side.

As described above, according to this embodiment, an image having an aspect ratio of 9:16 and an image having an aspect ratio of 3: 4 can be arbitrarily obtained by selecting the first mode and the second mode. .. As a result, by using the signal processing circuit and the LSI of the conventional standard television image pickup device, the wide EDT is used.
By configuring the signal processing device of the V image pickup device, the signal processing circuit and the LSI can be shared to reduce the development cost, and its practical effect is great.

Although the first clock and the second clock are the same in this embodiment, the second clock may be an integral multiple or a fraction of the first clock. Further, although the synchronizing signal given the same delay time as the delay time of the signal generated in the video signal storage unit 5 is added to the composite signal, it may be added to the output signal of the video signal storage unit 5. Good.

The switches 9 and 10 are used to select whether the video signal passes through or bypasses the video signal storage unit 5. However, in the video signal storage unit 5, an arbitrary address of the line memory is read out and the start address is read. As an alternative, the mode for reading the line memory with the read clock having a speed of 3/4 of the write clock and the mode for reading the line memory with the same clock as the write clock may be selectively switched.

Also, in order to add a synchronization signal, an external G
A sync signal generator may be provided which has an ENLOCK input and which generates a sync signal that precedes the external GENLOCK signal by the same delay time as the signal generated in the video signal storage section 5. Further, a mode for generating a synchronization signal that precedes the external GENLOCK signal by the same delay time as the signal delay time generated in the video signal storage unit 5, and the external GE
The NLOCK signal is provided with a mode for generating a synchronization signal having no time lag, and a first mode (image having an aspect ratio of 9:16) and a second mode (image having an aspect ratio of 3: 4) are provided. You may make it switch according to selection.

[0023]

According to the digital camera of the present invention, the output signal of the digital video signal processing unit is written into the line memory of the video signal storage unit by using the second clock as a writing clock in units of horizontal synchronization intervals. Read out from the line memory with a read clock having a speed of 3/4 of the write clock as the read start address and read as the start address, and after analog conversion by the digital-analog converter, output as a composite signal from the encoder. Thus, an image having an aspect ratio of 3: 4 can be obtained.

Furthermore, by setting the read clock in the video signal storage unit to be the same clock as the write clock or by directly inputting the output signal of the digital video signal processing unit to the digital-analog converter, the aspect ratio can be improved. Images of 9:16 can be selected. As a result, a signal processing circuit or LSI of a conventional standard television image pickup device is used to configure a signal processing device of an image pickup device for wide EDTV. It can be reduced, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a television camera according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a horizontal / vertical synchronizing signal / clock generating unit in the embodiment.

FIG. 3 is a diagram showing an internal configuration of a video signal storage unit and a switch for switching a video signal in the embodiment.

FIG. 4 is an image diagram of the inside of the line memory in the embodiment.

[Explanation of symbols]

 1 CCD image pickup device (image pickup unit) 2 analog video signal processing unit 3 analog / digital converter 4 digital video signal processing unit 5 video signal storage unit 6 digital / analog converter 7 encoder 8 horizontal / vertical synchronization signal / clock generation unit 9, 10 switch (mode switching means) 18 delay circuit 22 clock generation unit 27 lens (imaging unit)

Claims (4)

[Claims] 1. Driven by a first clock 9:16
Aspect ratio of R (red), G (green) and B (blue) C
An imaging unit that has a CD and generates R, G, and B signals, an analog video signal processing unit that performs analog signal processing on the R, G, and B signals from this imaging unit, and the analog with the first clock. An analog-to-digital converter that digitally converts the R, G, and B signals processed by the video signal processing unit, and the digitally converted R, G with a second clock that is an integral multiple or an integer fraction of the first clock. , A B signal has a digital video signal processing unit for performing signal processing including horizontal and vertical detail creation, and a line memory. An output signal from the digital video signal processing unit is used as the second clock as a write clock. Write to the line memory in units of horizontal synchronization intervals, read out any address of the line memory and write as the start address A video signal storage unit that reads out from the line memory with a read clock having a speed of 3/4 of the internal clock, a digital-analog converter that converts the output signal of the video signal storage unit into an analog signal, and the digital-analog converter And an encoder for outputting a composite signal obtained by encoding the input, and a synchronization signal to which the same delay time as the delay time of the signal generated in the video signal storage section is given, A digital camera adapted to be added to the output signal of the storage unit or the composite signal. 2. The digital camera according to claim 1, wherein a clock having a speed of 3/4 of a write clock and a clock same as the write clock can be selected as a read clock in the video signal storage section. 3. Driven by the first clock 9:16
Aspect ratio of R (red), G (green) and B (blue) C
An imaging unit that has a CD and generates R, G, and B signals, an analog video signal processing unit that performs analog signal processing on the R, G, and B signals from this imaging unit, and the analog with the first clock. An analog-to-digital converter that digitally converts the R, G, and B signals processed by the video signal processing unit, and the digitally converted R, G with a second clock that is an integral multiple or an integer fraction of the first clock. , A B signal has a digital video signal processing unit for performing signal processing including horizontal and vertical detail creation, and a line memory. An output signal from the digital video signal processing unit is used as the second clock as a write clock. Write to the line memory in units of horizontal synchronization intervals, read out any address of the line memory and write as the start address A video signal storage unit that reads out from the line memory with a read clock having a speed of 3/4 of the built-in clock; and a digital-analog converter that converts the output signal of the video signal storage unit or the digital video signal processing unit into an analog signal. An encoder that receives the output of the digital-analog converter as an input and outputs a composite signal obtained by encoding the input, and an output signal of the digital video signal processing unit is directly input to the digital-analog converter. A mode switching unit that switches between a first mode and a second mode in which an output signal of the digital video signal processing unit is input to the digital-analog converter via the video signal storage unit; In the mode 2, the synchronization signal is given the same delay time as that of the signal generated in the video signal storage section. Signal is added to the output signal of the video signal storage unit or the composite signal. 4. The read start address of the line memory in the video signal storage unit is set so that the center of the image portion of the write signal and the center of the image portion of the read signal coincide with each other. Or the digital camera described in 3.