JP2811647B2 - Digital color difference signal modulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for modulating a digital color difference signal of a television signal, and more particularly to a method suitable for use in a digital color encoder.

[0002]

2. Description of the Related Art FIG. 1 shows a signal processing system in a general recording / reproducing apparatus integrated with a camera in which a digital color encoder is used. Here, the image is photoelectrically converted and converted into a digital signal in an A / D (analog / digital) converter 2 at a sampling frequency of 3 fsc (fsc: color subcarrier frequency) or 4 fsc. The digitized signal is separated into a luminance signal and a chrominance signal in the process circuit system 3 or subjected to matrix processing or the like to be converted into two color difference signals, which are supplied to the encoder 4 where they are balanced-modulated. For example NT
The color signal of the SC system is used. (JP
No. 50-114123 and Japanese Patent Publication No. 58-715).

[0003]

The driving frequency of a camera using a solid-state image sensor changes according to the number of pixels. When digital signal processing is performed, sampling is performed at the same frequency as the driving frequency. . This sampling frequency is
In particular, this will affect the circuit configuration of the encoder at the time of modulation, and depending on the sampling frequency, a large number of multipliers, adders, etc. for performing calculations at the time of modulation must be prepared.
In some cases, the circuit configuration becomes very complicated. In this case, the circuit configuration can be simplified by setting the sampling frequency to an integral multiple of fsc. Especially, especially 4fsc
When the sampling is performed at the sampling frequency of, the most simplified configuration circuit is obtained. In this case, if a solid-state imaging device having 910 pixels in the horizontal direction is used, the sampling frequency becomes 4 fsc,
Although a simplified configuration can be achieved, the number of pixels increases and the cost becomes higher.

Recently, the number of pixels in the horizontal direction is 606, 80
8,858 solid-state imaging devices are widely available, and using such a number of pixels reduces the cost. However, as described above, the sampling frequency does not become an integral multiple of fsc and is extremely complicated. Circuit configuration. For example, when the number of pixels in the horizontal direction is 606, the sampling frequency is 606/910 fsc = 303/455 fsc, which is not an integral multiple of the chrominance subcarrier, and is 303 times during 455 periods of the chrominance subcarrier. A coefficient must be obtained for each of the points, and a computing unit such as a multiplier corresponding to the coefficient must be prepared.

Accordingly, when the sampling frequency is an integer multiple of fsc, the circuit configuration of the encoder can be simplified. However, when the sampling frequency is other than that, the phase of the sampling point increases extremely. Accordingly, arithmetic operations such as multiplication and addition increase, and the circuit becomes complicated. In addition, in order to support various sampling frequencies, circuits corresponding to the respective sampling frequencies are required, and there is a problem that the circuit is not versatile. Therefore, an object of the present invention is to solve the above problems.

[0006]

The system according to the present invention solves the following problems and has the following arrangement. In other words, in a modulation method of a digital color difference signal in which two digitized color difference signals are balanced and modulated to generate a modulated color signal, two color difference signals sampled at a sampling frequency other than four times the color subcarrier are used. The sampling frequency converter converts the chrominance subcarrier frequency to four times, and these two color difference signals are divided into four by the encoder.
A modulation method of a digital chrominance signal that performs arithmetic processing according to the phase of a chrominance subcarrier and generates a modulated chrominance signal, wherein the sampling frequency conversion means samples the chrominance signal as a first sample point sequence. The sample adjacent to each sample point of
Point obtained by multiplying 2 ⁿ (n: integer) by linear interpolation
When the sample point sequence is formed as a second sample point sequence, and when the color difference signal is sampled by a quadruple color subcarrier, each sample point sequence is a third sample point sequence, Of the sample points of the second sample point sequence closest to each sample point of the third sample point sequence among the sample points of the third sample point sequence, A modulation method of a digital color difference signal, wherein a sampling frequency is converted as a value of each sample point.

[0007]

The two color difference signals sampled at a sampling frequency other than four times the color subcarrier are converted to four times the color subcarrier frequency by the sampling frequency conversion means, and are balanced and modulated by the encoding means. Generate a color signal. In the sampling frequency conversion means, each sample point of the first sequence of sample points of the color difference signal is multiplied by 2 ⁿ (n: integer) by linear interpolation to obtain a second sample point.
Is formed. Then, when the sequence of each sample point when the chrominance signal is sampled by the quadruple color subcarrier is set as a third sample point sequence, the third sample point of the second sample point sequence is used. The value closest to each sample point in the sample point sequence is
Is adopted as the value of each sample point in the sample point sequence.

[0008]

An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a signal processing system in an imaging apparatus to which the present invention is applied, and a schematic configuration of the signal processing system will be described. In FIG. 1, reference numeral 11 denotes a solid-state image sensor, which has, for example, 606 pixels arranged in a horizontal direction. The imaging light from the subject is
1 and 606f corresponding to the number of pixels.
An image signal is sequentially taken out by a driving clock pulse of h (fh: horizontal synchronization frequency). The extracted image signal is supplied to an A / D (analog / digital) conversion circuit 12.
Thus, an analog signal is converted into a digital signal.

The digitized signal is separated into a luminance signal and a chrominance signal in a process circuit 13 at the next stage.
The luminance signal is output after being subjected to camera process signal processing, and the color signal is converted into a color difference signal (RY, BY) in a color signal processing system in the process circuit 13.
This color signal has a band of 500 KHZ to 1.5 KHz.
Since it is enough if the band of MHZ is secured,
In this color signal processing system, sampling data is thinned out,
The sampling frequency is （(3) of the driving frequency (606fh).
03fh: about 4.8 MHZ), which simplifies the circuit and saves power.

These color difference signals are supplied to a sampling frequency conversion circuit 14 which is a main component for achieving the method of the present invention.
a and b. These conversion circuits 14a,
In each of b, three data are interpolated between each sample point of the sampled color difference signal as described later,
The sampling frequency is raised to 4 × 303 fh, and the data closest to each sampling point of 4 fsc among the data of each interpolated sample is adopted as the data of each sampling point of 4 fsc. A color difference signal equivalent to that sampled at 4 fsc above is obtained. These color difference signals are supplied to the encoder 15 at the next stage, where the color difference signals RY and BY are modulated and output as color signals.

Hereinafter, the present invention will be described in more detail.
FIG. 2 is a diagram showing a relationship between each sampling frequency and a sampling point. The A / D converter 12 performs sampling at a timing shown in FIG. 2B (1212/455 × fsc:
The data sampled at 606fh) is output,
The luminance signal is removed in the process circuit 13 during this data. The color signal from which the luminance signal has been removed is further thinned out in the color signal system, and is sampled (sampled at 303fh) at the timing indicated by the black circle in FIG. 2C. A, B, C, D, E,... Indicate color difference signals sampled sequentially.

Here, these data are subjected to three data interpolations (data indicated by a triangle) with the next sampled data. For example, between data A and data B, data (3A + B) / 4 and data
(A + B) / 2 and data (A + 3B) / 4 are sequentially interpolated. Thereafter, data interpolation is similarly performed between the data of B, C, D, E. Further, of these data, the data closest to each sampling point of the sampling frequency 4fsc is adopted as the sampling data of the sampling frequency 4fsc. FIG.
(A) shows the sampling points of the sampling frequency 4fsc. Of the sampling data at the sampling frequency 303fh, the data closest to the first sampling point at the sampling frequency 4fsc is as follows. Data A,
This data is adopted as the data of the first sampling point of the sampling frequency 4fsc. The data of the subsequent second sampling point is data (3A + B) /
4 is the closest, and data (A + 3B) / 4 is the closest as the data of the third sample point. And the fourth
As the data at the second sampling point, data B is the closest. Thereafter, among the sampling data at the sampling frequency 303fh, the data closest to each sampling point at the sampling frequency 4fsc is adopted as the data at the sampling frequency 4fsc. I have.

Next, a specific configuration and operation of the sampling frequency conversion circuits 14a and 14b will be described with reference to FIGS. FIG. 3 is a circuit diagram of the sampling frequency conversion circuit 14a, and FIG. 4 is a timing chart in the circuit. Since the sampling frequency conversion circuit 14b has the same configuration as the sampling frequency conversion circuit 14a, the description is omitted. From the input terminal 20, a color difference signal RY sampled at the sampling frequency 303fh is input. For example, this signal is composed of data A, B,
., C, D, E, F... The incoming data A is input from a data input terminal D of a D-type flip-flop (hereinafter, simply referred to as DFF) 1. The input terminal on the other end side is connected to the input terminal as shown in FIG. 606f shown
When the clock pulse of h is supplied, the data A is latched and supplied to the data input terminal D of the next stage DFF2.
At the same time, the clock pulse is also supplied from the other input terminal of the DFF2, and the data A is output from the DFF2 after being delayed by two clocks. This data A is supplied to adders 21 and 22, respectively, and is input from data input terminals of DFF4 and DFF8. At this time, the data B has arrived at one side of the adder 21, where the data A and the data B are added. The added data is multiplied in a 1/2 multiplier 23 in the next stage, and supplied to data input terminals of DFF6 and DFF10, and also supplied to adders 22 and 25, respectively. .

In the adder 22, the data (A + B)
/ 2 and data A are added, and this data is added to the next stage.
The data is converted into data (3A + B) / 4 by a / 2 multiplier 24 and supplied to data input terminals D of DFF5 and DFF9, respectively. On the other hand, in the adder 25, the data B is supplied to one side thereof, where the data B and the data (A + B) / 2 are added. The added data is multiplied by a 1/2 multiplier 26 in the next stage to obtain data (A + 3B) / 4.
The data is input from the data input terminals of the FF11. The data B, C,.

Here, 606 is provided at one end of the frequency divider 27.
A clock pulse of fh is supplied, and a reset pulse is input to the input terminal R on the other end side from the input terminal 28 every horizontal synchronization period. Here, the incoming clock pulse is divided by four, and is generated as a latch pulse having timings as shown in FIGS. The latch pulse is input to the latch inputs of DFF4 and DFF5, and from the data input D side of FIG.
Data A and data (3A + B) shown in (g) and (h)
/ 4 is latched from the rising edge and latched until the next rising period. The latch pulse is data (A + B) / 2
And latching data (A + 3B) / 4, and the latch pulse latches incoming data B and data (3B + C) / 4 at this timing. The latch pulse is data (B + C) / 2 and data (B + 3C) / 4
Are respectively latched. Further, these latched data are sequentially supplied to the selector 29.

Next, switching of these data and data
The data interpolation method will be described with reference to Table 1. Table 1
Is a conversion table for explaining conversion processing performed in the decoder 30.

[0017]

[Table 1]

In the table, [Sampling frequency 303fh
The number shown in the column of [Data Position at Time] indicates the data position of the sampling data. For example, as shown in FIG. 2 (c), the position of data A is [0]. , Data [(3A +
B) / 4] is [1], data [(A + B) / 2]
Are sequentially determined from [2] to [1211]. The column of [Sampling Position at Sampling Frequency of 4 fsc] indicates the sampling position at which the data shown in FIG. 2 (c) is adopted as the data of the sampling position, and every 1/910 interval. The numbers are sequentially determined from [1] to [910]. The number shown in the column of [Addition result] is the data interval [1] of one section shown in FIG.
212/910 = 1.33] are sequentially added. This data interval [1.33] is shown in FIG.
Are data intervals when one data interval of each data shown in [1] is [1].

For example, at the top of Table 1, [Sampling position at sampling frequency 4 fsc] is [1],
[Addition result] is shown as [0], and [Data position at sampling frequency 303fh] is shown as [0]. This is because the data sampled at the sampling frequency 303fh
This means that the data at position [0] (data A) is adopted as data at sampling position [1] at a sampling frequency of 4 fsc. In the second row from the top row, the addition result is [1.33], but the data at the data position [1] is used as the sampling data at the sampling frequency 303fh. Will do. This is, of course, because the data [1.33] is closer to the data position [1] than the data position [2].
Means that the data is adopted as data at the sampling position [2] when sampling at a sampling frequency of 4 fsc.

Referring again to FIG. 3, a reset pulse is input from the input terminal 28 to the reset input R of the DFF 3 in accordance with the horizontal synchronization period, and a clock input from the input terminal 30 to the reset input R of 4fsc shown in FIG. A clock pulse arrives. At the time of the rising edge of the clock pulse, there is no input signal from the data input D of the DFF3, and the data [0] is output from the DFF3. The data [0] is supplied to the next-stage decoder 32, where the conversion processing described above is executed, and a switching signal for adopting the data at the sampling position [0] is supplied to the selector 29. As a result, the selector 29 is switched to the contact 1 to supply the data A to the data input D of the DFF 12.

Subsequently, the coefficient [1.33] is supplied to the data input D of the DFF 3 through the adder 31, and is latched at the rising edge of the incoming clock pulse.
3 and supplied to the decoder 32. In the decoder 32, the result is rounded off and converted as a coefficient [1], and a switching signal based on this signal is supplied to the selector 29. Based on this, the selector 29 is switched to the contact 2 and the data (3A + B) / 4 is transferred to the data of the DFF 12.
Data input D. On the other hand, the coefficient [1.33] fed back to the adder 33 is added here to the coefficient [1.33] that comes next, and is added to the coefficient [2.66].
Then, the coefficient is supplied to the decoder 32 through the DFF 3, where it is rounded off to [3], and a switching signal based on this is supplied to the selector 29. As a result, the selector 29 is switched to the contact 4 to supply data (A + 3B) / 4 to the data input D of the DFF 12. In this way, the coefficient [1.33] is
Are sequentially added up to [1210.67], and based on this, each contact of the selector 29 is sequentially and cyclically switched in accordance with the incoming position of the data, and 910 data corresponding to one horizontal scanning period are obtained. Data is taken out from the selector 29. Then, in the next horizontal synchronization period, a reset signal is input again from the input terminal 28, and the same operation as described above is repeated.

FIG. 5 is a block diagram of the encoder 15. The color difference signals RY and BY output from the sampling frequency conversion circuits 14a and 14b come from input terminals 15a and 15b, respectively. The color difference signal RY is applied to the contact 1, the color difference signal BY is applied to the contact 2, the color difference signal RY is inverted by the inverter 15 c to the contact 3, and [+1] is added in the adder 15 d. The contact 4 is supplied with the color difference signals BY which are inverted by the inverter 15e and added with [+1] in the adder 15f, and these signals are sequentially switched by the signal of the frequency 4fsc. N
It is extracted from the output terminal 15g as a modulated color signal that has been TSC-balanced modulated.

Therefore, according to the modulation method of this embodiment, the sampling frequency conversion circuits 14a and 14b temporarily convert the frequency to 4 fsc, so that the encoder 15 provided in the next stage has an inverter and a simple configuration. It is not necessary to specially prepare an arithmetic unit having a complicated configuration simply by preparing the adder of (1). Further, in the case of the present embodiment, the configuration in which the frequency is temporarily converted to 4 fsc has been described. However, the configuration may be such that the frequency is converted to 3 fsc, although the number of arithmetic circuits is increased. Further, in the present embodiment, the configuration is described in which the data is quadrupled and interpolation is performed. However, the interpolation number may be changed according to the number of pixels of the solid-state imaging device, and fsc
If the sampling frequency is 2 ⁿ (n: an integer) times the same, almost the same effect can be expected. In this case, the present invention can be applied to various solid-state imaging devices simply by changing the coefficient supplied to the adder 33. Furthermore, it goes without saying that the color difference signal modulation method according to the present embodiment can be applied not only to the NTSC method but also to the PAL method.

[0024]

According to the method of the present invention, encoding means
Can be applied to solid-state imaging devices having different numbers of pixels by simply changing the coefficients in the frequency conversion means, and it is possible to provide a versatile circuit.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a signal processing system in an imaging device to which the present invention is applied.

FIG. 2 is a diagram illustrating a relationship between each sampling frequency and a sampling point.

FIG. 3 is a circuit configuration diagram of a sampling frequency conversion circuit 14a.

FIG. 4 is a timing chart of a sampling frequency conversion circuit 14a.

FIG. 5 is a block diagram of the encoder 15;

FIG. 6 is a diagram illustrating a general example of a signal processing system of a recording / reproducing apparatus integrated with a camera.

[Explanation of symbols]

 Reference Signs List 11 solid-state imaging device 12 A / D (analog / digital) conversion circuit 13 process circuit 14a, b sampling frequency conversion circuit 15 encoder 15c, e inverter 15d, 15f, 21, 22, 25, 33 adder 23 , 24, 26 1/2 multiplier 274 frequency divider 29 selector 32 decoder

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mamoru Miyashita Examiner Masahiro Inui, Victor Company of Japan Victor Company, Ltd. 3--12 Moriyacho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture JP-A-62-143588 (JP, A) JP-A-2-292012 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 9/67 H04N 9/45 H04N 9 / 64 H04N 11/04

Claims (2)

(57) [Claims] 1. A method of modulating a digital color difference signal in which two digitized color difference signals are balanced and modulated to generate a modulated color signal, wherein two digital signals sampled at a sampling frequency other than four times the color subcarrier are used. The chrominance signal is converted to a four-fold chrominance subcarrier frequency by the sampling frequency conversion means, these two chrominance signals are divided into four by the encoding means, and arithmetic processing is performed according to the phase of the chrominance subcarrier and modulated. A modulation method of a digital color difference signal generated as a color signal, wherein the sampling frequency conversion means includes a marker adjacent to each sample point of the color difference signal sampled as a first sample point sequence.
This point is obtained by multiplying 2 ⁿ (n: integer) by linear interpolation.
The specimen point sequence formed as a second sample point sequence, when the sequence of the sample point when sampled at four times the color subcarrier of the chrominance signal and the third sampling point sequence, the first The value of the sample point of the second sample point sequence closest to each sample point of the third sample point sequence among the sample points of the second sample point sequence
A digital color difference signal modulation method, wherein a sampling frequency is converted as a value of each sample point of the sample point sequence. 2. The sampling frequency conversion means according to claim 1, wherein each sample point of the color difference signal sampled as the first sample point sequence is multiplied by 2 ⁿ (n: integer) by linear interpolation. When a second sample point sequence is formed and the color difference signal is sampled by a quadruple color subcarrier, each sample point sequence is a third sample point sequence. Of the sample points, the third
The value closest to each sample point in the sample point sequence of
A modulation method for a digital chrominance signal, wherein a sampling frequency is converted by using a value of each sample point of a third sample point sequence.