JPH0226403B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase modulator using a digital circuit, and in particular to a phase modulator using a digital circuit that provides sufficient characteristics even when the conversion speed of an analog-to-digital conversion circuit that converts an input analog signal into a digital signal is slow. Regarding phase modulators.

Conventionally known digital phase modulation circuits have the disadvantage that the speed of analog-to-digital conversion is slow, resulting in discontinuous phase modulation and deterioration of spectral characteristics such as generation of spurious signals. An object of the present invention is to provide a digital phase modulator that eliminates these drawbacks.

According to the present invention, the output digital value of an analog-to-digital conversion circuit that receives an analog signal and converts this signal into a digital value at a fixed cycle, and the accumulation circuit that adds a fixed value at every fixed cycle. A memory circuit is provided whose address is the output of the adder circuit that calculates the sum with the output, the output digital value of this memory circuit is converted to an analog value, and this converted output is input to a low-pass filter to obtain the value. In a digital phase modulator that outputs a signal, calculation is performed using the output digital value of the analog-to-digital conversion circuit at two or more different times, and the value within the sample period of the input analog signal is estimated. search interpolation circuit,
The above object can be achieved by providing it between the analog-digital conversion circuit and the addition circuit.

This will be explained in detail below using the drawings. FIG. 1 is a block diagram showing the configuration of a conventional digital phase modulator. The modulated input analog signal is converted into a digital value by the analog-to-digital converter 2 and then becomes one input of the adder circuit 3.
The output of device 5 for setting a constant value is at terminal 10.
The sum is added by the accumulator circuit 4 which adds the sum every clock cycle inputted from the clock signal, and becomes the other input of the adder circuit 3. The two inputs of the adder circuit 3 are in phase with the modulated input signal and the carrier signal, respectively. That is, if the phase of the modulated wave is θ _s (t), the modulated input signal is θ _i (t), and the phase of the carrier is θ _c (t), then θ _s (t _i )=θ _c (t _i ) +θ _i (t _i )...(1). Here, θ(t _i ) indicates a sample value of θ(t). Furthermore, since the phase is modulo 2π, the accumulation circuit and the addition circuit may perform calculations modulo a value corresponding to 2π. The memory circuit 6 outputs Asin(θ _s (t _i )) for the address θ _s (t _i ), and this output means that a sampled phase modulated wave is obtained. Here, A is a constant.
This output is converted into an analog quantity by digital-to-analog conversion, and then passed through a low-pass filter 8 to become a temporally continuous signal.

FIG. 2 shows the input and output of the adder circuit 3 on the assumption that the modulated input signal increases linearly to simplify the explanation. In the figure, black circles indicate values sampled over time. Straight lines shown in FIG. 21 and 22 indicate the modulation input and carrier wave phases, respectively. When the phase of the carrier wave and the modulation input are sampled at the same period, the output of the adder circuit becomes linear as shown in FIG. 23, and there is no problem. At this time, the digital value of the sine wave is determined by the storage circuit 6, and the output is as shown in FIG. 2B. When the sample period of the carrier wave phase is made faster than the sample period of the modulation input signal, the points 22 and 23 in the same figure change as shown by the arrows, so the signal that has passed through the low-pass filter 8 becomes ideal. In this case, the frequency will not be a single frequency, and spurious components will be generated. Such a problem can be solved by making the period for sampling the phase of the carrier wave the same as the sampling period of the input signal. However, this sampling period must satisfy the sampling theorem and must be faster than the period corresponding to twice the highest frequency of the modulated wave determined by the carrier frequency and the band of the input signal. Generally, the frequency of the carrier wave is chosen to be much higher than the highest frequency of the input signal, so the sampling frequency will be much higher. At this time, the speed of the analog-to-digital conversion circuit is generally slower than the speed of the digital-to-analog converter, so the speed of the analog-to-digital conversion cannot keep up with the period that satisfies the sampling theorem, resulting in discontinuous phase modulation. Therefore, there is a problem that the spectral characteristics deteriorate. Here, for convenience of explanation, we have considered the case where the input signal changes linearly, but it is true that similar problems exist for other general input signals as well.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. The difference from FIG. 1 is that an interpolation circuit 12 is provided between the output of the analog-digital conversion circuit 2 and the addition circuit 3. be. This interpolation circuit 1
2 attempts to estimate values at points other than the sampling points using values at each sampling point in order to compensate for the slow conversion speed of the analog-to-digital converter. As a method of obtaining such an estimated value, for example, internal interpolation as shown in FIG. 4 can be considered as a method of performing first-order approximation. The operation of this circuit is shown in FIG. The circuit shown in FIG. 4 will be explained below using FIG. 5. The input analog signal is sent to analog-to-digital converter 2
is converted into a digital value at every sampling period T. Using the sampling values at two successive times t _i and t _i+1 , the value of ΔE shown in FIG. 5 is calculated by the delay circuit 43 and the subtraction circuit 44.

Next, the division circuit 45 calculates ΔE/N according to the required number of interpolation points (N). This value is input to an accumulator circuit that performs addition for each interpolating clock cycle T/N, and the increment of the interpolated value shown by the small black circle in Fig. 5 relative to the sampled value at time t _i is determined. . This increase is equal to the sample value at time t _i and the addition circuit 47
This means that the required interpolation points are obtained by adding them together. Here, the addition accumulation circuit is reset every period T.

In the example shown in Fig. 2, the input signal increases linearly with time, so the fourth
The linear interpolator shown in the figure will give a perfect value with no errors. Even in the general case where the input signal does not increase linearly, interpolation can be performed with a fairly good approximation, but in order to increase the approximation, it is necessary to perform interpolation using three or more sample values. .

Although the present invention has been described with respect to the case of phase modulation, it is clear that it is also effective when performing frequency modulation equivalently by performing phase modulation after integrating an input signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional digital phase modulation circuit, FIG. 2 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 5 is a block diagram showing one embodiment of the interpolation circuit used in the present invention, and a diagram for explaining its operation. In these figures, 1 is a modulation signal input terminal, 2 is an analog-to-digital conversion circuit, 3 and 47 are addition circuits, 4 and 46 are accumulation circuits that add a certain value, and 5 is a circuit that sets a certain value. , 6 is a memory circuit, 7
is a digital-to-analog conversion circuit, 8 is a low-pass filter, 9 is an output terminal, 10 and 49 are clock input terminals, 11 and 50 are frequency dividing circuits, 12
is an interpolation circuit, 42 is an input terminal, 43 is a delay circuit,
44 is a subtraction circuit, 45 is a division circuit, and 48 is an output terminal.

Claims (1)

[Claims] 1. The sum of the output digital value of an analog-to-digital converter circuit that inputs an analog signal and converts this signal into a digital value at a fixed cycle, and the output of an accumulator circuit that adds a fixed value at each fixed cycle. A memory circuit whose address is the output of the adding circuit to be calculated is provided, the output digital value of this memory circuit is converted into an analog quantity, and the converted output is input to a low-pass filter, and the resulting signal is output. In the digital phase modulator, an interpolation interpolation circuit that performs calculations using the output digital values of the analog-to-digital conversion circuit at two or more different times to estimate the value within the sample period of the input analog signal; A digital phase modulator, characterized in that it is provided between the analog-digital conversion circuit and the addition circuit.