JPH0640616B2 - Digital filter-frequency characteristic converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter frequency characteristic conversion device for converting the frequency characteristic of a digital filter without changing the coefficient thereof.

2. Description of the Related Art Conventionally, when changing the frequency characteristics of a digital filter, for example, when the low pass filter corner frequency is shifted, it is necessary to recalculate and change the coefficient of the digital filter.

Problems to be Solved by the Invention However, when the frequency characteristic is changed as described above, if the coefficient is recalculated and changed each time, the frequency characteristic cannot be easily changed, and further, the digital characteristic cannot be changed. When the ROM is used instead of the multiplier for multiplying the coefficient of the filter, the content of the ROM has to be rewritten every time the coefficient is changed.

In view of the above point, an object of the present invention is to provide a digital filter frequency characteristic conversion device capable of changing the frequency characteristic without changing the coefficient of the digital filter when changing the frequency characteristic of the digital filter. To do.

Means for Solving the Problems The present invention is directed to frequency conversion coefficient setting means for setting a ratio for changing the frequency characteristic of a digital filter, and time series data input according to the ratio set by the frequency conversion coefficient setting means. An interpolation calculation circuit that performs a first interpolation calculation for converting the first sample clock rate into a second sample clock rate; and an interpolation coefficient ROM that stores a coefficient used for the first interpolation calculation. A digital filter that receives the output of an interpolation calculation circuit that performs the first interpolation calculation, and an inverse interpolation calculation circuit that performs the second interpolation calculation for returning the output of the digital filter to the first sample clock rate. , RO for inverse interpolation coefficient that stores the coefficient used for this second interpolation calculation
M, a clock pulse generation ROM storing a clock pulse corresponding to the second sample clock for operating the interpolation calculation circuit, the interpolation coefficient ROM, the digital filter, and the inverse interpolation calculation circuit, and the interpolation coefficient R
ROM that generates addresses for OM and ROM for inverse interpolation coefficient
It is a digital filter frequency characteristic conversion device including an address generation circuit.

Operation According to the present invention, the sampling clock rate of the input time-series signal can be freely converted by the interpolation calculation circuit and the interpolation coefficient ROM, and the converted signal is input to the digital filter. The frequency characteristic of the digital filter can be arbitrarily compressed or expanded on the frequency axis. Further, the sample clock rate of the output signal from the digital filter is returned to the original sample clock rate by the inverse interpolation calculation circuit and the inverse interpolation coefficient ROM. In this way, by using the digital filter frequency characteristic conversion device according to the present invention, the frequency characteristic can be changed without changing the coefficient of the digital filter.

Embodiment 1 FIG. 1 shows a block diagram of a digital filter frequency characteristic conversion device in a first embodiment of the present invention. In FIG. 1, 1 is an input terminal, 2 is an interpolation calculation circuit for interpolating an input data series into a data series of different sampling clocks, 3 is a digital filter, and 4 is an output of the digital filter 3 to the original time series data. Therefore, an inverse interpolation calculation circuit 5 that performs an interpolation calculation opposite to that of the interpolation calculation circuit 2, 5 is an output terminal, 6 is an interpolation coefficient ROM in which coefficients used for the calculation of the interpolation calculation circuit 2 are stored, and 7 is an interpolation circuit 2 ROM for interpolation coefficient 6, digital filter 3, ROM for clock pulse which stores clock pulse for operating inverse interpolation calculation circuit 4, 8 for inverse interpolation coefficient which stores coefficient used for calculation in inverse interpolation calculation circuit 4 RO
M and 9 are frequency conversion coefficient setting switches for setting the amount of change that changes the frequency characteristics of the digital filter.
Is a ROM address generation circuit 10 for generating the addresses of the interpolation coefficient ROM 6 and the inverse interpolation coefficient ROM 8 in accordance with the input from the frequency conversion coefficient setting switch 9.

The operation of the digital filter frequency characteristic converter of the present embodiment configured as described above will be described below. A case where a low-pass filter is used as the digital filter 3 will be described. As shown in FIG. 2A, the frequency characteristic of this low-pass filter is a corner frequency _c , and this corner frequency _c is shown in FIG. 2B _as'c (= M
/ N _c ). Hereinafter, M and N are M = 3, N
= 8 and the operation _is'c = 3 / _8c . When 3/8 is set by the frequency conversion coefficient setting switch 1, the time series data D (k) of the sampling clock _sc input from the terminal 1 in the interpolation calculation circuit 2 is
An interpolation calculation is performed to convert the sampling clock ' _sc (= _{3/8 sc} ) into time series data D' (k). The coefficients used for this interpolation calculation are stored in the interpolation coefficient ROM 6, and the contents of this ROM are read out as needed and used. The new time-series data subjected to the interpolation calculation is output in synchronization with the clock pulse from the clock pulse generation ROM 7. The clock pulse output from the clock pulse generation ROM 7 is an interpolation calculation circuit 2, an interpolation coefficient ROM, a digital filter 3, a reverse filter by appropriately thinning out the sampling clock _sc of the original time series data D (k). A clock pulse is generated to operate the interpolation calculation circuit 4 in the same manner as the clock operation _of'sc .

In the digital filter 3, since the calculation is performed on the data series D '(k) of the sampling clock ‘ _sc ’, the breakpoint frequency ‘ _c ’ is calculated when the calculation is performed on the data series D (k) (sampling clock _sc ). It has the following relationship with respect to the point frequency _c .

' _C / _c = _sc /' _sc = M / N = 3/8 (1) Thus, the break frequency of the output from the digital filter 3 is changed to a desired value. Further, the inverse interpolation calculation circuit 4
The data sequence D '(k) is
_It is converted to the original data series D (k) of _sc and output from the terminal 5. The coefficients used for the calculation of the inverse interpolation calculation circuit 4 are stored in the inverse interpolation coefficient ROM 8 and are read out and used at any time. The address of the interpolation coefficient ROM 6 is RO
The address of the inverse interpolation coefficient ROM 8 is also generated by the M address generation circuit 10 according to the value of M and is sent to the interpolation coefficient ROM 6 in synchronization with the clock pulse.
Is generated by the address generation circuit 10 according to the value of M,
The data sequence D (k) is sent to the inverse interpolation coefficient ROM 8 in synchronization with the sampling clock _sc . As described above, according to this embodiment, the interpolation calculation circuit 2 for converting the sampling clock of the input data and the interpolation coefficient ROM 6, and the inverse interpolation calculation circuit and the inverse interpolation for returning the output from the digital filter 3 to the original sampling clock. By providing the frequency conversion coefficient setting switch 9 for setting the ratio for changing the frequency of the coefficient ROM 8 and the digital filter 3, without changing the coefficient of the digital filter 3,
The frequency characteristic can be changed according to the value set in the frequency conversion switch 9. Next, it will be described with reference to FIG. 3 that the frequency characteristic of the digital filter moves on the frequency axis by the sampling clock _sc of the input data series. In FIG. 3, 12 and 13 are latches, 1
4 and 16 are 1/4 multipliers, 15 is a 1/2 multiplier, and 17 is an adder. The digital filter configured as described above has the following transfer characteristics.

G (Z) = 1/2 + 1 / 4Z ^-1 + 1 / 4Z ⁺¹ (2) Z = e ^{i Ω} Now, when this digital filter is operated with a clock of frequency _sc , its transmission The characteristics are as shown in FIG. 4A. Next, apply the digital filter to the frequency ‘ _sc (’
_When operated with a clock of ( _sc = 1/2 _sc ), its transfer characteristic becomes as shown in Fig. 4B, and the frequency characteristic of Fig. 4A is compressed to 1/2 toward the apex on the frequency axis. It has been done. As described above, it is clear that the frequency characteristic of the digital filter changes on the frequency axis depending on the frequency of the clock pulse for operating the digital filter, that is, the sampling clock of the input data. Thus as shown in Figure 2 A and B, the corner frequency when operated at break frequency _sc when the low-pass digital filter operating at a frequency _sc and is _c, frequency edge _'sc (= M / N _sc ), assuming that the break frequency is ‘ _c ’, ‘ _c / _c =
It is clear that the relation of ' _sc / _sc = M / N holds.

Next, the interpolation calculation will be described with reference to FIGS. The time series data shown in FIG. 5A is the sampling clock _sc
Data sampled at
_This is the data D '(k) sampled by _sc . Where _sc
And ′ _sc is, as is clear from the figure, ′ _sc = _{3/8 sc}
There is a relationship. Here, as one method of interpolating D (k) data to obtain D '(k) data, linear interpolation shown in FIG. 6A can be considered. In FIG. 6A, the time
t ₁ and 2t ₁ are sample points of the data D (k), and D 1
(t ₁ ) and D (2t ₁ ) indicate sample values at the respective times. Then D (t ₁₎ and connected by straight line D (2t _1), the straight line of the values of time t _2, the the sample value D at time t ₂ '(t _2). This calculation is performed as follows.

By the above calculation, D '(t ₂ ) can be interpolated from two points D (t ₁ ) and D (2t ₁ ). When the above interpolation calculation is performed on the data D (k) of FIG. 5A to obtain the data D ′ (k) of FIG. 5B, the value of D (0) is calculated as indicated by the broken line in the figure. Let D '(0), interpolate D' (1) using D (2) and D (3), and interpolate D '(2) using D (5) and D (6). Good. In addition, the above-mentioned interpolation calculation is performed with the triangular wave shown in FIG. 6B.
This is equivalent to convoluting the data D (k) on the time axis.
The triangular wave in FIG. 6B is an isosceles triangle having a vertex value of 1 and a time width of 2t ₁ . When considering the interpolation calculation on the frequency axis,
By multiplying the data D (k) of FIG. 5A by the triangular wave spectrum of FIG. 6B, that is, S _F 18 of FIG. 6C, the spectrum of data D ′ (k) of FIG. 5B is obtained. . In this way, when considered on the frequency axis, it is ideal that the spectrum of the interpolation function is the rectangular spectrum shown in FIG. 6C, which allows the spectrum of the original signal to pass without deterioration, and the number of data used for interpolation is increased. By doing so, the spectrum of the interpolation function can be approximated to a rectangle. FIG. 7 is a block diagram of an interpolation calculation circuit for performing the interpolation calculation shown in the formula (3). 20 is a latch, 21 and 23 are multipliers, 22 and 24 are multiplication coefficient input terminals, and 25 is an adder. Is. In the interpolating circuit thus configured, the time series data input from the terminal 19 is delayed in the latch 20, and the undelayed data is multiplied in the multiplier 22 by the coefficient C ₀ input from the terminal 22. Adder 2
5 and the delayed signal is sent to the terminal 2 in the multiplier 23.
The signal is multiplied by the coefficient C ₁ input from _No. 4 and added to the signal from the multiplier 21 in the adder 26, and output from the terminal 26. FIG. 8 shows that the sampling clock of the original time series data D (k) is _sc , the sampling clock of the data D ′ (k) obtained by the interpolation calculation is ‘ _sc , and‘ _sc / _sc = n / 8 (n = 1, 2, ... 7) shows the arrangement of the coefficients C ₁ and C ₂ in the interpolation coefficient ROM. As shown in FIG. 5, in the case _of'sc / _sc = _3/8 , there are three sets of coefficients C ₁ and C ₂ used for the interpolation calculation,
In the case of ′ _sc / _sc = n / 8, it is sufficient that there are n sets of coefficients, and as shown in FIG. 8, R (n, 1) R (n, 2) ... R (n, n) has coefficient C ₁ C ₂ is stored. Next, the clock pulse generated by the clock pulse generation ROM 7 will be described with reference to FIG. This clock pulse is a clock Pasuru corresponding to the clock frequency of the _'sc. FIG. 9A,
In B, C and D, the horizontal axis is the time axis. A is the frequency _sc
Clocks T ₀ , T ₁ , T _2, ...
Clocks of _sc (' _sc / _sc = _3/8 ) T ₀ ′, T ₁ ′, T ₂ ′
... is shown. The sample point of the data D '(k) of the sample clock' _sc converted from the data D (k) of the sample clock _sc by the interpolation calculation circuit 2 is the ninth point.
Although shown as T ₀ ′, T ₁ ′, T ₂ ′ in FIG. B, the clock pulses generated by the clock pulse generating ROM 7 are T ₀ , T ₂ , T ₅ ...... shown in FIG. 9C. This clock is a clock made by thinning out T ₀ , T ₁ , T _2, ... Of A. Thus, the clocks T ₀ ′, T ₁ ′, T shown in FIG.
_{Even if} C clocks T ₀ , T ₃ and T ₆ are used instead of ₂ ′, the values of D (k) at times T ₁ ′ and T ₃ are the same, and at times T ₂ ′ and T ₆
The values of D (k) are equal and the interpolation calculation circuit 2 operates correctly. Also, the clock T ₀ ″ (= T ₀ ) T ₁ ″ (= T shown in FIG. 9D.
₂ ) ... The clock pulse ROM stores the above clock pulses. FIG. 10 shows the contents of a certain range of the clock pulse ROM. Fig. 10A
Corresponds to the clocks T ₀ , T ₂ , T ₅ ... Of FIG. 9C, and [1, 0, from the address n to the address n + 7.
1, 0, 0, 1, 0, 0] is stored,
By repeatedly reading this with a clock of frequency _sc , clocks T ₀ , T ₂ , T ₅ ... Are obtained. See also FIG. 10B.
Are clocks T ₀ ″, T ₂ ″, T ₃ ″, T ₄ ″ in FIG. 9D (=
Corresponding to T ₀ , T ₂ , T ₄ , T ₆ ......), and address m
From address to m + 7 [1,0,1,0,1,0,
1, 0] is stored, and this value is used as the frequency _sc
The clock D is obtained by repeatedly reading with the clock. FIG. 11 is a diagram for explaining the operation of the inverse interpolation calculation circuit 4. The data D '(k) of A (sample clock' _sc ) to the data D (k) of B (sample clock).
_sc , ′ _sc / _sc = _3/8 ), the same value as D ′ (0) is used for D (0) as shown by the broken line in the figure, and D (1)
And D (2) are both obtained by interpolation calculation from D '(0) and D' (1). Also, D (3), D (4), D (5) are D '(1) and D'
From (2), D (6) and D (7) are obtained from D '(2) and D' (3). The inverse interpolation calculation circuit 4 has the same configuration as the block diagram shown in FIG. FIG. 12 shows the arrangement of the coefficients C ₁ and C _{2 in} the inverse interpolation coefficient ROM 8. ' _{Sc in} FIG. 11 is the sample clock frequency of the signal D' (k) in FIG. 10A, and _sc in FIG. 12 is B in FIG.
Is the sample clock frequency of the signal D (k). Thirteenth
The figure shows the spectra of signals D (k) and D '(k). A is a signal D obtained by sampling a continuous signal having a spectrum indicated by diagonal lines with a sample clock of frequency _sc
In the spectrum of (k), B indicates the spectrum of the signal D ' _(k) obtained by sampling the continuous signal of A and the shaded area with the sample clock of frequency' _sc (' _sc / _sc = M / N). It should be noted here that when the signal D (k) is converted into the signal D ′ (k) by interpolation and the sample rate is changed from _sc to ′ _sc , the signal D ′ (k) is not deteriorated due to aliasing distortion. This means that there is a lower bound on ′ _sc . Here, the occupied spectrum width of the original signal (hatched portion in FIG. 13A) is set so that _bw and 1/2 _bw <' _sc, that is, M / N =' _sc / _sc > 1/2 _bw / _sc , You must choose a value for N.

As described above, according to the present invention, the interpolation calculation circuit for converting the sample clock rate of time series data and the interpolation coefficient ROM are provided before the digital filter, and the sample clock rate converted after the digital filter is provided. Clock pulse generation ROM that generates a clock pulse to operate these systems by providing an inverse interpolation calculation circuit that restores the original clock rate and an inverse interpolation coefficient ROM
By providing, the frequency characteristic can be converted without changing the coefficient of the digital filter, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital filter frequency characteristic conversion device according to an embodiment of the present invention, FIG. 2 is an explanatory view of an operation for converting the frequency characteristic of a digital filter, and FIG. 3 shows an embodiment of a digital filter. A block diagram, FIG. 4 is a characteristic diagram of the digital filter shown in FIG. 3, FIG. 5 is an explanatory diagram of interpolation calculation, FIG. 7 is a block diagram of an interpolation calculation circuit, and FIG. 8 is an interpolation coefficient ROM. FIG. 9, FIG. 9 is an explanatory diagram of clock pulses generated by the clock pulse generation ROM, FIG. 10 is an explanatory diagram of the clock pulse ROM, and FIG. 11 is an explanatory diagram of the operation of the inverse interpolation calculation circuit. FIG. 12 is an explanatory diagram of the inverse interpolation coefficient ROM, the first
Figure 3 is a spectrum diagram. 2 ... Interpolation calculation circuit, 3 ... Digital filter, 4
...... Inverse interpolation calculation circuit, 6 ... Interpolation coefficient ROM, 7 ...
ROM for clock pulse generation, 8 ... RO for inverse interpolation coefficient
M, 9 ... Frequency conversion coefficient setting switch, 10 ... RO
M address generation circuit.

Claims (1)

[Claims] 1. A frequency conversion coefficient setting means for setting a ratio for changing a frequency characteristic of a digital filter, and a first sample clock rate of time series data input according to the ratio set by the frequency conversion coefficient setting means. First to convert to second sample clock rate
And an interpolation coefficient ROM storing the coefficients used in the first interpolation operation, and a digital filter having the output of the interpolation operation circuit for performing the first interpolation operation as an input. An inverse interpolation calculation circuit for performing a second interpolation calculation for returning the output of the digital filter to the first sample clock rate, and the second interpolation calculation circuit.
For inverse interpolation coefficient that stores the coefficient used for the interpolation calculation of
OM, and the second operation circuit for operating the interpolation calculation circuit, the interpolation coefficient ROM, the digital filter, and the inverse interpolation calculation circuit.
Of the clock pulse for storing the clock pulse corresponding to the sample clock, and the RO for generating the addresses of the interpolation coefficient ROM and the inverse interpolation coefficient ROM.
A digital filter frequency characteristic converter having an M address generating circuit.