JP2667119B2 - AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling AD converter, and more particularly to an oversampling AD converter used in a physical survey system.

[0002]

2. Description of the Related Art An AD converter of the Δ-Σ oversampling system has a better performance than a conventional successive approximation type AD converter.
Since an analog circuit such as an aliasing filter can be digitized, and a quantizer that converts an analog amount to a digital amount, a DA converter, and the like can be configured with a circuit of 1 to several bits, it is a system suitable for an LSI, and thus hardware This is a method that can realize an AD converter that is extremely excellent in terms of uniformity of quality and simplification of maintenance, in addition to downsizing of hardware, reduction in cost, and reduction in power consumption.

Although the Δ-Σ oversampling AD converter is already used in the audio world, time synchronization between an analog input signal and a digital output signal in AD conversion is a very important problem in the audio field. May not be. However, when used in a system that emphasizes the time synchronization of A / D conversion, for example, a physical exploration system that receives reflected waves from the ground of an artificial seismic source wave generated on the ground surface using a large number of sensors (gephones) deployed over a wide area. Then
Accurate measurement of the propagation time of artificial source waves is required.

In the conventional successive approximation type AD conversion method, a sample and hold circuit provided immediately before the input section holds an analog signal for the AD conversion processing time to obtain a digital signal output corresponding to the analog signal. it can. Therefore, it is possible to easily obtain AD conversion data synchronized with the AD conversion start signal.

On the other hand, A-Σ
Unlike the conventional successive approximation type, which holds the analog signal at a constant value and increases the resolution in the amplitude direction, the D converter performs oversampling at a frequency sufficiently higher than the Nyquist frequency to increase the resolution in the time direction, thereby increasing the resolution. Since it is a method of obtaining S / N, the time synchronization error between the analog input signal of AD conversion and the digital output signal is at most AD.
This corresponds approximately to the final sampling interval (time interval corresponding to the Nyquist frequency) of the conversion. For example, when the final sampling interval of the AD conversion is 1 msec, the time synchronization error is about 1 msec at maximum.

[0006]

When such a time synchronization error is present, the delay time from the input of an analog signal to the output of a corresponding digital signal becomes uncertain, and a plurality of channels are not provided. However, when an AD converter is provided, there is a possibility that the delay time is shifted between channels. Especially in geophysical exploration systems,
If the time synchronization error is large, the effect on the measurement of the propagation time of the artificial source wave cannot be ignored, and the AD converter of the △ -Σ oversampling method has not been put to practical use.

[0007]

SUMMARY OF THE INVENTION An AD converter according to the present invention has been made in view of the above points, and oversamples an input analog signal into a first digital signal having a first sampling interval. An A / D conversion modulator section for converting, the first digital signal being input, a first digital signal delayed by giving a predetermined delay time to the first digital signal, and an A / D conversion start pulse given from the outside being supplied to a predetermined An AD conversion start synchronizing circuit for generating a delayed AD conversion start pulse by time delay; and a second digital signal having a second sampling interval by thinning out samples represented by the delayed first digital signal. A decimation filter for producing a signal, wherein the address of at least one processing program is the delayed A And a said decimation filter to be reset by the conversion start pulse.

Here, the first digital signal is a 1-bit digital signal, and the decimation filter includes a first decimation filter for thinning out samples represented by the 1-bit digital signal and outputting a multi-bit digital signal. And a second decimation filter that further thins out the sample represented by the multi-bit digital signal and outputs the sampled signal as the second digital signal.

Further, the processing time of the second decimation filter is determined so as to be substantially equal to the second sampling interval, and the address of the processing program of the second decimation filter is supplied to the externally supplied AD. It may be reset by a conversion start pulse.

The sum of the processing time of the AD conversion modulator, the delay time of the AD conversion start synchronization circuit, and the processing time of the first decimation filter is:
The address of the processing program of the first decimation filter is determined to be substantially equal to the second sampling interval, and the address of the processing program of the first decimation filter is the sum of the processing time of the AD conversion modulator unit and the delay time of the AD conversion start synchronization circuit. It may be reset by an AD conversion start pulse delayed by a substantially equal time.

Another AD converter according to the present invention comprises an AD converter for oversampling an input analog signal and converting the input analog signal into a first digital signal having a first sampling interval; A second sample interval having a second sampling interval
A first decimation filter for creating a digital signal of the first and second digital signals, wherein the first decimation filter whose processing program address is reset by an externally supplied AD conversion start pulse and the second digital signal are inputted. And an AD conversion start synchronizing circuit which outputs a second digital signal delayed by giving a predetermined delay time to the signal.

Here, the first digital signal is a one-bit digital signal, and the first decimation filter thins out a sample represented by the one-bit digital signal and generates a multi-bit digital signal as the second digital signal. A signal, and input the delayed second digital signal output from the AD conversion start synchronization circuit;
It may further include a second decimation filter that further thins out the sample represented by this signal and outputs a multi-bit digital signal having a third sampling interval.

Further, a processing time of the second decimation filter is determined to be substantially equal to the third sampling interval, and an address of a processing program of the second decimation filter is supplied to the externally supplied AD. It may be reset by a conversion start pulse.

The sum of the processing time of the AD conversion modulator, the processing time of the first decimation filter, and the delay time of the AD conversion start synchronization circuit is:
The determination may be made so as to be substantially equal to the third sampling interval.

Still another AD converter according to the present invention is an AD converter for oversampling an input analog signal to convert it into a 1-bit digital signal having a first sampling interval, and represents the 1-bit digital signal. A first decimation filter that thins out samples to create a multi-bit digital signal having a second sampling interval, and the multi-bit digital signal that is delayed by inputting the multi-bit digital signal and applying a predetermined delay time to the first decimation filter. An AD conversion start synchronizing circuit for outputting a signal; and a second for inputting the delayed multi-bit digital signal, further thinning out samples represented by the signal, and outputting a multi-bit digital signal having a third sampling interval. A decimation filter,
And a second decimation filter having a processing time substantially equal to the third sampling interval and resetting an address of the processing program by an externally supplied AD conversion start pulse.

Here, the sum of the processing time of the AD conversion modulator section, the processing time of the first decimation filter, and the delay time of the AD conversion start synchronization circuit is substantially equal to the third sampling interval. May be determined.

In the above, the AD conversion start synchronizing circuit may input a clock used for the oversampling and perform delay time control of an integral multiple of the first sampling interval.

[0018]

According to the AD converter according to the present invention, the final sampling interval generated between the input analog signal and the output digital signal in the conventional oversampling type AD converter. This time synchronization error can be reduced to about the sampling interval at the time of oversampling.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 △ -Σ oversampling AD according to Embodiment 1 of the present invention
As shown in FIG. 1, the converter is roughly composed of an AD conversion modulator section 11 and a decimation filter section 12. The decimation filter section 12 includes an AD conversion start synchronization circuit 13 and a decimation filter I (1).
4) and a decimation filter II (15).

The operation of the Δ-Σ oversampling A / D converter is such that the A / D conversion modulator 11 converts the analog input signal to a bit rate of 1024 ks / s (sample / s).
Second), it is converted into a serial binary digital signal, and this 1-bit serial data is output to the decimation filter unit 12 in the next stage. Since the AD conversion modulator 11 requires a certain processing time (delay time), this is set to τ ₀ .

On the other hand, in the decimation filter unit 12, the decimation filter I (14) thins (decimates) the input 1-bit serial data to convert it into 24-bit parallel data, and further,
The decimation filter II (15) thins this out and outputs 24-bit parallel data having the final sampling rate. For example, a final sampling rate of 2ks / s, 1ks / s, 500s / s, or 250
s / s (0.5 ms, 1 ms, 2
msec, or 4 msec).
The samples in the input serial data of 24 ks / s are divided by the decimation filter I into 1/16, 1/32, 1 /
64ks / s, 32ks /
The 24-bit parallel data reduced to the rate of s, 16 ks / s, or 8 ks / s is output, and further decimation to 1/32 in the decimation filter II to obtain final output data.

In this operation, the delay time generated by the decimation filter I is τ ₁ , and the delay time generated by the decimation filter II is τ ₂ . These delay times are so resets the address of the processing program of the decimation filter is changed by (the address to 0) timing, if reset at any time, about the same level as the final sampling interval tau _s 0 .5
The maximum time synchronization error of msec, 1 msec, 2 msec, or 4 msec occurs.

[0024] Therefore, in the present embodiment, the AD conversion start synchronizing circuit 13, the delay time of the delay time tau ₀ and decimation filter I of the delay time tau ₁ and AD conversion start synchronizing circuit 13 of the AD converter modulator part 11 tau
The delay time τ is controlled so that the total τ _all (= τ ₀ + τ ₁ + τ) is substantially equal to the final sampling interval τ _s of AD conversion. Actually, a delay occurs when data is transferred from the decimation filter I to the decimation filter II. Therefore, τ _all may be within the range shown in the following equation.

Τ _s −τ _c <τ _all ≦ τ _s where τ _c is the period of the output clock of the decimation filter I. For example, if the frequency of the output clock of the decimation filter I is 64 ks / s, the period τ _c is 16 μsec. FIG. 2 shows how the delay time is adjusted. The AD conversion start synchronizing circuit 13 controls the delay time τ by using the 1024 kHz clock according to the following equation.

Τ = (N ₀ +1) / clock frequency where N ₀ is a predetermined positive integer. The delay time τ ₀ + τ is obtained by the following equation.

Τ ₀ + τ = N ₁ / clock frequency where N ₁ is a predetermined positive integer. The AD conversion start synchronizing circuit 13 outputs the τ ₀ + τ after a delay time of τ ₀ + τ from the input of the AD conversion start pulse STP.
The address of the processing program of the decimation filter I is reset.

On the other hand, the processing time τ ₂ of the processing program of the decimation filter II is set to be substantially equal to the final sampling interval τ _s of AD conversion.
It is directly reset by the AD conversion start pulse STP.

As a result, the time synchronization accuracy between the input analog signal of the AD conversion modulator 11 and the 24-bit digital output signal from the decimation filter unit 12 can be set to about ± 1 μsec. Incidentally, the values N ₀ and N ₁ for determining the delay time may be inputted from the outside, or may be provided inside the AD conversion start synchronization circuit 13.

FIG. 3 is a diagram showing details of the AD conversion start synchronization circuit 13. The AD conversion start synchronization circuit 13
It is composed of a circuit for controlling the delay time of τ (= (N ₀ +1) / clock (1024 ks / s)) and resetting the addresses of the processing programs of the decimation filters I and II by the AD conversion start pulse STP.

The digital counter 34 has a clock (10
24 ks / s), N = 0, 1, 2,... N ₀ , ₀ , 1, 2,.
.. N0, ₀ , 1, 2,... Are counted and output, and the write address control is to store serial data at a transmission speed of 1024 ks / s output from the AD conversion modulator in an address memory of a value output from the digital counter 34. To memorize. The adder 35 outputs a value obtained by adding 1 to the value N indicated by the digital counter 34. The read address control circuit performs one bit of data of the address memory of the value indicated by the adder, that is, (N ₀ +1) The data written by the previous clock is read out and output to the next stage decimation filter I at a transmission speed of 1024 ks / s. As a result of these series of operations, τ (= (N ₀ +1) / clock (1024 ks) exists between the serial data output from the AD conversion modulator and the input serial data of the decimation filter I.
/ s)), that is, a delay time has occurred.

The digital counter 36 starts counting when an AD conversion start pulse STP is input, and counts from ₁ to N1 with a clock (1024 ks / s).
The reset control circuit 37 determines that the value of the digital counter I is N ₁
, A reset signal is output to the decimation filter I. The decimation filter I resets the address of the processing program by the reset signal from the reset control circuit 37, thereby synchronizing the sampling time with the analog input signal of the AD conversion modulator and terminating the processing program at the AD conversion sampling time. It becomes possible to synchronize. The decimation filter II can synchronize with the end of the processing program of the preceding decimation filter I by resetting the address of the processing program with the AD conversion start pulse STP.

In this embodiment, the memory is used for the synchronizing circuit, but it is also possible to use a shift register.

Embodiment 2 In order to improve the accuracy of time synchronization between an analog input signal and a digital output signal of a Δ-Σ oversampling AD converter, in Embodiment 1, a synchronization circuit is provided in a stage preceding a decimation filter I, That is, it is placed on the input side of the decimation filter, and the final sampling interval of the AD conversion is 0.5 ms.
ec ± 1μ regardless of 1msec, 2msec or 4msec
High-precision time synchronization called sec.

In the second embodiment, the time synchronization accuracy similar to that of the first embodiment, that is, the high accuracy of ± about 1 μsec, is obtained,
In addition, power consumption is reduced as compared with the first embodiment. This operation will be described below. The effect of low power consumption is as follows.
In this embodiment, the power consumption is significantly improved to about 1/5 to 1/10 or less of the first embodiment, although it depends on the sampling interval of the AD conversion, the oversampling clock, and the like.

In the present synchronization system, in order to improve the accuracy of time synchronization between the analog input signal and the digital output signal of the Δ-Σ oversampling AD converter, the synchronization circuit 43 is decimated as shown in FIG. By providing the filter after the decimation filter I of the filter unit 42, that is, between the decimation filters I and II, the time synchronization accuracy is about the same as that of the first embodiment, approximately ± 1 μsec, and low power consumption is realized. ΣThe oversampling AD converter has been enabled.

The Δ-Δ oversampling AD conversion of the present invention
The synchronous operation of the converter is performed by the AD converter 41.
Analog input signals at a bit rate of 1024 ks / s.
Convert to a real binary digital signal and output to the next stage
You. In the decimation filter section 42, FIG.
As shown, in the decimation filter I (44), A
Final sampling interval of D conversion 0.5msec, 1mse
c 1/16, 1/3, respectively, depending on 2msec or 4msec
2, 1/64 or 1/128 is decimated and output level
Down to 64ks / s, 32ks / s, 16ks / s or 8ks / s
Output 24-bit parallel data.
With the replacement start pulse STP, the address of the processing program
Reset. In the next stage of the synchronization circuit 43, the decimation
Output rate of output filter 64k / s, 32ks
/ s, 16ks / s or 8ks / s 24-bit parallel data
Is the processing time (delay) in the AD conversion modulator 41.
Time) τ ₀, The delay time τ in the decimation filter I
₁, And the total delay time τ in the synchronous circuit τall (= τ₀
+ Τ₁+ Τ) is the final sampling interval τ of AD conversion
_sΤ (= (N₀+1) / Cross
H) delay by the value.

The delay time τ determined by the frequency of the external input N ₀ value and the clock. Here, the clock is an output rate 64 k of the 24-bit parallel data output by the decimation filter I according to the sampling interval of the AD conversion.
s / s, 32 ks / s, 16 ks / s , or 8 ks / s
This is a clock synchronized with s. Note that τ _a11 (= τ ₀
+ Τ ₁ + τ), the processing time τ ₀ of the AD conversion modulator is τ ₀ <1 μsec, and the processing time τ ₁ of the decimation filter I (44) is the final sampling interval of AD conversion 0.5 msec, 1 msec , 2m
The processing program time of the decimation filter I (44) in response to 1 sec or 4 msec is 1/1
Output rates 64 ks / s, 32 ks / s decimated to 6, 1/32, 1/64 , or 1/128
s, 16 ks / s , or 8 ks / s , so that 16 μs, 32 μs,
64μsec, or take the value of 128Myusec, by an external input _{N 0} values, for example, 30 of the digital counter 64 of the synchronizing circuit, the last sampling interval 0.5msec approximately AD convert tau _a11,, 1 msec, 2
msec or 4 msec.

The decimation filter II operates to decimate the input data to 1/32 and to output a 24-bit digital signal at a time (τ _s ) corresponding to the final sampling interval of AD conversion. The decimation filter II resets the address of the processing program in the AD conversion start pulse STP, to wait for data from the preceding stage is input, and the processing time tau ₂ of the processing program is equal to tau _s, namely tau by being made to be ₂ = _{τ s,} which enables the synchronization of the input data.

The configuration of the AD conversion start synchronization circuit 43 is as follows.
Equal to τall approximately tau _s as shown in FIG. 6 (number 1)
And a circuit for controlling the delay time of τ, and a decimation filter I by an AD conversion start pulse STP.
And the addresses of the II processing programs are reset controlled. The circuit configuration is different from that of the first embodiment in that a circuit for controlling the delay time of τ is placed after the decimation filter I, and a digital counter for controlling the delay time of the reset signal to the decimation filter I is not used. However, it is different. The memory capacity is almost the same as that of the first embodiment, and the AD conversion start pulse STP causes the decimation filter I to reset the address of the processing program. As another synchronous operation, the decimation filter II resets the address of the processing program with an AD conversion start signal, waits for input of data from the previous stage, and the processing time τ _{2 of the} processing program is equal to τ _s The respective operations are performed as described below.

A major difference between the synchronous configurations of the first and second embodiments is that the input data rate of the delay time control circuit of τ is 1024 ks / s in the first embodiment, and 1/16 to 1 in the second embodiment. /
The point is 128, which is 64 ks / s to 8 ks / s. This difference
It appears as a difference in power consumption of the synchronous operation, and the power consumption of the second embodiment is 1/5 to 1/10 of that of the first embodiment.

In this embodiment, a memory is used for the delay time control circuit (synchronous circuit). However, it is also possible to use a shift register. Further to the N ₀ and the external input is a possible way to have the synchronization circuit.

Third Embodiment FIG. 7 shows a circuit configuration of an AD converter according to a third embodiment of the present invention. As compared with the second embodiment, the time synchronization accuracy between the analog input signal and the digital output signal of the AD converter is inferior, but the power consumption can be reduced similarly to the second embodiment, and the product development is facilitated. Circuit.

The construction of the AD converter of the Δ-Σ oversampling system of the present time synchronization system is shown in the second embodiment, that is, FIG.
And is different from the first embodiment in that the AD converter start signal does not have the function of resetting the address of the processing program of the decimation filter I. The accuracy of this time synchronization method is maximum compared to the second embodiment.
Although it is deteriorated by 1/32, development of the decimation filter unit can be facilitated.

[0042]

As described above, according to the present invention, a time synchronization error between an input analog signal and an output digital signal, which generally occurs in an oversampling AD converter, can be greatly improved. Therefore, it is possible to perform highly accurate measurement especially in a system in which time synchronization error is a problem, such as a physical survey system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an AD converter according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the AD converter according to the first embodiment.

FIG. 3 is a block diagram illustrating details of a synchronization circuit in the AD converter according to the first embodiment.

FIG. 4 is a block diagram illustrating an AD converter according to a second embodiment of the present invention.

FIG. 5 is a time chart illustrating an operation of the AD converter according to the second embodiment.

FIG. 6 is a block diagram illustrating details of a synchronization circuit in the AD converter according to the second embodiment.

FIG. 7 is a block diagram illustrating an AD converter according to a third embodiment of the present invention.

[Explanation of symbols]

 11, 41, 71 AD conversion modulator section 12, 42, 72 Decimation filter section 13, 43, 73 AD conversion start synchronization circuit 14, 44, 74 Decimation filter I 15, 45, 75 Decimation filter II 31, 61 Memory 32, 62 Write address controller 33, 63 Read address controller 34, 36, 64 Digital counter 35, 65 Adder 37 Reset control circuit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Yoshiro Kawabe, Inventor 2-17-22 Akasaka, Minato-ku, Tokyo (Akasaka Twin Tower East Building) Inside the Earth Sciences Research Institute, Inc. (56) References JP 62 -76313 (JP, A) JP-A-5-175785 (JP, A) JP-A-4-65912 (JP, A) JP-A-6-209296 (JP, A)

Claims (11)

(57) [Claims] 1. An AD conversion modulator section (11) for oversampling an input analog signal to convert it into a first digital signal having a first sampling interval, and receiving the first digital signal, and AD conversion start synchronizing circuit for generating a delayed AD conversion start pulse by outputting a first digital signal delayed by giving a predetermined delay time and delaying an externally supplied AD conversion start pulse by a predetermined time (1
3) and a decimation filter (14, 1) for thinning out samples represented by the delayed first digital signal to create a second digital signal having a second sampling interval.
5) wherein the address of at least one processing program is reset by the delayed A / D conversion start pulse;
15) An AD converter comprising: 2. The AD converter according to claim 1, wherein said first digital signal is a 1-bit digital signal, and said decimation filters (14, 15)
A first decimation filter (14) for thinning out the sample represented by the bit digital signal to output a multi-bit digital signal; and a first decimation filter for further thinning out the sample represented by the multi-bit digital signal to output as the second digital signal. 2 decimation filters (15)
And an A / D converter. 3. The A / D converter according to claim 2, wherein said second decimation filter has a processing processor.
The address of the program is converted to an external
By resetting the Tatoparusu, the second processing time of the decimation filter (15) is, are determined to be equal properly with the second sampling interval
AD converter, characterized in that that. 4. The AD converter according to claim 3, wherein a processing time of the AD conversion modulator section, a delay time of the AD conversion start synchronization circuit, and the first decimation filter. 14) the sum of the processing time and the second sampling interval is less than or equal to the second sampling interval ;
The first decimation from the second sampling interval.
Subtraction cycle of the output clock of the filter (14)
An AD converter characterized in that it is determined so as to be larger than the calculated value. 5. An AD conversion modulator section (41) for oversampling an input analog signal to convert it into a first digital signal having a first sampling interval, and decimating a sample represented by the first digital signal. A first decimation filter (44) for producing a second digital signal having a second sampling interval, wherein the address of the processing program is reset by an externally supplied AD conversion start pulse. A decimation filter (44), which inputs the second digital signal, gives a predetermined delay time to the second digital signal, and outputs a delayed second digital signal
An AD converter comprising: a D conversion start synchronization circuit (43); 6. The AD converter according to claim 5, wherein the first digital signal is a one-bit digital signal, and the first decimation filter (44) is
A sample represented by the bit digital signal is decimated to create a multi-bit digital signal as the second digital signal, and a delayed second digital signal output from the AD conversion start synchronization circuit (43) is input; An AD converter further comprising a second decimation filter (45) for further thinning out a sample represented by the signal and outputting a multi-bit digital signal having a third sampling interval. 7. An analog-to-digital converter according to claim 6, wherein said second decimation filter (45) has a processing processor.
The address of the program is converted to an external
By resetting the Tatoparusu, the second processing time of the decimation filter (45) is, are determined to be equal properly and the third sampling interval
AD converter, characterized in that that. 8. A AD converter according to claim 7, the sum of the delay time of the processing time and the AD conversion start synchronizing circuit before Symbol first decimation filter (44) (43), wherein AD converter, characterized in that it is determined to be the third equal properly and the sampling interval. 9. An AD conversion modulator section (71) for oversampling an input analog signal to convert it into a 1-bit digital signal having a first sampling interval, and decimating a sample represented by the 1-bit digital signal to form a second signal. First decimation filter (74) for producing a multi-bit digital signal having a sampling interval of
An AD conversion start synchronizing circuit (73) which receives the multi-bit digital signal, outputs a delayed multi-bit digital signal by giving a predetermined delay time to the multi-bit digital signal, and inputs the delayed multi-bit digital signal and, a second decimation filter for outputting a multi-bit digital signal having a third sampling interval decimating further samples this signal represents (75), its
AD to which the address of the processing program of
AD converter including a <br/> the second decimation filter (75) which have a <br/> the third equal correct processing time and the sampling interval by being reset by the conversion start pulse. 10. A AD converter according to claim 9, the sum of the delay time of the processing time and the AD conversion start synchronizing circuit before Symbol first decimation filter (44) (43), wherein AD converter, characterized in that it is determined to be the third equal properly and the sampling interval. 11. The A / D converter according to claim 1, wherein the A / D conversion start synchronization circuit inputs a clock used for the oversampling and performs the first sampling. An AD converter characterized by performing delay time control of an integral multiple of an interval.