JPH0233177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a signal generator, particularly a digital signal generator that generates a pulse signal with a signal waveform expressed in a digital code, by synchronizing a delayed sampled signal and generating an arbitrary signal from the sampled signal. The present invention relates to a signal generating device that sequentially outputs a waveform signal expressed by a digital code as an encoded bit pulse signal after a predetermined delay time set to .

As shown in FIG. 1, a conventional digital signal generation device generates an output f from a signal generation circuit 1 that generates an encoded bit pulse signal of a waveform signal expressed in digital codes in synchronization with a sampled signal.
(t), that is, the encoded bit pulse signal is transmitted to the delay circuit 2 provided at the next stage of the signal generation circuit 1.
A coded bit pulse signal f(t-Δt) delayed by Δt from reception of the sampled signal fs is generated.

By the way, an advantage of digital signal processing is that it is possible to perform time division multiplexing in which one circuit processes several signals within one sampling period. Therefore, in a signal generator, for example, in the diagram for explaining the operation of time division multiplexing shown in FIG. 2, when the sampling period T of sampling signals S ₁ and S ₂ is time divided into n, the channel When giving a desired signal to channel 1 (CH1), it is given in synchronization with sampling signal S ₁ , but when giving a desired signal to channel 2 (CH2), channel 3 (CH3), etc., it is given at Δt from sampling signal S ₁ . ₁ , _Δt2 ,
…You need to give late.

In addition, when giving a test signal to a pipeline processing circuit to speed up signal processing, it is necessary to arbitrarily set the delay from the sampled signal in order to give the test signal to each stage of the cascade-connected pipeline processing circuit. It needs to be variable.

A signal generating device used for testing or maintaining a digital signal processing circuit is required not only to output a desired signal in synchronization with a sampled signal, but also to be able to arbitrarily set a delay from the sampled signal as described above. ing.

As explained in FIG. 1, the conventional digital signal generation device generates an encoded bit pulse signal f(t) from a signal generation circuit 1 in synchronization with a sampling signal fs, and generates the encoded bit pulse signal f(t) using a delay circuit 2 using a shift register or the like. Δt
Since f(t - Δt) is obtained by delaying, if you set the delay time arbitrarily or increase the range of delay time, you will need to stack many delay elements, which will increase the circuit scale or change the circuit configuration. The disadvantage was that it made things more complicated. In particular, when outputting encoded bit pulse signals in parallel from the signal generation circuit 1, a delay circuit 2 must be provided for each bit.
As the number of bits increases and the delay time increases, the above-mentioned drawbacks are further magnified.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks, and in generating an encoded bit pulse signal from a signal generation circuit in synchronization with a delayed sampled signal, the sampled signal is delayed by a desired delay time. A delayed sampling signal is given to the signal generation circuit as described above, so that a desired delayed encoded bit pulse signal is always obtained regardless of whether the encoded bit pulse signal output from the signal generation circuit is serial or parallel. The purpose is to provide a generator. Therefore, a variable delay circuit that delays the received sampled signal by an arbitrary time and outputs it, and a waveform signal expressed by a digital code is read out using the delayed sampled signal so that the waveform signal is output after an arbitrarily set delay. The present invention is characterized by comprising a signal generation circuit that generates a waveform signal expressed by the digital code. This will be explained below with reference to the drawings from FIG. 3 onwards.

FIG. 3 shows the basic configuration of the signal generator according to the present invention, FIG. 4 shows the configuration of a specific embodiment of FIG. 3, and FIG.
The figure shows a waveform explanatory diagram in which the output waveform is a sine wave.

In FIG. 3, 3 is a signal generating circuit, which corresponds to the signal generating circuit 1 in FIG. Reference numeral 4 denotes a variable delay circuit which outputs a delayed sampled signal obtained by delaying the sampled signal by a delay time Δt arbitrarily set from the outside. Therefore, the sampled signal becomes the delayed sampled signal delayed by Δt in the variable delay circuit 4, and is inputted to the signal generation circuit 3 as the delayed sampled signal, thereby generating an encoded bit pulse signal delayed by Δt from the sampled signal. f(t-Δt) is output from the signal generation circuit 3.

In FIG. 4, 3 and 4 correspond to those in FIG. 5 is a register, and the register 5
6 is an adder circuit that holds the data of the step number of the step number setting signal which is arbitrarily set from the outside. 7 is a comparator circuit that compares the output of the adder circuit 6 with a fixed sampled value N stored in advance (described in detail later), and calculates the output of the adder circuit 6. If the sampled value N or less, the output of the adder circuit 6 is output as is, and if the output of the adder circuit 6 is greater than or equal to the sampled value N, the value obtained by subtracting the sampled value N from the output of the adder circuit 6 is output. , 8 is an address register in which the value output from the comparator circuit 7, that is, data specifying a memory address, which will be explained next, is delayed by Δt with respect to reception of the sampling signal output from the variable delay circuit 4. 9 is a memory which stores an encoded bit pulse signal of a signal waveform expressed in a digital code; 10 is a pulse generation circuit; 11 is a memory. A counter counts the pulses generated by the pulse generation circuit 10, and the count value of the counter 11 is reset to zero upon reception of the sampling signal. 12 is a register that delays the sampling signal by Δt. 13 is a matching circuit which outputs a delayed sampling signal when the delayed data value of Δt set in the register 12 and the count value of the counter 11 match. be.

Next, the operation of FIG. 4 will be explained using the waveform explanatory diagram of FIG. 5.

The memory 9 stores in advance an encoded bit pulse signal obtained by sampling an analog signal waveform, for example, the sine wave waveform shown in FIG. 5 at a fixed period (sampling period), quantizing it, and further encoding it as data. Store one waveform. The number of samples of this waveform is taken as N mentioned above. and register 5
In order to obtain a delayed sampling signal of Δt, a delay data value K is set in the register 12 by a delay time setting signal.

To explain the operation of the variable delay circuit 4 first, the counter 11 counts the pulses generated by the pulse generation circuit 10 and outputs the count value to the coincidence circuit 13. The count value is reset to zero. The delay data value K set in the register 12 is input to the coincidence circuit 13, and when the count number of the counter 11 reaches K, the coincidence circuit 13 outputs a coincidence signal. That is, a delayed sampled signal delayed by Δt from the sampled signal is obtained. As you can see, the delay data value K to be set in register 12
The delay time Δt is determined by the pulse period of the pulse generating circuit 10 and the pulse period of the pulse generating circuit 10. Therefore, by setting the delay data value K=0 in the register 12, a delayed sampling signal with a delay time Δt=0 can be obtained.

As can be seen from the above description, every time a sampled signal is received, a delayed sampled signal delayed by Δt is output from the variable delay circuit 4.

On the other hand, in the signal generating circuit 3, if we assume that the step number k set in the register 5 is set to, for example, "3", then the "3" is input to the adder circuit 6, and the initial value of the address register 8 is It is added with the value "0" and "3" is output from the adder circuit 6 to the comparator circuit 7. Comparison circuit 7
Now, compare the sampled value N=1000 shown in FIG. 5 with the output "3" from the adder circuit 6. As explained above, since the output "3" from the adder circuit 6 is smaller than the sampled value N=1000, the output "3" from the adder circuit 6 is directly outputted to the address register 8. When the delayed sampling signal delayed by Δt from the sampling signal described above is input to the address register 8, "3" is set in the address register 8, and address 3 of the memory 9 is accessed. As a result, data _N3 of the encoded bit pulse signal stored at address 3 in the memory 9 is read out.
The output "3" from the comparator circuit 7 set in the address register 8 is input to the adder circuit 6, and the output "3" is added to the number of steps k=3 set in the register 5. "6" is output. As before, the comparator circuit 7 outputs "6" to the address register 8,
"6" is set in the address register 8 by the delayed sampling signal delayed by Δt from the sampling signal. As a result, data _N6 of the encoded bit pulse signal is read out from the memory 9. Similarly, each time the delayed sampled signal delayed by Δt from the sampled signal is output from the variable delay circuit 4 to the signal generation circuit 3, the encoded bit pulse signal data N ₉ , N ₁₂ ,
. . . are sequentially read out from the memory 9. In this way, one waveform of a sine wave is output from the signal generating circuit 3.

When the output from the adder circuit 6 becomes "1002", the "1002" is larger than the sampled value N = 1000, so the comparator circuit 7 directs "2" of 1002 - 1000 = 2 to the address register 8. Output. Thereafter, as before, the corresponding "2" is set in the address register 8 by the delayed sampling signal delayed by .DELTA.t from the sampling signal, and data _N2 of the encoded bit pulse signal is read out from the memory 9. Thereafter, every second encoded bit pulse signal data N ₅ , N ₈ , .

As is clear from FIG. 5, the oscillation frequency of the sine wave is determined by the number of steps k set in the register 5, the sampling value N, and the period of the sampling signal, and the delay data value set in the register 12 is determined. A sine wave encoded bit pulse signal delayed by Δt from the sampled signal can be obtained by K and the pulse period of the pulse generating circuit 10.

By storing data regarding an arbitrary signal waveform in the memory 9, a desired delayed signal can be generated for that waveform, and different signal waveforms can also be generated continuously.

Regarding the variable delay circuit 4, in FIG. 4, the oscillation frequency of the pulse generation circuit 10 is kept constant and the delay data value K set in the register 12 is made variable to change Δt. It is also possible to make the Δt variable by keeping the delay data value K set in the register 12 constant and changing the oscillation frequency of the pulse generating circuit 10. Furthermore, the delay time setting signal (Fig. 4)
The above-mentioned Δt can also be changed by a high-speed timer circuit whose operation time is made variable by . This type of high-speed timer circuit is also included in the variable delay circuit 4 shown in FIG. .

As described above, according to the present invention, it is possible to easily generate a desired signal delayed by an arbitrary time from a sampled signal, and since there is no delay after the signal generation circuit, the delay circuit can be simple. This effect becomes even greater when the encoded bit pulse signals output from the signal generator have to be output in parallel. Since the delay time can be easily set variably over a wide range, it is useful when used as a signal generator for testing or maintenance of digital signal processing circuits.

[Brief explanation of drawings]

Figure 1 shows the basic configuration of a conventional signal generator, and Figure 2 shows the basic configuration of a conventional signal generator.
The figure is an explanatory diagram of the operation of time-division multiplexing processing, Figure 3 is the basic configuration of the signal generator according to the present invention, Figure 4 is the configuration of a specific embodiment of Figure 3, and Figure 5 outputs a sine wave. An explanatory diagram of waveforms is shown. In the figure, 1 is a signal generation circuit, 2 is a delay circuit, 3 is a signal generation circuit, 4 is a variable delay circuit, 5 is a register, 6 is an addition circuit, 7 is a comparison circuit, 8 is an address register, 9 is a memory, 10 is a pulse generation circuit,
11 represents a counter, 12 a register, and 13 a matching circuit.

Claims (1)

[Claims] 1. A variable delay circuit that delays a received sampled signal by an arbitrary time and outputs it, and a delay time that is arbitrarily set by reading out a waveform signal expressed in a digital code using the delayed sampled signal. and a signal generating circuit that later generates a waveform signal expressed in the digital code.