JPS6171499A - Data sampling method - Google Patents

Abstract

PURPOSE:To digitize securely even for an input close to a Nyquist frequency by sampling an input signal over plural periods, indicating that individual digital codes should be located at any position in one period of an input analog signal and restoring an original waveform. CONSTITUTION:A signal AS outputted from an analog signal source 1 is inputted to an A/D converter, converted to a digital quantity DS by a sampling clock SC from a clock generating device 5 and written in a memory 3. An address controller 4 is a part to generate an address to re-arrange the data at the time of reading from the memory 3 and at the time of writing to the memory 3. The address controller 4 is composed of a register 6 to give an address skipping quantity to re-arrange, a register 7 to specify a start address, an accumulator 8 to calculate a skipping quantity, a latch 9 to hold the calculation result, an accumulator 10 to add a start address and a skipping quantity and a latch 11 to hold the result.

Description

DETAILED DESCRIPTION OF THE INVENTION [°Field of Application of the Invention] The present invention relates to a data sampling method for an A/D converter suitable for digitizing an analog input signal that is periodic and has a high frequency.

[Background of the invention]

When sampling and digitizing a periodic analog signal SA with an A/D converter, the period TT is sufficiently larger than the sampling clock (period TS) as shown in Figure 1.
If a signal is input, the sampled and digitized digital data can be converted into the original analog signal by inputting it as is to the D/A converter. However, as shown in Figure 2, the digital data that is A/D converted by inputting a high frequency signal close to the Nyquist frequency is directly converted to D/D.
Even if it is converted to an analog signal with an A converter, the original waveform cannot be reproduced sufficiently.Also, even when performing digital signal processing on the obtained digital data, in the case of Figure 1, the data per input signal cycle is Although a large number of points can be obtained, in the case of a two-dimensional image, only a few points can be obtained, so there are drawbacks such as difficulty in obtaining the desired accuracy.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide a data sampling method that can reliably digitize even inputs close to the Nyquist frequency.

[Summary of the invention]

In order to achieve the above object, the present invention includes a memory that stores a digital code output from an A/D converter;
An address controller is provided to control the address of the memory, and an A/D converter samples the input signal over multiple periods, and then later converts each digital code into one of the input analog signals to a group of digital codes. The feature is that the original waveform can be restored by instructing where the waveform should be within the cycle using an address controller and storing data at a predetermined position or reading data from a predetermined position. be.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be explained according to the figures.
This figure shows sampling and rearrangement when data at N points are sampled over M cycles.

Input signal frequency is FT, sampling frequency is FS
If M and N are mutually prime integers, and MF'5
If a frequency relationship such that -NFT is maintained, N points are sampled during M cycles as described above, and points with the same phase are not sampled redundantly. Here, the same phase points refer to points where multiple cycles of the input signal overlap in one cycle. So now M-
Assuming 3°N-16, when the input signal AS in Figure 3 is sampled by the sampling clock, the output code DS will be an array of points PO to P16 as shown in the figure, but,
With this arrangement, the original waveform cannot be sufficiently reproduced because sampling is done sparsely. Therefore, when writing or reading this data into the memory, it is necessary to rearrange it as shown in the rearranged data DSI in Figure 3. Figure 4 shows an embodiment of the present invention for realizing the above-mentioned rearrangement. The signal As output from analog signal source 1 is A
The signal is input to the /D converter 2, converted into a digital quantity DS by the sampling clock SC from the clock generator 5, and written into the memory 3. The part surrounded by the broken line is the address controller 4 that is the object of the present invention, and when writing to or reading from the memory 3,
This is the part that generates addresses for sorting data. This address controller 4 includes a register 6 for providing the address jump amount for sorting, a register 7 for specifying the start address, an accumulator 8 for calculating the jump amount, a latch 9 for holding the calculation result, and a start address and register 7 for specifying the start address. Akie emulator 10 that adds jumpers
and a latch 11 that holds the result.

The operating principle of this circuit is as follows. Now, the input signal M
If eight samples are taken over a cycle and these N sample values are rearranged within one cycle period as shown in Figure 6, the time interval should be TT/N. However, the sampling interval is MTT/N, and the +1st sampling point Pk is at a time when -kM TT/N has elapsed from the first sampling point PO to τ.

The time points shifted by an integral multiple of TT are rearranged to the same time point within one cycle period (from τ to −(kM/N) TT of TT
It is sufficient to remove the integer part of the coefficients, which means that when the sampling point Pk is L -k M (modN) · fll, it will come to the time point LTT/N after reordering, that is, the L+1th position from the left. However, the equation A=B with mod N)
(modN) means that A-B is equal to an integral multiple of N.

Therefore, the first sampling point is 1 (= 00 sampling point PO, and at this time L = O (m Od N ), the amount is generally i + 1. If the sampling points that come i + 2nd are Pki and Pki + 1, respectively, then from equation (1) M k i w i (m o d N )-i21M
k i + 1- i + 1 (m o d N
) = (31, so formula +21.13) to M(k i + 1-k j )-1 (modN) ・
141 is obtained. Now, since we are considering M and N as relatively prime positive integers, there is an inverse number M-1 of M that satisfies the formula (41) and ki+
1-kismM-' (modN) = -(51, and this M-1 is a constant number that does not depend on i. Therefore, since it was 0!0 when i-wealth O, ki = 6 + M-'
As in r kl-', 1+ M-' r...
This can be obtained by sequentially dividing k, 1, l, . . . through M-. In the example of Figure 3, M-3, N-1
6, so M-' -11 (mod + 6), so kox O+ k, x 1 it k, x
22w6 (modl 6L l(, xl 7-+ (
mod'16), . . . The array of points Pk shown in the output code DS1 of Figure 3 is obtained.

Therefore, as can be seen from the above principle, in the initial state of the address controller 4 shown in Figure 4, the latches 9 and 11 are reset and their contents are set to 0, and the output of the register 6 (jump amount M-1) and the output 0 of the launch 9 are added in the accumulator 8 to give the first jump amount M'' to the latch 9, and the output 0 of the latch 9 and the start address which is the output of the register 7 are added in the accumulator 10. gives the start address to the latch 11. From this state, the latch pulse L synchronized with the sampling clock
When P is also output from the clock generator 5, the latch 11 holds the start address and outputs the start address to the memory 3. At the same time, the latch 9 also holds the first jump amount and outputs the jump amount to the Achiemulator 10. Then, the output of latch 9 (i.e., the first skip amount M-1)
and the output M-1 of the register 6 are added by the achievator 8, and the second skip amount 2M- is given to the latch 9. In addition, the output of latch 9 (first skip amount M-1) and register 7
The output of (start address 0) is added by the accumulator 10, and the address M'' to be accessed next is given to the latch 11. When the next latch pulse LP is output in this state, the above operation is performed and the next access is made. The address is output to memory 5.

When the address controller 4, which operates as described above, is used during sampling, first the sampling clock and latch pulse LP are output from the clock generator 5, and the A/D
A converter 2 converts the analog signal into a digital quantity DS, an address controller 4 calculates a desired address and provides it to the memory 3, and a sampling clock SC.

Write enable signal WE delayed by latch pulse LP
is output from the clock generator and data is written into the memory 3. By controlling the address in this way,
Data can be written into memory in a form that allows the original waveform to be restored.

Also, when writing, the arrangement remains as it was at sampling (PO, Pl
, P2. . . .)), and the read address may be controlled as described above.

As described above, in this embodiment, the data rearrangement is realized by hardware, and the data is rearranged at the time of writing or reading. can be restored.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, high-speed repetitive signals can be digitized reliably and in real time, and processing time can be shortened when used in digital sampling oscilloscopes, waveform digitizers, etc. There is an effect.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the operation when a signal with a frequency sufficiently lower than the sampling frequency of the A/D converter is sampled.
Figure 2 is an explanatory diagram of the operation when sampling a signal with a higher frequency than that in Figure 1, Figure 3 is an explanatory diagram of the operation of a method of sampling over multiple periods and rearranging the samples to obtain a digital signal equivalent to the original waveform. Figure 4 is a block diagram showing one conventional embodiment of the present invention. 2...A/D converter, 3...memory, 4...
Address controller, 5... Clock generator, 6.
...Address jump amount register, 7...Start address register, 8.10...Akie emulator, 9゜11
···latch.

Claims (1)

[Claims] An A/D converter that samples and digitizes periodic analog signals, and an A/D converter that samples and digitizes periodic analog signals, and
A memory for storing N sampled values (M is a positive integer that is relatively prime) and an address controller for controlling an address when accessing the memory are provided. , the address controller sets the first one as the first one, and the kth (k=0 to N-1) for an integer M^-^1 satisfying MM^-^1=1 with modulus N. The data sampling is characterized in that the order of the sampling values is rearranged so that the data is the (k-1)M^-^1st data in the modulus N of the sampling values, and then written to or read from the memory. Method.